1 /* $NetBSD: gemini_gmac.c,v 1.5 2010/01/19 22:06:19 pooka Exp $ */ 2 /*- 3 * Copyright (c) 2008 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas <matt@3am-software.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "locators.h" 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/kmem.h> 35 #include <sys/mbuf.h> 36 37 #include <net/if.h> 38 #include <net/if_ether.h> 39 40 #include <machine/bus.h> 41 42 #include <arm/gemini/gemini_reg.h> 43 #include <arm/gemini/gemini_obiovar.h> 44 #include <arm/gemini/gemini_gmacvar.h> 45 #include <arm/gemini/gemini_gpiovar.h> 46 47 #include <dev/mii/mii.h> 48 #include <dev/mii/mii_bitbang.h> 49 50 #include <sys/gpio.h> 51 52 __KERNEL_RCSID(0, "$NetBSD: gemini_gmac.c,v 1.5 2010/01/19 22:06:19 pooka Exp $"); 53 54 #define SWFREEQ_DESCS 256 /* one page worth */ 55 #define HWFREEQ_DESCS 256 /* one page worth */ 56 57 static int geminigmac_match(device_t, cfdata_t, void *); 58 static void geminigmac_attach(device_t, device_t, void *); 59 static int geminigmac_find(device_t, cfdata_t, const int *, void *); 60 static int geminigmac_print(void *aux, const char *name); 61 62 static int geminigmac_mii_readreg(device_t, int, int); 63 static void geminigmac_mii_writereg(device_t, int, int, int); 64 65 #define GPIO_MDIO 21 66 #define GPIO_MDCLK 22 67 68 #define MDIN __BIT(3) 69 #define MDOUT __BIT(2) 70 #define MDCLK __BIT(1) 71 #define MDTOPHY __BIT(0) 72 73 CFATTACH_DECL_NEW(geminigmac, sizeof(struct gmac_softc), 74 geminigmac_match, geminigmac_attach, NULL, NULL); 75 76 extern struct cfdriver geminigmac_cd; 77 extern struct cfdriver geminigpio_cd; 78 79 void 80 gmac_swfree_min_update(struct gmac_softc *sc) 81 { 82 uint32_t v; 83 84 if (sc->sc_swfreeq != NULL 85 && sc->sc_swfree_min > sc->sc_swfreeq->hwq_size - 1) 86 sc->sc_swfree_min = sc->sc_swfreeq->hwq_size - 1; 87 88 v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_QFE_THRESHOLD); 89 v &= ~QFE_SWFQ_THRESHOLD_MASK; 90 v |= QFE_SWFQ_THRESHOLD(sc->sc_swfree_min); 91 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_QFE_THRESHOLD, v); 92 } 93 94 void 95 gmac_intr_update(struct gmac_softc *sc) 96 { 97 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_MASK, 98 ~sc->sc_int_enabled[0]); 99 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT1_MASK, 100 ~sc->sc_int_enabled[1]); 101 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT2_MASK, 102 ~sc->sc_int_enabled[2]); 103 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT3_MASK, 104 ~sc->sc_int_enabled[3]); 105 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_MASK, 106 ~sc->sc_int_enabled[4]); 107 } 108 109 static void 110 gmac_init(struct gmac_softc *sc) 111 { 112 gmac_hwqmem_t *hqm; 113 114 /* 115 * This shouldn't be needed. 116 */ 117 for (bus_size_t i = 0; i < GMAC_TOE_QH_SIZE; i += 4) { 118 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 119 GMAC_TOE_QH_OFFSET + i, 0); 120 } 121 #if 0 122 { 123 bus_space_handle_t global_ioh; 124 int error; 125 126 error = bus_space_map(sc->sc_iot, GEMINI_GLOBAL_BASE, 4, 0, 127 &global_ioh); 128 KASSERT(error == 0); 129 aprint_normal_dev(sc->sc_dev, "gmac_init: global_ioh=%#zx\n", global_ioh); 130 bus_space_write_4(sc->sc_iot, global_ioh, GEMINI_GLOBAL_RESET_CTL, 131 GLOBAL_RESET_GMAC0|GLOBAL_RESET_GMAC1); 132 do { 133 v = bus_space_read_4(sc->sc_iot, global_ioh, 134 GEMINI_GLOBAL_RESET_CTL); 135 } while (v & (GLOBAL_RESET_GMAC0|GLOBAL_RESET_GMAC1)); 136 bus_space_unmap(sc->sc_iot, global_ioh, 4); 137 DELAY(1000); 138 } 139 #endif 140 141 sc->sc_swfree_min = 4; /* MIN_RXMAPS; */ 142 143 gmac_swfree_min_update(sc); 144 145 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_SKBSIZE, 146 SKB_SIZE_SET(PAGE_SIZE, MCLBYTES)); 147 148 sc->sc_int_select[0] = INT0_GMAC1; 149 sc->sc_int_select[1] = INT1_GMAC1; 150 sc->sc_int_select[2] = INT2_GMAC1; 151 sc->sc_int_select[3] = INT3_GMAC1; 152 sc->sc_int_select[4] = INT4_GMAC1; 153 154 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_SELECT, INT0_GMAC1); 155 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT1_SELECT, INT1_GMAC1); 156 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT2_SELECT, INT2_GMAC1); 157 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT3_SELECT, INT3_GMAC1); 158 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_SELECT, INT4_GMAC1); 159 160 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_STATUS, ~0); 161 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT1_STATUS, ~0); 162 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT2_STATUS, ~0); 163 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT3_STATUS, ~0); 164 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_STATUS, ~0); 165 166 gmac_intr_update(sc); 167 168 aprint_debug_dev(sc->sc_dev, "gmac_init: sts=%#x/%#x/%#x/%#x/%#x\n", 169 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_STATUS), 170 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT1_STATUS), 171 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT2_STATUS), 172 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT3_STATUS), 173 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_STATUS)); 174 175 aprint_debug_dev(sc->sc_dev, "gmac_init: mask=%#x/%#x/%#x/%#x/%#x\n", 176 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_MASK), 177 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT1_MASK), 178 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT2_MASK), 179 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT3_MASK), 180 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_MASK)); 181 182 aprint_debug_dev(sc->sc_dev, "gmac_init: select=%#x/%#x/%#x/%#x/%#x\n", 183 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_SELECT), 184 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT1_SELECT), 185 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT2_SELECT), 186 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT3_SELECT), 187 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_SELECT)); 188 189 aprint_debug_dev(sc->sc_dev, "gmac_init: create rx dmamap cache\n"); 190 /* 191 * Allocate the cache for receive dmamaps. 192 */ 193 sc->sc_rxmaps = gmac_mapcache_create(sc->sc_dmat, MAX_RXMAPS, 194 MCLBYTES, 1); 195 KASSERT(sc->sc_rxmaps != NULL); 196 197 aprint_debug_dev(sc->sc_dev, "gmac_init: create tx dmamap cache\n"); 198 /* 199 * Allocate the cache for transmit dmamaps. 200 */ 201 sc->sc_txmaps = gmac_mapcache_create(sc->sc_dmat, MAX_TXMAPS, 202 ETHERMTU_JUMBO + ETHER_HDR_LEN, 16); 203 KASSERT(sc->sc_txmaps != NULL); 204 205 aprint_debug_dev(sc->sc_dev, "gmac_init: create sw freeq\n"); 206 /* 207 * Allocate the memory for sw (receive) free queue 208 */ 209 hqm = gmac_hwqmem_create(sc->sc_rxmaps, 32 /*SWFREEQ_DESCS*/, 1, 210 HQM_PRODUCER|HQM_RX); 211 sc->sc_swfreeq = gmac_hwqueue_create(hqm, sc->sc_iot, sc->sc_ioh, 212 GMAC_SWFREEQ_RWPTR, GMAC_SWFREEQ_BASE, 0); 213 KASSERT(sc->sc_swfreeq != NULL); 214 215 aprint_debug_dev(sc->sc_dev, "gmac_init: create hw freeq\n"); 216 /* 217 * Allocate the memory for hw (receive) free queue 218 */ 219 hqm = gmac_hwqmem_create(sc->sc_rxmaps, HWFREEQ_DESCS, 1, 220 HQM_PRODUCER|HQM_RX); 221 sc->sc_hwfreeq = gmac_hwqueue_create(hqm, sc->sc_iot, sc->sc_ioh, 222 GMAC_HWFREEQ_RWPTR, GMAC_HWFREEQ_BASE, 0); 223 KASSERT(sc->sc_hwfreeq != NULL); 224 225 aprint_debug_dev(sc->sc_dev, "gmac_init: done\n"); 226 } 227 228 int 229 geminigmac_match(device_t parent, cfdata_t cf, void *aux) 230 { 231 struct obio_attach_args *obio = aux; 232 233 if (obio->obio_addr != GEMINI_GMAC_BASE) 234 return 0; 235 236 return 1; 237 } 238 239 void 240 geminigmac_attach(device_t parent, device_t self, void *aux) 241 { 242 struct gmac_softc *sc = device_private(self); 243 struct obio_attach_args *obio = aux; 244 struct gmac_attach_args gma; 245 cfdata_t cf; 246 uint32_t v; 247 int error; 248 249 sc->sc_dev = self; 250 sc->sc_iot = obio->obio_iot; 251 sc->sc_dmat = obio->obio_dmat; 252 sc->sc_gpio_dev = geminigpio_cd.cd_devs[0]; 253 sc->sc_gpio_mdclk = GPIO_MDCLK; 254 sc->sc_gpio_mdout = GPIO_MDIO; 255 sc->sc_gpio_mdin = GPIO_MDIO; 256 KASSERT(sc->sc_gpio_dev != NULL); 257 258 error = bus_space_map(sc->sc_iot, obio->obio_addr, obio->obio_size, 0, 259 &sc->sc_ioh); 260 if (error) { 261 aprint_error(": error mapping registers: %d", error); 262 return; 263 } 264 265 v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 0); 266 aprint_normal(": devid %d rev %d\n", GMAC_TOE_DEVID(v), 267 GMAC_TOE_REVID(v)); 268 aprint_naive("\n"); 269 270 mutex_init(&sc->sc_mdiolock, MUTEX_DEFAULT, IPL_NET); 271 272 /* 273 * Initialize the GPIO pins 274 */ 275 geminigpio_pin_ctl(sc->sc_gpio_dev, sc->sc_gpio_mdclk, GPIO_PIN_OUTPUT); 276 geminigpio_pin_ctl(sc->sc_gpio_dev, sc->sc_gpio_mdout, GPIO_PIN_OUTPUT); 277 if (sc->sc_gpio_mdout != sc->sc_gpio_mdin) 278 geminigpio_pin_ctl(sc->sc_gpio_dev, sc->sc_gpio_mdin, 279 GPIO_PIN_INPUT); 280 281 /* 282 * Set the MDIO GPIO pins to a known state. 283 */ 284 geminigpio_pin_write(sc->sc_gpio_dev, sc->sc_gpio_mdclk, 0); 285 geminigpio_pin_write(sc->sc_gpio_dev, sc->sc_gpio_mdout, 0); 286 sc->sc_mdiobits = MDCLK; 287 288 gmac_init(sc); 289 290 gma.gma_iot = sc->sc_iot; 291 gma.gma_ioh = sc->sc_ioh; 292 gma.gma_dmat = sc->sc_dmat; 293 294 gma.gma_mii_readreg = geminigmac_mii_readreg; 295 gma.gma_mii_writereg = geminigmac_mii_writereg; 296 297 gma.gma_port = 0; 298 gma.gma_phy = -1; 299 gma.gma_intr = 1; 300 301 cf = config_search_ia(geminigmac_find, sc->sc_dev, 302 geminigmac_cd.cd_name, &gma); 303 if (cf != NULL) 304 config_attach(sc->sc_dev, cf, &gma, geminigmac_print); 305 306 gma.gma_port = 1; 307 gma.gma_phy = -1; 308 gma.gma_intr = 2; 309 310 cf = config_search_ia(geminigmac_find, sc->sc_dev, 311 geminigmac_cd.cd_name, &gma); 312 if (cf != NULL) 313 config_attach(sc->sc_dev, cf, &gma, geminigmac_print); 314 } 315 316 static int 317 geminigmac_find(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 318 { 319 struct gmac_attach_args * const gma = aux; 320 321 if (gma->gma_port != cf->cf_loc[GEMINIGMACCF_PORT]) 322 return 0; 323 if (gma->gma_intr != cf->cf_loc[GEMINIGMACCF_INTR]) 324 return 0; 325 326 gma->gma_phy = cf->cf_loc[GEMINIGMACCF_PHY]; 327 gma->gma_intr = cf->cf_loc[GEMINIGMACCF_INTR]; 328 329 return config_match(parent, cf, gma); 330 } 331 332 static int 333 geminigmac_print(void *aux, const char *name) 334 { 335 struct gmac_attach_args * const gma = aux; 336 337 aprint_normal(" port %d", gma->gma_port); 338 aprint_normal(" phy %d", gma->gma_phy); 339 aprint_normal(" intr %d", gma->gma_intr); 340 341 return UNCONF; 342 } 343 344 static uint32_t 345 gemini_gmac_gpio_read(device_t dv) 346 { 347 struct gmac_softc * const sc = device_private(dv); 348 int value = geminigpio_pin_read(sc->sc_gpio_dev, GPIO_MDIO); 349 350 KASSERT((sc->sc_mdiobits & MDTOPHY) == 0); 351 352 return value ? MDIN : 0; 353 } 354 355 static void 356 gemini_gmac_gpio_write(device_t dv, uint32_t bits) 357 { 358 struct gmac_softc * const sc = device_private(dv); 359 360 if ((sc->sc_mdiobits ^ bits) & MDTOPHY) { 361 int flags = (bits & MDTOPHY) ? GPIO_PIN_OUTPUT : GPIO_PIN_INPUT; 362 geminigpio_pin_ctl(sc->sc_gpio_dev, GPIO_MDIO, flags); 363 } 364 365 if ((sc->sc_mdiobits ^ bits) & MDOUT) { 366 int flags = ((bits & MDOUT) != 0); 367 geminigpio_pin_write(sc->sc_gpio_dev, GPIO_MDIO, flags); 368 } 369 370 if ((sc->sc_mdiobits ^ bits) & MDCLK) { 371 int flags = ((bits & MDCLK) != 0); 372 geminigpio_pin_write(sc->sc_gpio_dev, GPIO_MDCLK, flags); 373 } 374 375 sc->sc_mdiobits = bits; 376 } 377 378 static const struct mii_bitbang_ops geminigmac_mii_bitbang_ops = { 379 .mbo_read = gemini_gmac_gpio_read, 380 .mbo_write = gemini_gmac_gpio_write, 381 .mbo_bits[MII_BIT_MDO] = MDOUT, 382 .mbo_bits[MII_BIT_MDI] = MDIN, 383 .mbo_bits[MII_BIT_MDC] = MDCLK, 384 .mbo_bits[MII_BIT_DIR_HOST_PHY] = MDTOPHY, 385 }; 386 387 int 388 geminigmac_mii_readreg(device_t dv, int phy, int reg) 389 { 390 device_t parent = device_parent(dv); 391 struct gmac_softc * const sc = device_private(parent); 392 int rv; 393 394 mutex_enter(&sc->sc_mdiolock); 395 rv = mii_bitbang_readreg(parent, &geminigmac_mii_bitbang_ops, phy, reg); 396 mutex_exit(&sc->sc_mdiolock); 397 398 //aprint_debug_dev(dv, "mii_readreg(%d, %d): %#x\n", phy, reg, rv); 399 400 return rv; 401 } 402 403 void 404 geminigmac_mii_writereg(device_t dv, int phy, int reg, int val) 405 { 406 device_t parent = device_parent(dv); 407 struct gmac_softc * const sc = device_private(parent); 408 409 //aprint_debug_dev(dv, "mii_writereg(%d, %d, %#x)\n", phy, reg, val); 410 411 mutex_enter(&sc->sc_mdiolock); 412 mii_bitbang_writereg(parent, &geminigmac_mii_bitbang_ops, phy, reg, val); 413 mutex_exit(&sc->sc_mdiolock); 414 } 415 416 417 gmac_mapcache_t * 418 gmac_mapcache_create(bus_dma_tag_t dmat, size_t maxmaps, bus_size_t mapsize, 419 int nsegs) 420 { 421 gmac_mapcache_t *mc; 422 423 mc = kmem_zalloc(offsetof(gmac_mapcache_t, mc_maps[maxmaps]), 424 KM_SLEEP); 425 if (mc == NULL) 426 return NULL; 427 428 mc->mc_max = maxmaps; 429 mc->mc_dmat = dmat; 430 mc->mc_mapsize = mapsize; 431 mc->mc_nsegs = nsegs; 432 return mc; 433 } 434 435 void 436 gmac_mapcache_destroy(gmac_mapcache_t **mc_p) 437 { 438 gmac_mapcache_t *mc = *mc_p; 439 440 if (mc == NULL) 441 return; 442 443 KASSERT(mc->mc_used == 0); 444 while (mc->mc_free-- > 0) { 445 KASSERT(mc->mc_maps[mc->mc_free] != NULL); 446 bus_dmamap_destroy(mc->mc_dmat, mc->mc_maps[mc->mc_free]); 447 mc->mc_maps[mc->mc_free] = NULL; 448 } 449 450 kmem_free(mc, offsetof(gmac_mapcache_t, mc_maps[mc->mc_max])); 451 *mc_p = NULL; 452 } 453 454 int 455 gmac_mapcache_fill(gmac_mapcache_t *mc, size_t limit) 456 { 457 int error; 458 459 KASSERT(limit <= mc->mc_max); 460 aprint_debug("gmac_mapcache_fill(%p): limit=%zu used=%zu free=%zu\n", 461 mc, limit, mc->mc_used, mc->mc_free); 462 463 for (error = 0; mc->mc_free + mc->mc_used < limit; mc->mc_free++) { 464 KASSERT(mc->mc_maps[mc->mc_free] == NULL); 465 error = bus_dmamap_create(mc->mc_dmat, mc->mc_mapsize, 466 mc->mc_nsegs, mc->mc_mapsize, 0, 467 BUS_DMA_ALLOCNOW|BUS_DMA_WAITOK, 468 &mc->mc_maps[mc->mc_free]); 469 if (error) 470 break; 471 } 472 aprint_debug("gmac_mapcache_fill(%p): limit=%zu used=%zu free=%zu\n", 473 mc, limit, mc->mc_used, mc->mc_free); 474 475 return error; 476 } 477 478 bus_dmamap_t 479 gmac_mapcache_get(gmac_mapcache_t *mc) 480 { 481 bus_dmamap_t map; 482 483 KASSERT(mc != NULL); 484 485 if (mc->mc_free == 0) { 486 int error; 487 if (mc->mc_used == mc->mc_max) 488 return NULL; 489 error = bus_dmamap_create(mc->mc_dmat, mc->mc_mapsize, 490 mc->mc_nsegs, mc->mc_mapsize, 0, 491 BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, 492 &map); 493 if (error) 494 return NULL; 495 KASSERT(mc->mc_maps[mc->mc_free] == NULL); 496 } else { 497 KASSERT(mc->mc_free <= mc->mc_max); 498 map = mc->mc_maps[--mc->mc_free]; 499 mc->mc_maps[mc->mc_free] = NULL; 500 } 501 mc->mc_used++; 502 KASSERT(map != NULL); 503 504 return map; 505 } 506 507 void 508 gmac_mapcache_put(gmac_mapcache_t *mc, bus_dmamap_t map) 509 { 510 KASSERT(mc->mc_free + mc->mc_used < mc->mc_max); 511 KASSERT(mc->mc_maps[mc->mc_free] == NULL); 512 513 mc->mc_maps[mc->mc_free++] = map; 514 mc->mc_used--; 515 } 516 517 gmac_desc_t * 518 gmac_hwqueue_desc(gmac_hwqueue_t *hwq, size_t i) 519 { 520 i += hwq->hwq_wptr; 521 if (i >= hwq->hwq_size) 522 i -= hwq->hwq_size; 523 return hwq->hwq_base + i; 524 } 525 526 static void 527 gmac_hwqueue_txconsume(gmac_hwqueue_t *hwq, const gmac_desc_t *d) 528 { 529 gmac_hwqmem_t * const hqm = hwq->hwq_hqm; 530 struct ifnet *ifp; 531 bus_dmamap_t map; 532 struct mbuf *m; 533 534 IF_DEQUEUE(&hwq->hwq_ifq, m); 535 KASSERT(m != NULL); 536 map = M_GETCTX(m, bus_dmamap_t); 537 538 bus_dmamap_sync(hqm->hqm_dmat, map, 0, map->dm_mapsize, 539 BUS_DMASYNC_POSTWRITE); 540 bus_dmamap_unload(hqm->hqm_dmat, map); 541 M_SETCTX(m, NULL); 542 gmac_mapcache_put(hqm->hqm_mc, map); 543 544 ifp = hwq->hwq_ifp; 545 ifp->if_opackets++; 546 ifp->if_obytes += m->m_pkthdr.len; 547 548 aprint_debug("gmac_hwqueue_txconsume(%p): %zu@%p: %s m=%p\n", 549 hwq, d - hwq->hwq_base, d, ifp->if_xname, m); 550 551 if (ifp->if_bpf) 552 bpf_ops->bpf_mtap(ifp->if_bpf, m); 553 m_freem(m); 554 } 555 556 void 557 gmac_hwqueue_sync(gmac_hwqueue_t *hwq) 558 { 559 gmac_hwqmem_t * const hqm = hwq->hwq_hqm; 560 uint32_t v; 561 uint16_t old_rptr; 562 size_t rptr; 563 564 KASSERT(hqm->hqm_flags & HQM_PRODUCER); 565 566 old_rptr = hwq->hwq_rptr; 567 v = bus_space_read_4(hwq->hwq_iot, hwq->hwq_qrwptr_ioh, 0); 568 hwq->hwq_rptr = (v >> 0) & 0xffff; 569 hwq->hwq_wptr = (v >> 16) & 0xffff; 570 571 if (old_rptr == hwq->hwq_rptr) 572 return; 573 574 aprint_debug("gmac_hwqueue_sync(%p): entry rptr old=%u new=%u free=%u(%u)\n", 575 hwq, old_rptr, hwq->hwq_rptr, hwq->hwq_free, 576 hwq->hwq_size - hwq->hwq_free - 1); 577 578 hwq->hwq_free += (hwq->hwq_rptr - old_rptr) & (hwq->hwq_size - 1); 579 for (rptr = old_rptr; 580 rptr != hwq->hwq_rptr; 581 rptr = (rptr + 1) & (hwq->hwq_size - 1)) { 582 gmac_desc_t * const d = hwq->hwq_base + rptr; 583 if (hqm->hqm_flags & HQM_TX) { 584 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 585 sizeof(gmac_desc_t [hwq->hwq_qoff + rptr]), 586 sizeof(gmac_desc_t), 587 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 588 if (d->d_desc3 & htole32(DESC3_EOF)) 589 gmac_hwqueue_txconsume(hwq, d); 590 } else { 591 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 592 sizeof(gmac_desc_t [hwq->hwq_qoff + rptr]), 593 sizeof(gmac_desc_t), 594 BUS_DMASYNC_POSTWRITE); 595 596 aprint_debug("gmac_hwqueue_sync(%p): %zu@%p=%#x/%#x/%#x/%#x\n", 597 hwq, rptr, d, d->d_desc0, d->d_desc1, 598 d->d_bufaddr, d->d_desc3); 599 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 600 sizeof(gmac_desc_t [hwq->hwq_qoff + rptr]), 601 sizeof(gmac_desc_t), 602 BUS_DMASYNC_PREWRITE); 603 } 604 } 605 606 aprint_debug("gmac_hwqueue_sync(%p): exit rptr old=%u new=%u free=%u(%u)\n", 607 hwq, old_rptr, hwq->hwq_rptr, hwq->hwq_free, 608 hwq->hwq_size - hwq->hwq_free - 1); 609 } 610 611 void 612 gmac_hwqueue_produce(gmac_hwqueue_t *hwq, size_t count) 613 { 614 gmac_hwqmem_t * const hqm = hwq->hwq_hqm; 615 uint16_t wptr; 616 uint16_t rptr = bus_space_read_4(hwq->hwq_iot, hwq->hwq_qrwptr_ioh, 0); 617 618 KASSERT(count < hwq->hwq_free); 619 KASSERT(hqm->hqm_flags & HQM_PRODUCER); 620 KASSERT(hwq->hwq_wptr == bus_space_read_4(hwq->hwq_iot, hwq->hwq_qrwptr_ioh, 0) >> 16); 621 622 aprint_debug("gmac_hwqueue_produce(%p, %zu): rptr=%u(%u) wptr old=%u", 623 hwq, count, hwq->hwq_rptr, rptr, hwq->hwq_wptr); 624 625 hwq->hwq_free -= count; 626 #if 1 627 for (wptr = hwq->hwq_wptr; 628 count > 0; 629 count--, wptr = (wptr + 1) & (hwq->hwq_size - 1)) { 630 KASSERT(((wptr + 1) & (hwq->hwq_size - 1)) != hwq->hwq_rptr); 631 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 632 sizeof(gmac_desc_t [hwq->hwq_qoff + wptr]), 633 sizeof(gmac_desc_t), 634 BUS_DMASYNC_PREWRITE); 635 } 636 KASSERT(count == 0); 637 hwq->hwq_wptr = wptr; 638 #else 639 if (hwq->hwq_wptr + count >= hwq->hwq_size) { 640 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 641 sizeof(gmac_desc_t [hwq->hwq_qoff + hwq->hwq_wptr]), 642 sizeof(gmac_desc_t [hwq->hwq_size - hwq->hwq_wptr]), 643 BUS_DMASYNC_PREWRITE); 644 count -= hwq->hwq_size - hwq->hwq_wptr; 645 hwq->hwq_wptr = 0; 646 } 647 if (count > 0) { 648 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 649 sizeof(gmac_desc_t [hwq->hwq_qoff + hwq->hwq_wptr]), 650 sizeof(gmac_desc_t [count]), 651 BUS_DMASYNC_PREWRITE); 652 hwq->hwq_wptr += count; 653 hwq->hwq_wptr &= (hwq->hwq_size - 1); 654 } 655 #endif 656 657 /* 658 * Tell the h/w we've produced a few more descriptors. 659 * (don't bother writing the rptr since it's RO). 660 */ 661 bus_space_write_4(hwq->hwq_iot, hwq->hwq_qrwptr_ioh, 0, 662 hwq->hwq_wptr << 16); 663 664 aprint_debug(" new=%u\n", hwq->hwq_wptr); 665 } 666 667 size_t 668 gmac_rxproduce(gmac_hwqueue_t *hwq, size_t free_min) 669 { 670 gmac_hwqmem_t * const hqm = hwq->hwq_hqm; 671 size_t i; 672 673 aprint_debug("gmac_rxproduce(%p): entry free=%u(%u) free_min=%zu ifq_len=%d\n", 674 hwq, hwq->hwq_free, hwq->hwq_size - hwq->hwq_free - 1, 675 free_min, hwq->hwq_ifq.ifq_len); 676 677 gmac_hwqueue_sync(hwq); 678 679 aprint_debug("gmac_rxproduce(%p): postsync free=%u(%u)\n", 680 hwq, hwq->hwq_free, hwq->hwq_size - hwq->hwq_free - 1); 681 682 for (i = 0; hwq->hwq_free > 0 && hwq->hwq_size - hwq->hwq_free - 1 < free_min; i++) { 683 bus_dmamap_t map; 684 gmac_desc_t * const d = gmac_hwqueue_desc(hwq, 0); 685 struct mbuf *m, *m0; 686 int error; 687 688 if (d->d_bufaddr && (le32toh(d->d_bufaddr) >> 16) != 0xdead) { 689 gmac_hwqueue_produce(hwq, 1); 690 continue; 691 } 692 693 map = gmac_mapcache_get(hqm->hqm_mc); 694 if (map == NULL) 695 break; 696 697 KASSERT(map->dm_mapsize == 0); 698 699 m = m_gethdr(MT_DATA, M_DONTWAIT); 700 if (m == NULL) { 701 gmac_mapcache_put(hqm->hqm_mc, map); 702 break; 703 } 704 705 MCLGET(m, M_DONTWAIT); 706 if ((m->m_flags & M_EXT) == 0) { 707 m_free(m); 708 gmac_mapcache_put(hqm->hqm_mc, map); 709 break; 710 } 711 error = bus_dmamap_load(hqm->hqm_dmat, map, m->m_data, 712 MCLBYTES, NULL, BUS_DMA_READ|BUS_DMA_NOWAIT); 713 if (error) { 714 m_free(m); 715 gmac_mapcache_put(hqm->hqm_mc, map); 716 aprint_error("gmac0: " 717 "map %p(%zu): can't map rx mbuf(%p) wptr=%u: %d\n", 718 map, map->_dm_size, m, hwq->hwq_wptr, error); 719 Debugger(); 720 break; 721 } 722 bus_dmamap_sync(hqm->hqm_dmat, map, 0, map->dm_mapsize, 723 BUS_DMASYNC_PREREAD); 724 m->m_pkthdr.len = 0; 725 M_SETCTX(m, map); 726 #if 0 727 d->d_desc0 = htole32(map->dm_segs->ds_len); 728 #endif 729 d->d_bufaddr = htole32(map->dm_segs->ds_addr); 730 for (m0 = hwq->hwq_ifq.ifq_head; m0 != NULL; m0 = m0->m_nextpkt) 731 KASSERT(m0 != m); 732 IF_ENQUEUE(&hwq->hwq_ifq, m); 733 m->m_len = d - hwq->hwq_base; 734 aprint_debug( 735 "gmac_rxproduce(%p): m=%p %zu@%p=%#x/%#x/%#x/%#x\n", hwq, 736 m, d - hwq->hwq_base, d, d->d_desc0, d->d_desc1, 737 d->d_bufaddr, d->d_desc3); 738 gmac_hwqueue_produce(hwq, 1); 739 } 740 741 aprint_debug("gmac_rxproduce(%p): exit free=%u(%u) free_min=%zu ifq_len=%d\n", 742 hwq, hwq->hwq_free, hwq->hwq_size - hwq->hwq_free - 1, 743 free_min, hwq->hwq_ifq.ifq_len); 744 745 return i; 746 } 747 748 static bool 749 gmac_hwqueue_rxconsume(gmac_hwqueue_t *hwq, const gmac_desc_t *d) 750 { 751 gmac_hwqmem_t * const hqm = hwq->hwq_hqm; 752 struct ifnet * const ifp = hwq->hwq_ifp; 753 size_t buflen = d->d_desc1 & 0xffff; 754 bus_dmamap_t map; 755 struct mbuf *m, *last_m, **mp; 756 size_t depth; 757 758 KASSERT(ifp != NULL); 759 760 aprint_debug("gmac_hwqueue_rxconsume(%p): entry\n", hwq); 761 762 aprint_debug("gmac_hwqueue_rxconsume(%p): ifp=%p(%s): %#x/%#x/%#x/%#x\n", 763 hwq, hwq->hwq_ifp, hwq->hwq_ifp->if_xname, 764 d->d_desc0, d->d_desc1, d->d_bufaddr, d->d_desc3); 765 766 if (d->d_bufaddr == 0 || d->d_bufaddr == 0xdeadbeef) 767 return false; 768 769 /* 770 * First we have to find this mbuf in the software free queue 771 * (the producer of the mbufs) and remove it. 772 */ 773 KASSERT(hwq->hwq_producer->hwq_free != hwq->hwq_producer->hwq_size - 1); 774 for (mp = &hwq->hwq_producer->hwq_ifq.ifq_head, last_m = NULL, depth=0; 775 (m = *mp) != NULL; 776 last_m = m, mp = &m->m_nextpkt, depth++) { 777 map = M_GETCTX(m, bus_dmamap_t); 778 KASSERT(map != NULL); 779 KASSERT(map->dm_nsegs == 1); 780 aprint_debug("gmac_hwqueue_rxconsume(%p): ifq[%zu]=%p(@%#zx) %d@swfq\n", 781 hwq, depth, m, map->dm_segs->ds_addr, m->m_len); 782 if (le32toh(d->d_bufaddr) == map->dm_segs->ds_addr) { 783 *mp = m->m_nextpkt; 784 if (hwq->hwq_producer->hwq_ifq.ifq_tail == m) 785 hwq->hwq_producer->hwq_ifq.ifq_tail = last_m; 786 hwq->hwq_producer->hwq_ifq.ifq_len--; 787 break; 788 } 789 } 790 aprint_debug("gmac_hwqueue_rxconsume(%p): ifp=%p(%s) m=%p@%zu", 791 hwq, hwq->hwq_ifp, hwq->hwq_ifp->if_xname, m, depth); 792 if (m) 793 aprint_debug(" swfq[%d]=%#x\n", m->m_len, 794 hwq->hwq_producer->hwq_base[m->m_len].d_bufaddr); 795 aprint_debug("\n"); 796 KASSERT(m != NULL); 797 798 { 799 struct mbuf *m0; 800 for (m0 = hwq->hwq_producer->hwq_ifq.ifq_head; m0 != NULL; m0 = m0->m_nextpkt) 801 KASSERT(m0 != m); 802 } 803 804 KASSERT(hwq->hwq_producer->hwq_base[m->m_len].d_bufaddr == d->d_bufaddr); 805 hwq->hwq_producer->hwq_base[m->m_len].d_bufaddr = htole32(0xdead0000 | m->m_len); 806 807 m->m_len = buflen; 808 if (d->d_desc3 & DESC3_SOF) { 809 KASSERT(hwq->hwq_rxmbuf == NULL); 810 m->m_pkthdr.len = buflen; 811 buflen += 2; /* account for the pad */ 812 /* only modify m->m_data after we know mbuf is good. */ 813 } else { 814 KASSERT(hwq->hwq_rxmbuf != NULL); 815 hwq->hwq_rxmbuf->m_pkthdr.len += buflen; 816 } 817 818 map = M_GETCTX(m, bus_dmamap_t); 819 820 /* 821 * Sync the buffer contents, unload the dmamap, and save it away. 822 */ 823 bus_dmamap_sync(hqm->hqm_dmat, map, 0, buflen, BUS_DMASYNC_POSTREAD); 824 bus_dmamap_unload(hqm->hqm_dmat, map); 825 M_SETCTX(m, NULL); 826 gmac_mapcache_put(hqm->hqm_mc, map); 827 828 /* 829 * Now we build our new packet chain by tacking this on the end. 830 */ 831 *hwq->hwq_mp = m; 832 if ((d->d_desc3 & DESC3_EOF) == 0) { 833 /* 834 * Not last frame, so make sure the next gets appended right. 835 */ 836 hwq->hwq_mp = &m->m_next; 837 return true; 838 } 839 840 #if 0 841 /* 842 * We have a complete frame, let's try to deliver it. 843 */ 844 m->m_len -= ETHER_CRC_LEN; /* remove the CRC from the end */ 845 #endif 846 847 /* 848 * Now get the whole chain. 849 */ 850 m = hwq->hwq_rxmbuf; 851 m->m_pkthdr.rcvif = ifp; /* set receive interface */ 852 ifp->if_ipackets++; 853 ifp->if_ibytes += m->m_pkthdr.len; 854 switch (DESC0_RXSTS_GET(d->d_desc0)) { 855 case DESC0_RXSTS_GOOD: 856 case DESC0_RXSTS_LONG: 857 m->m_data += 2; 858 KASSERT(m_length(m) == m->m_pkthdr.len); 859 if (ifp->if_bpf) 860 bpf_ops->bpf_mtap(ifp->if_bpf, m); 861 (*ifp->if_input)(ifp, m); 862 break; 863 default: 864 ifp->if_ierrors++; 865 m_freem(m); 866 break; 867 } 868 hwq->hwq_rxmbuf = NULL; 869 hwq->hwq_mp = &hwq->hwq_rxmbuf; 870 871 return true; 872 } 873 874 size_t 875 gmac_hwqueue_consume(gmac_hwqueue_t *hwq, size_t free_min) 876 { 877 gmac_hwqmem_t * const hqm = hwq->hwq_hqm; 878 gmac_desc_t d; 879 uint32_t v; 880 uint16_t rptr; 881 size_t i; 882 883 KASSERT((hqm->hqm_flags & HQM_PRODUCER) == 0); 884 885 aprint_debug("gmac_hwqueue_consume(%p): entry\n", hwq); 886 887 888 v = bus_space_read_4(hwq->hwq_iot, hwq->hwq_qrwptr_ioh, 0); 889 rptr = (v >> 0) & 0xffff; 890 hwq->hwq_wptr = (v >> 16) & 0xffff; 891 KASSERT(rptr == hwq->hwq_rptr); 892 if (rptr == hwq->hwq_wptr) 893 return 0; 894 895 i = 0; 896 for (; rptr != hwq->hwq_wptr; rptr = (rptr + 1) & (hwq->hwq_size - 1)) { 897 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 898 sizeof(gmac_desc_t [hwq->hwq_qoff + rptr]), 899 sizeof(gmac_desc_t), 900 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 901 d.d_desc0 = le32toh(hwq->hwq_base[rptr].d_desc0); 902 d.d_desc1 = le32toh(hwq->hwq_base[rptr].d_desc1); 903 d.d_bufaddr = le32toh(hwq->hwq_base[rptr].d_bufaddr); 904 d.d_desc3 = le32toh(hwq->hwq_base[rptr].d_desc3); 905 hwq->hwq_base[rptr].d_desc0 = 0; 906 hwq->hwq_base[rptr].d_desc1 = 0; 907 hwq->hwq_base[rptr].d_bufaddr = 0xdeadbeef; 908 hwq->hwq_base[rptr].d_desc3 = 0; 909 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 910 sizeof(gmac_desc_t [hwq->hwq_qoff + rptr]), 911 sizeof(gmac_desc_t), 912 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 913 914 aprint_debug("gmac_hwqueue_consume(%p): rptr=%u\n", 915 hwq, rptr); 916 if (!gmac_hwqueue_rxconsume(hwq, &d)) { 917 rptr = (rptr + 1) & (hwq->hwq_size - 1); 918 i += gmac_rxproduce(hwq->hwq_producer, free_min); 919 break; 920 } 921 } 922 923 /* 924 * Update hardware's copy of rptr. (wptr is RO). 925 */ 926 aprint_debug("gmac_hwqueue_consume(%p): rptr old=%u new=%u wptr=%u\n", 927 hwq, hwq->hwq_rptr, rptr, hwq->hwq_wptr); 928 bus_space_write_4(hwq->hwq_iot, hwq->hwq_qrwptr_ioh, 0, rptr); 929 hwq->hwq_rptr = rptr; 930 931 aprint_debug("gmac_hwqueue_consume(%p): exit\n", hwq); 932 933 return i; 934 } 935 936 void 937 gmac_hwqmem_destroy(gmac_hwqmem_t *hqm) 938 { 939 if (hqm->hqm_nsegs) { 940 if (hqm->hqm_base) { 941 if (hqm->hqm_dmamap) { 942 if (hqm->hqm_dmamap->dm_mapsize) { 943 bus_dmamap_unload(hqm->hqm_dmat, 944 hqm->hqm_dmamap); 945 } 946 bus_dmamap_destroy(hqm->hqm_dmat, 947 hqm->hqm_dmamap); 948 } 949 bus_dmamem_unmap(hqm->hqm_dmat, hqm->hqm_base, 950 hqm->hqm_memsize); 951 } 952 bus_dmamem_free(hqm->hqm_dmat, hqm->hqm_segs, hqm->hqm_nsegs); 953 } 954 955 kmem_free(hqm, sizeof(*hqm)); 956 } 957 958 gmac_hwqmem_t * 959 gmac_hwqmem_create(gmac_mapcache_t *mc, size_t ndesc, size_t nqueue, int flags) 960 { 961 gmac_hwqmem_t *hqm; 962 int error; 963 964 KASSERT(ndesc > 0 && ndesc <= 2048); 965 KASSERT((ndesc & (ndesc - 1)) == 0); 966 967 hqm = kmem_zalloc(sizeof(*hqm), KM_SLEEP); 968 if (hqm == NULL) 969 return NULL; 970 971 hqm->hqm_memsize = nqueue * sizeof(gmac_desc_t [ndesc]); 972 hqm->hqm_mc = mc; 973 hqm->hqm_dmat = mc->mc_dmat; 974 hqm->hqm_ndesc = ndesc; 975 hqm->hqm_nqueue = nqueue; 976 hqm->hqm_flags = flags; 977 978 error = bus_dmamem_alloc(hqm->hqm_dmat, hqm->hqm_memsize, 0, 0, 979 hqm->hqm_segs, 1, &hqm->hqm_nsegs, BUS_DMA_WAITOK); 980 if (error) { 981 KASSERT(error == 0); 982 goto failed; 983 } 984 KASSERT(hqm->hqm_nsegs == 1); 985 error = bus_dmamem_map(hqm->hqm_dmat, hqm->hqm_segs, hqm->hqm_nsegs, 986 hqm->hqm_memsize, (void **)&hqm->hqm_base, BUS_DMA_WAITOK); 987 if (error) { 988 KASSERT(error == 0); 989 goto failed; 990 } 991 error = bus_dmamap_create(hqm->hqm_dmat, hqm->hqm_memsize, 992 hqm->hqm_nsegs, hqm->hqm_memsize, 0, 993 BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW, &hqm->hqm_dmamap); 994 if (error) { 995 KASSERT(error == 0); 996 goto failed; 997 } 998 error = bus_dmamap_load(hqm->hqm_dmat, hqm->hqm_dmamap, hqm->hqm_base, 999 hqm->hqm_memsize, NULL, 1000 BUS_DMA_WAITOK|BUS_DMA_WRITE|BUS_DMA_READ|BUS_DMA_COHERENT); 1001 if (error) { 1002 aprint_debug("gmac_hwqmem_create: ds_addr=%zu ds_len=%zu\n", 1003 hqm->hqm_segs->ds_addr, hqm->hqm_segs->ds_len); 1004 aprint_debug("gmac_hwqmem_create: bus_dmamap_load: %d\n", error); 1005 KASSERT(error == 0); 1006 goto failed; 1007 } 1008 1009 memset(hqm->hqm_base, 0, hqm->hqm_memsize); 1010 if ((flags & HQM_PRODUCER) == 0) 1011 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 0, 1012 hqm->hqm_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1013 1014 return hqm; 1015 1016 failed: 1017 gmac_hwqmem_destroy(hqm); 1018 return NULL; 1019 } 1020 1021 void 1022 gmac_hwqueue_destroy(gmac_hwqueue_t *hwq) 1023 { 1024 gmac_hwqmem_t * const hqm = hwq->hwq_hqm; 1025 KASSERT(hqm->hqm_refs & hwq->hwq_ref); 1026 hqm->hqm_refs &= ~hwq->hwq_ref; 1027 for (;;) { 1028 struct mbuf *m; 1029 bus_dmamap_t map; 1030 IF_DEQUEUE(&hwq->hwq_ifq, m); 1031 if (m == NULL) 1032 break; 1033 map = M_GETCTX(m, bus_dmamap_t); 1034 bus_dmamap_unload(hqm->hqm_dmat, map); 1035 gmac_mapcache_put(hqm->hqm_mc, map); 1036 m_freem(m); 1037 } 1038 kmem_free(hwq, sizeof(*hwq)); 1039 } 1040 1041 gmac_hwqueue_t * 1042 gmac_hwqueue_create(gmac_hwqmem_t *hqm, 1043 bus_space_tag_t iot, bus_space_handle_t ioh, 1044 bus_size_t qrwptr, bus_size_t qbase, 1045 size_t qno) 1046 { 1047 const size_t log2_memsize = ffs(hqm->hqm_ndesc) - 1; 1048 gmac_hwqueue_t *hwq; 1049 uint32_t v; 1050 1051 KASSERT(qno < hqm->hqm_nqueue); 1052 KASSERT((hqm->hqm_refs & (1 << qno)) == 0); 1053 1054 hwq = kmem_zalloc(sizeof(*hwq), KM_SLEEP); 1055 if (hwq == NULL) 1056 return NULL; 1057 1058 hwq->hwq_size = hqm->hqm_ndesc; 1059 1060 hwq->hwq_iot = iot; 1061 bus_space_subregion(iot, ioh, qrwptr, sizeof(uint32_t), 1062 &hwq->hwq_qrwptr_ioh); 1063 1064 hwq->hwq_hqm = hqm; 1065 hwq->hwq_ref = 1 << qno; 1066 hqm->hqm_refs |= hwq->hwq_ref; 1067 hwq->hwq_qoff = hqm->hqm_ndesc * qno; 1068 hwq->hwq_base = hqm->hqm_base + hwq->hwq_qoff; 1069 1070 if (qno == 0) { 1071 bus_space_write_4(hwq->hwq_iot, ioh, qbase, 1072 hqm->hqm_dmamap->dm_segs[0].ds_addr | (log2_memsize)); 1073 } 1074 1075 v = bus_space_read_4(hwq->hwq_iot, hwq->hwq_qrwptr_ioh, 0); 1076 hwq->hwq_rptr = (v >> 0) & 0xffff; 1077 hwq->hwq_wptr = (v >> 16) & 0xffff; 1078 1079 aprint_debug("gmac_hwqueue_create: %p: qrwptr=%zu(%#zx) wptr=%u rptr=%u" 1080 " base=%p@%#zx(%#x) qno=%zu\n", 1081 hwq, qrwptr, hwq->hwq_qrwptr_ioh, hwq->hwq_wptr, hwq->hwq_rptr, 1082 hwq->hwq_base, 1083 hqm->hqm_segs->ds_addr + sizeof(gmac_desc_t [hwq->hwq_qoff]), 1084 bus_space_read_4(hwq->hwq_iot, ioh, qbase), qno); 1085 1086 hwq->hwq_free = hwq->hwq_size - 1; 1087 hwq->hwq_ifq.ifq_maxlen = hwq->hwq_free; 1088 hwq->hwq_mp = &hwq->hwq_rxmbuf; 1089 1090 return hwq; 1091 } 1092