xref: /netbsd-src/sys/arch/arm/footbridge/footbridge_intr.h (revision 81e0d2b0af8485d94ed5da487d4253841a2e6e45)
1 /* 	$NetBSD: footbridge_intr.h,v 1.5 2003/06/16 20:00:57 thorpej Exp $	*/
2 
3 /*
4  * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
5  * All rights reserved.
6  *
7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  * 3. All advertising materials mentioning features or use of this software
18  *    must display the following acknowledgement:
19  *	This product includes software developed for the NetBSD Project by
20  *	Wasabi Systems, Inc.
21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22  *    or promote products derived from this software without specific prior
23  *    written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35  * POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 #ifndef _FOOTBRIDGE_INTR_H_
39 #define _FOOTBRIDGE_INTR_H_
40 
41 #include <arm/armreg.h>
42 
43 /* Define the various Interrupt Priority Levels */
44 
45 /* Hardware Interrupt Priority Levels are not mutually exclusive. */
46 
47 #define IPL_NONE	0	/* nothing */
48 #define IPL_SOFT	1	/* generic soft interrupts */
49 #define IPL_SOFTCLOCK	2	/* clock software interrupts */
50 #define IPL_SOFTNET	3	/* network software interrupts */
51 #define IPL_BIO		4	/* block I/O */
52 #define IPL_NET		5	/* network */
53 #define IPL_SOFTSERIAL	6	/* serial software interrupts */
54 #define IPL_TTY		7	/* terminal */
55 #define IPL_VM		8	/* memory allocation */
56 #define IPL_AUDIO	9	/* audio */
57 #define IPL_CLOCK	10	/* clock */
58 #define IPL_STATCLOCK	11	/* statclock */
59 #define IPL_HIGH	12	/* everything */
60 #define IPL_SERIAL	13	/* serial */
61 
62 #define NIPL		14
63 
64 #define	IST_UNUSABLE	-1	/* interrupt cannot be used */
65 #define	IST_NONE	0	/* none (dummy) */
66 #define	IST_PULSE	1	/* pulsed */
67 #define	IST_EDGE	2	/* edge-triggered */
68 #define	IST_LEVEL	3	/* level-triggered */
69 
70 #define	__NEWINTR	/* enables new hooks in cpu_fork()/cpu_switch() */
71 
72 #define	ARM_IRQ_HANDLER	_C_LABEL(footbridge_intr_dispatch)
73 
74 #ifndef _LOCORE
75 #include <arm/cpufunc.h>
76 
77 #include <arm/footbridge/dc21285mem.h>
78 #include <arm/footbridge/dc21285reg.h>
79 
80 #define INT_SWMASK							\
81 	((1U << IRQ_SOFTINT) | (1U << IRQ_RESERVED0) |			\
82 	 (1U << IRQ_RESERVED1) | (1U << IRQ_RESERVED2))
83 #define ICU_INT_HWMASK	(0xffffffff & ~(INT_SWMASK |  (1U << IRQ_RESERVED3)))
84 
85 /* only call this with interrupts off */
86 static __inline void __attribute__((__unused__))
87     footbridge_set_intrmask(void)
88 {
89     extern __volatile uint32_t intr_enabled;
90     /* fetch once so we write the same number to both registers */
91     uint32_t tmp = intr_enabled & ICU_INT_HWMASK;
92 
93     ((__volatile uint32_t*)(DC21285_ARMCSR_VBASE))[IRQ_ENABLE_SET>>2] = tmp;
94     ((__volatile uint32_t*)(DC21285_ARMCSR_VBASE))[IRQ_ENABLE_CLEAR>>2] = ~tmp;
95 }
96 
97 static __inline void __attribute__((__unused__))
98 footbridge_splx(int newspl)
99 {
100 	extern __volatile uint32_t intr_enabled;
101 	extern __volatile int current_spl_level;
102 	extern __volatile int footbridge_ipending;
103 	extern void footbridge_do_pending(void);
104 	int oldirqstate, hwpend;
105 
106 	current_spl_level = newspl;
107 
108 	hwpend = (footbridge_ipending & ICU_INT_HWMASK) & ~newspl;
109 	if (hwpend != 0) {
110 		oldirqstate = disable_interrupts(I32_bit);
111 		intr_enabled |= hwpend;
112 		footbridge_set_intrmask();
113 		restore_interrupts(oldirqstate);
114 	}
115 
116 	if ((footbridge_ipending & INT_SWMASK) & ~newspl)
117 		footbridge_do_pending();
118 }
119 
120 static __inline int __attribute__((__unused__))
121 footbridge_splraise(int ipl)
122 {
123 	extern __volatile int current_spl_level;
124 	extern int footbridge_imask[];
125 	int	old;
126 
127 	old = current_spl_level;
128 	current_spl_level |= footbridge_imask[ipl];
129 
130 	return (old);
131 }
132 
133 static __inline int __attribute__((__unused__))
134 footbridge_spllower(int ipl)
135 {
136 	extern __volatile int current_spl_level;
137 	extern int footbridge_imask[];
138 	int old = current_spl_level;
139 
140 	footbridge_splx(footbridge_imask[ipl]);
141 	return(old);
142 }
143 
144 /* should only be defined in footbridge_intr.c */
145 #if !defined(ARM_SPL_NOINLINE)
146 
147 #define splx(newspl)		footbridge_splx(newspl)
148 #define	_spllower(ipl)		footbridge_spllower(ipl)
149 #define	_splraise(ipl)		footbridge_splraise(ipl)
150 void	_setsoftintr(int);
151 
152 #else
153 
154 int	_splraise(int);
155 int	_spllower(int);
156 void	splx(int);
157 void	_setsoftintr(int);
158 
159 #endif /* ! ARM_SPL_NOINLINE */
160 
161 #include <sys/device.h>
162 #include <sys/queue.h>
163 #include <machine/irqhandler.h>
164 
165 #define	splsoft()	_splraise(IPL_SOFT)
166 #define	splsoftclock()	_splraise(IPL_SOFTCLOCK)
167 #define	splsoftnet()	_splraise(IPL_SOFTNET)
168 #define	splbio()	_splraise(IPL_BIO)
169 #define	splnet()	_splraise(IPL_NET)
170 #define splsoftserial()	_splraise(IPL_SOFTSERIAL)
171 #define	spltty()	_splraise(IPL_TTY)
172 #define spllpt()        spltty()
173 #define	splvm()		_splraise(IPL_VM)
174 #define	splaudio()	_splraise(IPL_AUDIO)
175 #define	splclock()	_splraise(IPL_CLOCK)
176 #define	splstatclock()	_splraise(IPL_STATCLOCK)
177 #define	splhigh()	_splraise(IPL_HIGH)
178 #define	splserial()	_splraise(IPL_SERIAL)
179 
180 #define	spl0()		(void)_spllower(IPL_NONE)
181 #define	spllowersoftclock() (void)_spllower(IPL_SOFTCLOCK)
182 
183 #define	splsched()	splhigh()
184 #define	spllock()	splhigh()
185 
186 /* Use generic software interrupt support. */
187 #include <arm/softintr.h>
188 
189 /* footbridge has 32 interrupt lines */
190 #define	NIRQ		32
191 
192 struct intrhand {
193 	TAILQ_ENTRY(intrhand) ih_list;	/* link on intrq list */
194 	int (*ih_func)(void *);		/* handler */
195 	void *ih_arg;			/* arg for handler */
196 	int ih_ipl;			/* IPL_* */
197 	int ih_irq;			/* IRQ number */
198 };
199 
200 #define	IRQNAMESIZE	sizeof("footbridge irq 31")
201 
202 struct intrq {
203 	TAILQ_HEAD(, intrhand) iq_list;	/* handler list */
204 	struct evcnt iq_ev;		/* event counter */
205 	int iq_mask;			/* IRQs to mask while handling */
206 	int iq_levels;			/* IPL_*'s this IRQ has */
207 	int iq_ist;			/* share type */
208 	char iq_name[IRQNAMESIZE];	/* interrupt name */
209 };
210 
211 #endif /* _LOCORE */
212 
213 #endif	/* _FOOTBRIDGE_INTR_H */
214