xref: /netbsd-src/sys/arch/arm/fdt/pcihost_fdtvar.h (revision 82d56013d7b633d116a93943de88e08335357a7c)
1 /* $NetBSD: pcihost_fdtvar.h,v 1.3 2019/12/28 17:19:43 jmcneill Exp $ */
2 
3 /*-
4  * Copyright (c) 2018 Jared D. McNeill <jmcneill@invisible.ca>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 /* Physical address format bit definitions */
30 #define	PHYS_HI_RELO			__BIT(31)
31 #define	PHYS_HI_PREFETCH		__BIT(30)
32 #define	PHYS_HI_ALIASED			__BIT(29)
33 #define	PHYS_HI_SPACE			__BITS(25,24)
34 #define	 PHYS_HI_SPACE_CFG		0
35 #define	 PHYS_HI_SPACE_IO		1
36 #define	 PHYS_HI_SPACE_MEM32		2
37 #define	 PHYS_HI_SPACE_MEM64		3
38 #define	PHYS_HI_BUS			__BITS(23,16)
39 #define	PHYS_HI_DEVICE			__BITS(15,11)
40 #define	PHYS_HI_FUNCTION		__BITS(10,8)
41 #define	PHYS_HI_REGISTER		__BITS(7,0)
42 
43 extern int pcihost_segment;
44 
45 enum pcihost_type {
46 	PCIHOST_CAM = 1,
47 	PCIHOST_ECAM,
48 };
49 
50 struct pcih_bus_space {
51 	struct bus_space	bst;
52 
53 	int		(*map)(void *, bus_addr_t, bus_size_t,
54 			      int, bus_space_handle_t *);
55 	int			flags;
56 
57 	struct space_range {
58 		bus_addr_t	bpci;
59 		bus_addr_t	bbus;
60 		bus_size_t	size;
61 	} 			ranges[4];
62 	size_t			nranges;
63 };
64 
65 struct pcihost_softc {
66 	device_t		sc_dev;
67 	bus_dma_tag_t		sc_dmat;
68 	bus_space_tag_t		sc_bst;
69 	bus_space_handle_t	sc_bsh;
70 	int			sc_phandle;
71 
72 	enum pcihost_type	sc_type;
73 
74 	u_int			sc_seg;
75 	u_int			sc_bus_min;
76 	u_int			sc_bus_max;
77 
78 	struct arm32_pci_chipset sc_pc;
79 
80 	struct pcih_bus_space	sc_io;
81 	struct pcih_bus_space	sc_mem;
82 
83 	int			sc_pci_flags;
84 
85 	const u_int		*sc_pci_ranges;
86 	u_int			sc_pci_ranges_cells;
87 };
88 
89 void	pcihost_init2(struct pcihost_softc *);
90 void	pcihost_init(pci_chipset_tag_t, void *);
91