1 /* $NetBSD: pcihost_fdt.c,v 1.8 2019/02/28 00:47:10 jakllsch Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: pcihost_fdt.c,v 1.8 2019/02/28 00:47:10 jakllsch Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/extent.h> 39 #include <sys/queue.h> 40 #include <sys/mutex.h> 41 #include <sys/kmem.h> 42 43 #include <machine/cpu.h> 44 45 #include <arm/cpufunc.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pciconf.h> 50 51 #include <dev/fdt/fdtvar.h> 52 53 #include <arm/pci/pci_msi_machdep.h> 54 #include <arm/fdt/pcihost_fdtvar.h> 55 56 #define IH_INDEX_MASK 0x0000ffff 57 #define IH_MPSAFE 0x80000000 58 59 #define PCIHOST_DEFAULT_BUS_MIN 0 60 #define PCIHOST_DEFAULT_BUS_MAX 255 61 62 #define PCIHOST_CACHELINE_SIZE arm_dcache_align 63 64 int pcihost_segment = 0; 65 66 static int pcihost_match(device_t, cfdata_t, void *); 67 static void pcihost_attach(device_t, device_t, void *); 68 69 static int pcihost_config(struct pcihost_softc *); 70 71 static void pcihost_attach_hook(device_t, device_t, 72 struct pcibus_attach_args *); 73 static int pcihost_bus_maxdevs(void *, int); 74 static pcitag_t pcihost_make_tag(void *, int, int, int); 75 static void pcihost_decompose_tag(void *, pcitag_t, int *, int *, int *); 76 static u_int pcihost_get_segment(void *); 77 static pcireg_t pcihost_conf_read(void *, pcitag_t, int); 78 static void pcihost_conf_write(void *, pcitag_t, int, pcireg_t); 79 static int pcihost_conf_hook(void *, int, int, int, pcireg_t); 80 static void pcihost_conf_interrupt(void *, int, int, int, int, int *); 81 82 static int pcihost_intr_map(const struct pci_attach_args *, 83 pci_intr_handle_t *); 84 static const char *pcihost_intr_string(void *, pci_intr_handle_t, 85 char *, size_t); 86 static const struct evcnt *pcihost_intr_evcnt(void *, pci_intr_handle_t); 87 static int pcihost_intr_setattr(void *, pci_intr_handle_t *, int, 88 uint64_t); 89 static void * pcihost_intr_establish(void *, pci_intr_handle_t, 90 int, int (*)(void *), void *, 91 const char *); 92 static void pcihost_intr_disestablish(void *, void *); 93 94 static int pcihost_bus_space_map(void *, bus_addr_t, bus_size_t, 95 int, bus_space_handle_t *); 96 97 CFATTACH_DECL_NEW(pcihost_fdt, sizeof(struct pcihost_softc), 98 pcihost_match, pcihost_attach, NULL, NULL); 99 100 static const struct of_compat_data compat_data[] = { 101 { "pci-host-cam-generic", PCIHOST_CAM }, 102 { "pci-host-ecam-generic", PCIHOST_ECAM }, 103 { NULL, 0 } 104 }; 105 106 static int 107 pcihost_match(device_t parent, cfdata_t cf, void *aux) 108 { 109 struct fdt_attach_args * const faa = aux; 110 111 return of_match_compat_data(faa->faa_phandle, compat_data); 112 } 113 114 static void 115 pcihost_attach(device_t parent, device_t self, void *aux) 116 { 117 struct pcihost_softc * const sc = device_private(self); 118 struct fdt_attach_args * const faa = aux; 119 bus_addr_t cs_addr; 120 bus_size_t cs_size; 121 int error; 122 123 if (fdtbus_get_reg(faa->faa_phandle, 0, &cs_addr, &cs_size) != 0) { 124 aprint_error(": couldn't get registers\n"); 125 return; 126 } 127 128 sc->sc_dev = self; 129 sc->sc_dmat = faa->faa_dmat; 130 sc->sc_bst = faa->faa_bst; 131 sc->sc_phandle = faa->faa_phandle; 132 error = bus_space_map(sc->sc_bst, cs_addr, cs_size, 0, &sc->sc_bsh); 133 if (error) { 134 aprint_error(": couldn't map registers: %d\n", error); 135 return; 136 } 137 sc->sc_type = of_search_compatible(sc->sc_phandle, compat_data)->data; 138 139 aprint_naive("\n"); 140 aprint_normal(": Generic PCI host controller\n"); 141 142 pcihost_init(&sc->sc_pc, sc); 143 pcihost_init2(sc); 144 } 145 146 void 147 pcihost_init2(struct pcihost_softc *sc) 148 { 149 struct pcibus_attach_args pba; 150 const u_int *data; 151 int len; 152 153 if ((data = fdtbus_get_prop(sc->sc_phandle, "bus-range", &len)) != NULL) { 154 if (len != 8) { 155 aprint_error_dev(sc->sc_dev, "malformed 'bus-range' property\n"); 156 return; 157 } 158 sc->sc_bus_min = be32toh(data[0]); 159 sc->sc_bus_max = be32toh(data[1]); 160 } else { 161 sc->sc_bus_min = PCIHOST_DEFAULT_BUS_MIN; 162 sc->sc_bus_max = PCIHOST_DEFAULT_BUS_MAX; 163 } 164 165 /* 166 * Assign a fixed PCI segment ("domain") number. If the property is not 167 * present, assign one. The binding spec says if this property is used to 168 * assign static segment numbers, all host bridges should have segments 169 * astatic assigned to prevent overlaps. 170 */ 171 if (of_getprop_uint32(sc->sc_phandle, "linux,pci-domain", &sc->sc_seg)) 172 sc->sc_seg = pcihost_segment++; 173 174 if (pcihost_config(sc) != 0) 175 return; 176 177 memset(&pba, 0, sizeof(pba)); 178 pba.pba_flags = PCI_FLAGS_MRL_OKAY | 179 PCI_FLAGS_MRM_OKAY | 180 PCI_FLAGS_MWI_OKAY | 181 PCI_FLAGS_IO_OKAY | 182 PCI_FLAGS_MEM_OKAY; 183 #ifdef __HAVE_PCI_MSI_MSIX 184 if (sc->sc_type == PCIHOST_ECAM) { 185 pba.pba_flags |= PCI_FLAGS_MSI_OKAY | 186 PCI_FLAGS_MSIX_OKAY; 187 } 188 #endif 189 pba.pba_iot = &sc->sc_io.bst; 190 pba.pba_memt = &sc->sc_mem.bst; 191 pba.pba_dmat = sc->sc_dmat; 192 #ifdef _PCI_HAVE_DMA64 193 pba.pba_dmat64 = sc->sc_dmat; 194 #endif 195 pba.pba_pc = &sc->sc_pc; 196 pba.pba_bus = sc->sc_bus_min; 197 198 config_found_ia(sc->sc_dev, "pcibus", &pba, pcibusprint); 199 } 200 201 void 202 pcihost_init(pci_chipset_tag_t pc, void *priv) 203 { 204 pc->pc_conf_v = priv; 205 pc->pc_attach_hook = pcihost_attach_hook; 206 pc->pc_bus_maxdevs = pcihost_bus_maxdevs; 207 pc->pc_make_tag = pcihost_make_tag; 208 pc->pc_decompose_tag = pcihost_decompose_tag; 209 pc->pc_get_segment = pcihost_get_segment; 210 pc->pc_conf_read = pcihost_conf_read; 211 pc->pc_conf_write = pcihost_conf_write; 212 pc->pc_conf_hook = pcihost_conf_hook; 213 pc->pc_conf_interrupt = pcihost_conf_interrupt; 214 215 pc->pc_intr_v = priv; 216 pc->pc_intr_map = pcihost_intr_map; 217 pc->pc_intr_string = pcihost_intr_string; 218 pc->pc_intr_evcnt = pcihost_intr_evcnt; 219 pc->pc_intr_setattr = pcihost_intr_setattr; 220 pc->pc_intr_establish = pcihost_intr_establish; 221 pc->pc_intr_disestablish = pcihost_intr_disestablish; 222 } 223 224 static int 225 pcihost_config(struct pcihost_softc *sc) 226 { 227 struct extent *ioext = NULL, *memext = NULL, *pmemext = NULL; 228 const u_int *ranges; 229 u_int probe_only; 230 int error, len; 231 232 struct pcih_bus_space * const pibs = &sc->sc_io; 233 pibs->bst = *sc->sc_bst; 234 pibs->bst.bs_cookie = pibs; 235 pibs->map = pibs->bst.bs_map; 236 pibs->bst.bs_map = pcihost_bus_space_map; 237 238 struct pcih_bus_space * const pmbs = &sc->sc_mem; 239 pmbs->bst = *sc->sc_bst; 240 pmbs->bst.bs_cookie = pmbs; 241 pmbs->map = pmbs->bst.bs_map; 242 pmbs->bst.bs_map = pcihost_bus_space_map; 243 244 /* 245 * If this flag is set, skip configuration of the PCI bus and use existing config. 246 */ 247 if (of_getprop_uint32(sc->sc_phandle, "linux,pci-probe-only", &probe_only)) 248 probe_only = 0; 249 if (probe_only) 250 return 0; 251 252 ranges = fdtbus_get_prop(sc->sc_phandle, "ranges", &len); 253 if (ranges == NULL) { 254 aprint_error_dev(sc->sc_dev, "missing 'ranges' property\n"); 255 return EINVAL; 256 } 257 258 /* 259 * Each entry in the ranges table contains: 260 * - bus address (3 cells) 261 * - cpu physical address (2 cells) 262 * - size (2 cells) 263 * Total size for each entry is 28 bytes (7 cells). 264 */ 265 while (len >= 28) { 266 const uint32_t phys_hi = be32dec(&ranges[0]); 267 const uint64_t bus_phys = be64dec(&ranges[1]); 268 const uint64_t cpu_phys = be64dec(&ranges[3]); 269 const uint64_t size = be64dec(&ranges[5]); 270 271 len -= 28; 272 ranges += 7; 273 274 const bool is64 = (__SHIFTOUT(phys_hi, PHYS_HI_SPACE) == 275 PHYS_HI_SPACE_MEM64) ? true : false; 276 switch (__SHIFTOUT(phys_hi, PHYS_HI_SPACE)) { 277 case PHYS_HI_SPACE_IO: 278 if (pibs->nranges + 1 >= __arraycount(pibs->ranges)) { 279 aprint_error_dev(sc->sc_dev, "too many IO ranges\n"); 280 continue; 281 } 282 pibs->ranges[pibs->nranges].bpci = bus_phys; 283 pibs->ranges[pibs->nranges].bbus = cpu_phys; 284 pibs->ranges[pibs->nranges].size = size; 285 ++pibs->nranges; 286 if (ioext != NULL) { 287 aprint_error_dev(sc->sc_dev, "ignoring duplicate IO space range\n"); 288 continue; 289 } 290 ioext = extent_create("pciio", bus_phys, bus_phys + size - 1, NULL, 0, EX_NOWAIT); 291 aprint_verbose_dev(sc->sc_dev, 292 "IO: 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n", 293 bus_phys, size, cpu_phys); 294 /* reserve a PC-like legacy IO ports range, perhaps for access to VGA registers */ 295 if (bus_phys == 0 && size >= 0x10000) 296 extent_alloc_region(ioext, 0, 0x1000, EX_WAITOK); 297 break; 298 case PHYS_HI_SPACE_MEM64: 299 /* FALLTHROUGH */ 300 case PHYS_HI_SPACE_MEM32: 301 if (pmbs->nranges + 1 >= __arraycount(pmbs->ranges)) { 302 aprint_error_dev(sc->sc_dev, "too many mem ranges\n"); 303 continue; 304 } 305 /* both pmem and mem spaces are in the same tag */ 306 pmbs->ranges[pmbs->nranges].bpci = bus_phys; 307 pmbs->ranges[pmbs->nranges].bbus = cpu_phys; 308 pmbs->ranges[pmbs->nranges].size = size; 309 ++pmbs->nranges; 310 if ((phys_hi & PHYS_HI_PREFETCH) != 0 || 311 __SHIFTOUT(phys_hi, PHYS_HI_SPACE) == PHYS_HI_SPACE_MEM64) { 312 if (pmemext != NULL) { 313 aprint_error_dev(sc->sc_dev, "ignoring duplicate mem (prefetchable) range\n"); 314 continue; 315 } 316 pmemext = extent_create("pcipmem", bus_phys, bus_phys + size - 1, NULL, 0, EX_NOWAIT); 317 aprint_verbose_dev(sc->sc_dev, 318 "MMIO (%d-bit prefetchable): 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n", 319 is64 ? 64 : 32, bus_phys, size, cpu_phys); 320 } else { 321 if (memext != NULL) { 322 aprint_error_dev(sc->sc_dev, "ignoring duplicate mem (non-prefetchable) range\n"); 323 continue; 324 } 325 memext = extent_create("pcimem", bus_phys, bus_phys + size - 1, NULL, 0, EX_NOWAIT); 326 aprint_verbose_dev(sc->sc_dev, 327 "MMIO (%d-bit non-prefetchable): 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n", 328 is64 ? 64 : 32, bus_phys, size, cpu_phys); 329 } 330 break; 331 default: 332 break; 333 } 334 } 335 336 error = pci_configure_bus(&sc->sc_pc, ioext, memext, pmemext, sc->sc_bus_min, PCIHOST_CACHELINE_SIZE); 337 338 if (ioext) 339 extent_destroy(ioext); 340 if (memext) 341 extent_destroy(memext); 342 if (pmemext) 343 extent_destroy(pmemext); 344 345 if (error) { 346 aprint_error_dev(sc->sc_dev, "configuration failed: %d\n", error); 347 return error; 348 } 349 350 return 0; 351 } 352 353 static void 354 pcihost_attach_hook(device_t parent, device_t self, 355 struct pcibus_attach_args *pba) 356 { 357 } 358 359 static int 360 pcihost_bus_maxdevs(void *v, int busno) 361 { 362 return 32; 363 } 364 365 static pcitag_t 366 pcihost_make_tag(void *v, int b, int d, int f) 367 { 368 return (b << 16) | (d << 11) | (f << 8); 369 } 370 371 static void 372 pcihost_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 373 { 374 if (bp) 375 *bp = (tag >> 16) & 0xff; 376 if (dp) 377 *dp = (tag >> 11) & 0x1f; 378 if (fp) 379 *fp = (tag >> 8) & 0x7; 380 } 381 382 static u_int 383 pcihost_get_segment(void *v) 384 { 385 struct pcihost_softc *sc = v; 386 387 return sc->sc_seg; 388 } 389 390 static pcireg_t 391 pcihost_conf_read(void *v, pcitag_t tag, int offset) 392 { 393 struct pcihost_softc *sc = v; 394 int b, d, f; 395 u_int reg; 396 397 pcihost_decompose_tag(v, tag, &b, &d, &f); 398 399 if (b < sc->sc_bus_min || b > sc->sc_bus_max) 400 return (pcireg_t) -1; 401 402 if (sc->sc_type == PCIHOST_CAM) { 403 if (offset & ~0xff) 404 return (pcireg_t) -1; 405 reg = (b << 16) | (d << 11) | (f << 8) | offset; 406 } else if (sc->sc_type == PCIHOST_ECAM) { 407 if (offset & ~0xfff) 408 return (pcireg_t) -1; 409 reg = (b << 20) | (d << 15) | (f << 12) | offset; 410 } else { 411 return (pcireg_t) -1; 412 } 413 414 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg); 415 } 416 417 static void 418 pcihost_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 419 { 420 struct pcihost_softc *sc = v; 421 int b, d, f; 422 u_int reg; 423 424 pcihost_decompose_tag(v, tag, &b, &d, &f); 425 426 if (b < sc->sc_bus_min || b > sc->sc_bus_max) 427 return; 428 429 if (sc->sc_type == PCIHOST_CAM) { 430 if (offset & ~0xff) 431 return; 432 reg = (b << 16) | (d << 11) | (f << 8) | offset; 433 } else if (sc->sc_type == PCIHOST_ECAM) { 434 if (offset & ~0xfff) 435 return; 436 reg = (b << 20) | (d << 15) | (f << 12) | offset; 437 } else { 438 return; 439 } 440 441 bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val); 442 } 443 444 static int 445 pcihost_conf_hook(void *v, int b, int d, int f, pcireg_t id) 446 { 447 return PCI_CONF_DEFAULT; 448 } 449 450 static void 451 pcihost_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *ilinep) 452 { 453 } 454 455 static int 456 pcihost_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih) 457 { 458 struct pcihost_softc *sc = pa->pa_pc->pc_intr_v; 459 u_int addr_cells, interrupt_cells; 460 const u_int *imap, *imask; 461 int imaplen, imasklen; 462 u_int match[4]; 463 int index; 464 465 if (pa->pa_intrpin == 0) 466 return EINVAL; 467 468 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen); 469 imask = fdtbus_get_prop(sc->sc_phandle, "interrupt-map-mask", &imasklen); 470 if (imap == NULL || imask == NULL || imasklen != 16) 471 return EINVAL; 472 473 /* Convert attach args to specifier */ 474 match[0] = htobe32( 475 __SHIFTIN(pa->pa_bus, PHYS_HI_BUS) | 476 __SHIFTIN(pa->pa_device, PHYS_HI_DEVICE) | 477 __SHIFTIN(pa->pa_function, PHYS_HI_FUNCTION) 478 ) & imask[0]; 479 match[1] = htobe32(0) & imask[1]; 480 match[2] = htobe32(0) & imask[2]; 481 match[3] = htobe32(pa->pa_intrpin) & imask[3]; 482 483 index = 0; 484 while (imaplen >= 20) { 485 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4])); 486 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells)) 487 addr_cells = 2; 488 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells)) 489 interrupt_cells = 0; 490 if (imaplen < (addr_cells + interrupt_cells) * 4) 491 return ENXIO; 492 493 if ((imap[0] & imask[0]) == match[0] && 494 (imap[1] & imask[1]) == match[1] && 495 (imap[2] & imask[2]) == match[2] && 496 (imap[3] & imask[3]) == match[3]) { 497 *ih = index; 498 return 0; 499 } 500 501 imap += (5 + addr_cells + interrupt_cells); 502 imaplen -= (5 + addr_cells + interrupt_cells) * 4; 503 index++; 504 } 505 506 return EINVAL; 507 } 508 509 static const u_int * 510 pcihost_find_intr(struct pcihost_softc *sc, pci_intr_handle_t ih, int *pihandle) 511 { 512 u_int addr_cells, interrupt_cells; 513 int imaplen, index; 514 const u_int *imap; 515 516 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen); 517 KASSERT(imap != NULL); 518 519 index = 0; 520 while (imaplen >= 20) { 521 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4])); 522 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells)) 523 addr_cells = 2; 524 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells)) 525 interrupt_cells = 0; 526 if (imaplen < (addr_cells + interrupt_cells) * 4) 527 return NULL; 528 529 if (index == ih) { 530 *pihandle = map_ihandle; 531 return imap + 5 + addr_cells; 532 } 533 534 imap += (5 + addr_cells + interrupt_cells); 535 imaplen -= (5 + addr_cells + interrupt_cells) * 4; 536 index++; 537 } 538 539 return NULL; 540 } 541 542 static const char * 543 pcihost_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 544 { 545 const int irq = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ); 546 const int vec = __SHIFTOUT(ih, ARM_PCI_INTR_MSI_VEC); 547 struct pcihost_softc *sc = v; 548 const u_int *specifier; 549 int ihandle; 550 551 if (ih & ARM_PCI_INTR_MSIX) { 552 snprintf(buf, len, "irq %d (MSI-X vec %d)", irq, vec); 553 } else if (ih & ARM_PCI_INTR_MSI) { 554 snprintf(buf, len, "irq %d (MSI vec %d)", irq, vec); 555 } else { 556 specifier = pcihost_find_intr(sc, ih & IH_INDEX_MASK, &ihandle); 557 if (specifier == NULL) 558 return NULL; 559 560 if (!fdtbus_intr_str_raw(ihandle, specifier, buf, len)) 561 return NULL; 562 } 563 564 return buf; 565 } 566 567 const struct evcnt * 568 pcihost_intr_evcnt(void *v, pci_intr_handle_t ih) 569 { 570 return NULL; 571 } 572 573 static int 574 pcihost_intr_setattr(void *v, pci_intr_handle_t *ih, int attr, uint64_t data) 575 { 576 switch (attr) { 577 case PCI_INTR_MPSAFE: 578 if (data) 579 *ih |= IH_MPSAFE; 580 else 581 *ih &= ~IH_MPSAFE; 582 return 0; 583 default: 584 return ENODEV; 585 } 586 } 587 588 static void * 589 pcihost_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 590 int (*callback)(void *), void *arg, const char *xname) 591 { 592 struct pcihost_softc *sc = v; 593 const int flags = (ih & IH_MPSAFE) ? FDT_INTR_MPSAFE : 0; 594 const u_int *specifier; 595 int ihandle; 596 597 if ((ih & (ARM_PCI_INTR_MSI | ARM_PCI_INTR_MSIX)) != 0) 598 return arm_pci_msi_intr_establish(&sc->sc_pc, ih, ipl, callback, arg, xname); 599 600 specifier = pcihost_find_intr(sc, ih & IH_INDEX_MASK, &ihandle); 601 if (specifier == NULL) 602 return NULL; 603 604 return fdtbus_intr_establish_raw(ihandle, specifier, ipl, flags, callback, arg); 605 } 606 607 static void 608 pcihost_intr_disestablish(void *v, void *vih) 609 { 610 struct pcihost_softc *sc = v; 611 612 fdtbus_intr_disestablish(sc->sc_phandle, vih); 613 } 614 615 static int 616 pcihost_bus_space_map(void *t, bus_addr_t bpa, bus_size_t size, int flag, 617 bus_space_handle_t *bshp) 618 { 619 struct pcih_bus_space * const pbs = t; 620 621 for (size_t i = 0; i < pbs->nranges; i++) { 622 const bus_addr_t rmin = pbs->ranges[i].bpci; 623 const bus_addr_t rmax = pbs->ranges[i].bpci - 1 + pbs->ranges[i].size; 624 if ((bpa >= rmin) && ((bpa - 1 + size) <= rmax)) { 625 return pbs->map(t, bpa - pbs->ranges[i].bpci + pbs->ranges[i].bbus, size, flag, bshp); 626 } 627 } 628 629 return ERANGE; 630 } 631