1 /* $NetBSD: pcihost_fdt.c,v 1.11 2019/06/23 22:06:03 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: pcihost_fdt.c,v 1.11 2019/06/23 22:06:03 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/extent.h> 39 #include <sys/queue.h> 40 #include <sys/mutex.h> 41 #include <sys/kmem.h> 42 43 #include <machine/cpu.h> 44 45 #include <arm/cpufunc.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pciconf.h> 50 51 #include <dev/fdt/fdtvar.h> 52 53 #include <arm/pci/pci_msi_machdep.h> 54 #include <arm/fdt/pcihost_fdtvar.h> 55 56 #define PCIHOST_DEFAULT_BUS_MIN 0 57 #define PCIHOST_DEFAULT_BUS_MAX 255 58 59 #define PCIHOST_CACHELINE_SIZE arm_dcache_align 60 61 int pcihost_segment = 0; 62 63 static int pcihost_match(device_t, cfdata_t, void *); 64 static void pcihost_attach(device_t, device_t, void *); 65 66 static int pcihost_config(struct pcihost_softc *); 67 68 static void pcihost_attach_hook(device_t, device_t, 69 struct pcibus_attach_args *); 70 static int pcihost_bus_maxdevs(void *, int); 71 static pcitag_t pcihost_make_tag(void *, int, int, int); 72 static void pcihost_decompose_tag(void *, pcitag_t, int *, int *, int *); 73 static u_int pcihost_get_segment(void *); 74 static pcireg_t pcihost_conf_read(void *, pcitag_t, int); 75 static void pcihost_conf_write(void *, pcitag_t, int, pcireg_t); 76 static int pcihost_conf_hook(void *, int, int, int, pcireg_t); 77 static void pcihost_conf_interrupt(void *, int, int, int, int, int *); 78 79 static int pcihost_intr_map(const struct pci_attach_args *, 80 pci_intr_handle_t *); 81 static const char *pcihost_intr_string(void *, pci_intr_handle_t, 82 char *, size_t); 83 static const struct evcnt *pcihost_intr_evcnt(void *, pci_intr_handle_t); 84 static int pcihost_intr_setattr(void *, pci_intr_handle_t *, int, 85 uint64_t); 86 static void * pcihost_intr_establish(void *, pci_intr_handle_t, 87 int, int (*)(void *), void *, 88 const char *); 89 static void pcihost_intr_disestablish(void *, void *); 90 91 static int pcihost_bus_space_map(void *, bus_addr_t, bus_size_t, 92 int, bus_space_handle_t *); 93 94 CFATTACH_DECL_NEW(pcihost_fdt, sizeof(struct pcihost_softc), 95 pcihost_match, pcihost_attach, NULL, NULL); 96 97 static const struct of_compat_data compat_data[] = { 98 { "pci-host-cam-generic", PCIHOST_CAM }, 99 { "pci-host-ecam-generic", PCIHOST_ECAM }, 100 { NULL, 0 } 101 }; 102 103 static int 104 pcihost_match(device_t parent, cfdata_t cf, void *aux) 105 { 106 struct fdt_attach_args * const faa = aux; 107 108 return of_match_compat_data(faa->faa_phandle, compat_data); 109 } 110 111 static void 112 pcihost_attach(device_t parent, device_t self, void *aux) 113 { 114 struct pcihost_softc * const sc = device_private(self); 115 struct fdt_attach_args * const faa = aux; 116 bus_addr_t cs_addr; 117 bus_size_t cs_size; 118 int error; 119 120 if (fdtbus_get_reg(faa->faa_phandle, 0, &cs_addr, &cs_size) != 0) { 121 aprint_error(": couldn't get registers\n"); 122 return; 123 } 124 125 sc->sc_dev = self; 126 sc->sc_dmat = faa->faa_dmat; 127 sc->sc_bst = faa->faa_bst; 128 sc->sc_phandle = faa->faa_phandle; 129 error = bus_space_map(sc->sc_bst, cs_addr, cs_size, 0, &sc->sc_bsh); 130 if (error) { 131 aprint_error(": couldn't map registers: %d\n", error); 132 return; 133 } 134 sc->sc_type = of_search_compatible(sc->sc_phandle, compat_data)->data; 135 136 #ifdef __HAVE_PCI_MSI_MSIX 137 if (sc->sc_type == PCIHOST_ECAM) { 138 sc->sc_pci_flags |= PCI_FLAGS_MSI_OKAY; 139 sc->sc_pci_flags |= PCI_FLAGS_MSIX_OKAY; 140 } 141 #endif 142 143 aprint_naive("\n"); 144 aprint_normal(": Generic PCI host controller\n"); 145 146 pcihost_init(&sc->sc_pc, sc); 147 pcihost_init2(sc); 148 } 149 150 void 151 pcihost_init2(struct pcihost_softc *sc) 152 { 153 struct pcibus_attach_args pba; 154 const u_int *data; 155 int len; 156 157 if ((data = fdtbus_get_prop(sc->sc_phandle, "bus-range", &len)) != NULL) { 158 if (len != 8) { 159 aprint_error_dev(sc->sc_dev, "malformed 'bus-range' property\n"); 160 return; 161 } 162 sc->sc_bus_min = be32toh(data[0]); 163 sc->sc_bus_max = be32toh(data[1]); 164 } else { 165 sc->sc_bus_min = PCIHOST_DEFAULT_BUS_MIN; 166 sc->sc_bus_max = PCIHOST_DEFAULT_BUS_MAX; 167 } 168 169 /* 170 * Assign a fixed PCI segment ("domain") number. If the property is not 171 * present, assign one. The binding spec says if this property is used to 172 * assign static segment numbers, all host bridges should have segments 173 * astatic assigned to prevent overlaps. 174 */ 175 if (of_getprop_uint32(sc->sc_phandle, "linux,pci-domain", &sc->sc_seg)) 176 sc->sc_seg = pcihost_segment++; 177 178 if (pcihost_config(sc) != 0) 179 return; 180 181 memset(&pba, 0, sizeof(pba)); 182 pba.pba_flags = PCI_FLAGS_MRL_OKAY | 183 PCI_FLAGS_MRM_OKAY | 184 PCI_FLAGS_MWI_OKAY | 185 sc->sc_pci_flags; 186 pba.pba_iot = &sc->sc_io.bst; 187 pba.pba_memt = &sc->sc_mem.bst; 188 pba.pba_dmat = sc->sc_dmat; 189 #ifdef _PCI_HAVE_DMA64 190 pba.pba_dmat64 = sc->sc_dmat; 191 #endif 192 pba.pba_pc = &sc->sc_pc; 193 pba.pba_bus = sc->sc_bus_min; 194 195 config_found_ia(sc->sc_dev, "pcibus", &pba, pcibusprint); 196 } 197 198 void 199 pcihost_init(pci_chipset_tag_t pc, void *priv) 200 { 201 pc->pc_conf_v = priv; 202 pc->pc_attach_hook = pcihost_attach_hook; 203 pc->pc_bus_maxdevs = pcihost_bus_maxdevs; 204 pc->pc_make_tag = pcihost_make_tag; 205 pc->pc_decompose_tag = pcihost_decompose_tag; 206 pc->pc_get_segment = pcihost_get_segment; 207 pc->pc_conf_read = pcihost_conf_read; 208 pc->pc_conf_write = pcihost_conf_write; 209 pc->pc_conf_hook = pcihost_conf_hook; 210 pc->pc_conf_interrupt = pcihost_conf_interrupt; 211 212 pc->pc_intr_v = priv; 213 pc->pc_intr_map = pcihost_intr_map; 214 pc->pc_intr_string = pcihost_intr_string; 215 pc->pc_intr_evcnt = pcihost_intr_evcnt; 216 pc->pc_intr_setattr = pcihost_intr_setattr; 217 pc->pc_intr_establish = pcihost_intr_establish; 218 pc->pc_intr_disestablish = pcihost_intr_disestablish; 219 } 220 221 static int 222 pcihost_config(struct pcihost_softc *sc) 223 { 224 struct extent *ioext = NULL, *memext = NULL, *pmemext = NULL; 225 const u_int *ranges; 226 u_int probe_only; 227 int error, len; 228 bool swap; 229 230 struct pcih_bus_space * const pibs = &sc->sc_io; 231 pibs->bst = *sc->sc_bst; 232 pibs->bst.bs_cookie = pibs; 233 pibs->map = pibs->bst.bs_map; 234 pibs->bst.bs_map = pcihost_bus_space_map; 235 236 struct pcih_bus_space * const pmbs = &sc->sc_mem; 237 pmbs->bst = *sc->sc_bst; 238 pmbs->bst.bs_cookie = pmbs; 239 pmbs->map = pmbs->bst.bs_map; 240 pmbs->bst.bs_map = pcihost_bus_space_map; 241 242 /* 243 * If this flag is set, skip configuration of the PCI bus and use existing config. 244 */ 245 if (of_getprop_uint32(sc->sc_phandle, "linux,pci-probe-only", &probe_only)) 246 probe_only = 0; 247 if (probe_only) 248 return 0; 249 250 if (sc->sc_pci_ranges != NULL) { 251 ranges = sc->sc_pci_ranges; 252 len = sc->sc_pci_ranges_cells * 4; 253 swap = false; 254 } else { 255 ranges = fdtbus_get_prop(sc->sc_phandle, "ranges", &len); 256 if (ranges == NULL) { 257 aprint_error_dev(sc->sc_dev, "missing 'ranges' property\n"); 258 return EINVAL; 259 } 260 swap = true; 261 } 262 263 /* 264 * Each entry in the ranges table contains: 265 * - bus address (3 cells) 266 * - cpu physical address (2 cells) 267 * - size (2 cells) 268 * Total size for each entry is 28 bytes (7 cells). 269 */ 270 while (len >= 28) { 271 #define DECODE32(x,o) (swap ? be32dec(&(x)[o]) : (x)[o]) 272 #define DECODE64(x,o) (swap ? be64dec(&(x)[o]) : (((uint64_t)((x)[(o)+0]) << 32) + (x)[(o)+1])) 273 const uint32_t phys_hi = DECODE32(ranges, 0); 274 const uint64_t bus_phys = DECODE64(ranges, 1); 275 const uint64_t cpu_phys = DECODE64(ranges, 3); 276 const uint64_t size = DECODE64(ranges, 5); 277 #undef DECODE32 278 #undef DECODE64 279 280 len -= 28; 281 ranges += 7; 282 283 const bool is64 = (__SHIFTOUT(phys_hi, PHYS_HI_SPACE) == 284 PHYS_HI_SPACE_MEM64) ? true : false; 285 switch (__SHIFTOUT(phys_hi, PHYS_HI_SPACE)) { 286 case PHYS_HI_SPACE_IO: 287 if (pibs->nranges + 1 >= __arraycount(pibs->ranges)) { 288 aprint_error_dev(sc->sc_dev, "too many IO ranges\n"); 289 continue; 290 } 291 pibs->ranges[pibs->nranges].bpci = bus_phys; 292 pibs->ranges[pibs->nranges].bbus = cpu_phys; 293 pibs->ranges[pibs->nranges].size = size; 294 ++pibs->nranges; 295 if (ioext != NULL) { 296 aprint_error_dev(sc->sc_dev, "ignoring duplicate IO space range\n"); 297 continue; 298 } 299 ioext = extent_create("pciio", bus_phys, bus_phys + size - 1, NULL, 0, EX_NOWAIT); 300 aprint_verbose_dev(sc->sc_dev, 301 "IO: 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n", 302 bus_phys, size, cpu_phys); 303 /* reserve a PC-like legacy IO ports range, perhaps for access to VGA registers */ 304 if (bus_phys == 0 && size >= 0x10000) 305 extent_alloc_region(ioext, 0, 0x1000, EX_WAITOK); 306 sc->sc_pci_flags |= PCI_FLAGS_IO_OKAY; 307 break; 308 case PHYS_HI_SPACE_MEM64: 309 /* FALLTHROUGH */ 310 case PHYS_HI_SPACE_MEM32: 311 if (pmbs->nranges + 1 >= __arraycount(pmbs->ranges)) { 312 aprint_error_dev(sc->sc_dev, "too many mem ranges\n"); 313 continue; 314 } 315 /* both pmem and mem spaces are in the same tag */ 316 pmbs->ranges[pmbs->nranges].bpci = bus_phys; 317 pmbs->ranges[pmbs->nranges].bbus = cpu_phys; 318 pmbs->ranges[pmbs->nranges].size = size; 319 ++pmbs->nranges; 320 if ((phys_hi & PHYS_HI_PREFETCH) != 0 || 321 __SHIFTOUT(phys_hi, PHYS_HI_SPACE) == PHYS_HI_SPACE_MEM64) { 322 if (pmemext != NULL) { 323 aprint_error_dev(sc->sc_dev, "ignoring duplicate mem (prefetchable) range\n"); 324 continue; 325 } 326 pmemext = extent_create("pcipmem", bus_phys, bus_phys + size - 1, NULL, 0, EX_NOWAIT); 327 aprint_verbose_dev(sc->sc_dev, 328 "MMIO (%d-bit prefetchable): 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n", 329 is64 ? 64 : 32, bus_phys, size, cpu_phys); 330 } else { 331 if (memext != NULL) { 332 aprint_error_dev(sc->sc_dev, "ignoring duplicate mem (non-prefetchable) range\n"); 333 continue; 334 } 335 memext = extent_create("pcimem", bus_phys, bus_phys + size - 1, NULL, 0, EX_NOWAIT); 336 aprint_verbose_dev(sc->sc_dev, 337 "MMIO (%d-bit non-prefetchable): 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n", 338 is64 ? 64 : 32, bus_phys, size, cpu_phys); 339 } 340 sc->sc_pci_flags |= PCI_FLAGS_MEM_OKAY; 341 break; 342 default: 343 break; 344 } 345 } 346 347 if (memext == NULL && pmemext != NULL) { 348 memext = pmemext; 349 pmemext = NULL; 350 } 351 352 error = pci_configure_bus(&sc->sc_pc, ioext, memext, pmemext, sc->sc_bus_min, PCIHOST_CACHELINE_SIZE); 353 354 if (ioext) 355 extent_destroy(ioext); 356 if (memext) 357 extent_destroy(memext); 358 if (pmemext) 359 extent_destroy(pmemext); 360 361 if (error) { 362 aprint_error_dev(sc->sc_dev, "configuration failed: %d\n", error); 363 return error; 364 } 365 366 return 0; 367 } 368 369 static void 370 pcihost_attach_hook(device_t parent, device_t self, 371 struct pcibus_attach_args *pba) 372 { 373 } 374 375 static int 376 pcihost_bus_maxdevs(void *v, int busno) 377 { 378 return 32; 379 } 380 381 static pcitag_t 382 pcihost_make_tag(void *v, int b, int d, int f) 383 { 384 return (b << 16) | (d << 11) | (f << 8); 385 } 386 387 static void 388 pcihost_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 389 { 390 if (bp) 391 *bp = (tag >> 16) & 0xff; 392 if (dp) 393 *dp = (tag >> 11) & 0x1f; 394 if (fp) 395 *fp = (tag >> 8) & 0x7; 396 } 397 398 static u_int 399 pcihost_get_segment(void *v) 400 { 401 struct pcihost_softc *sc = v; 402 403 return sc->sc_seg; 404 } 405 406 static pcireg_t 407 pcihost_conf_read(void *v, pcitag_t tag, int offset) 408 { 409 struct pcihost_softc *sc = v; 410 int b, d, f; 411 u_int reg; 412 413 pcihost_decompose_tag(v, tag, &b, &d, &f); 414 415 if (b < sc->sc_bus_min || b > sc->sc_bus_max) 416 return (pcireg_t) -1; 417 418 if (sc->sc_type == PCIHOST_CAM) { 419 if (offset & ~0xff) 420 return (pcireg_t) -1; 421 reg = (b << 16) | (d << 11) | (f << 8) | offset; 422 } else if (sc->sc_type == PCIHOST_ECAM) { 423 if (offset & ~0xfff) 424 return (pcireg_t) -1; 425 reg = (b << 20) | (d << 15) | (f << 12) | offset; 426 } else { 427 return (pcireg_t) -1; 428 } 429 430 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg); 431 } 432 433 static void 434 pcihost_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 435 { 436 struct pcihost_softc *sc = v; 437 int b, d, f; 438 u_int reg; 439 440 pcihost_decompose_tag(v, tag, &b, &d, &f); 441 442 if (b < sc->sc_bus_min || b > sc->sc_bus_max) 443 return; 444 445 if (sc->sc_type == PCIHOST_CAM) { 446 if (offset & ~0xff) 447 return; 448 reg = (b << 16) | (d << 11) | (f << 8) | offset; 449 } else if (sc->sc_type == PCIHOST_ECAM) { 450 if (offset & ~0xfff) 451 return; 452 reg = (b << 20) | (d << 15) | (f << 12) | offset; 453 } else { 454 return; 455 } 456 457 bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val); 458 } 459 460 static int 461 pcihost_conf_hook(void *v, int b, int d, int f, pcireg_t id) 462 { 463 return PCI_CONF_DEFAULT; 464 } 465 466 static void 467 pcihost_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *ilinep) 468 { 469 } 470 471 static int 472 pcihost_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih) 473 { 474 struct pcihost_softc *sc = pa->pa_pc->pc_intr_v; 475 u_int addr_cells, interrupt_cells; 476 const u_int *imap, *imask; 477 int imaplen, imasklen; 478 u_int match[4]; 479 int index; 480 481 if (pa->pa_intrpin == 0) 482 return EINVAL; 483 484 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen); 485 imask = fdtbus_get_prop(sc->sc_phandle, "interrupt-map-mask", &imasklen); 486 if (imap == NULL || imask == NULL || imasklen != 16) 487 return EINVAL; 488 489 /* Convert attach args to specifier */ 490 match[0] = htobe32( 491 __SHIFTIN(pa->pa_bus, PHYS_HI_BUS) | 492 __SHIFTIN(pa->pa_device, PHYS_HI_DEVICE) | 493 __SHIFTIN(pa->pa_function, PHYS_HI_FUNCTION) 494 ) & imask[0]; 495 match[1] = htobe32(0) & imask[1]; 496 match[2] = htobe32(0) & imask[2]; 497 match[3] = htobe32(pa->pa_intrpin) & imask[3]; 498 499 index = 0; 500 while (imaplen >= 20) { 501 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4])); 502 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells)) 503 addr_cells = 2; 504 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells)) 505 interrupt_cells = 0; 506 if (imaplen < (addr_cells + interrupt_cells) * 4) 507 return ENXIO; 508 509 if ((imap[0] & imask[0]) == match[0] && 510 (imap[1] & imask[1]) == match[1] && 511 (imap[2] & imask[2]) == match[2] && 512 (imap[3] & imask[3]) == match[3]) { 513 *ih = index; 514 return 0; 515 } 516 517 imap += (5 + addr_cells + interrupt_cells); 518 imaplen -= (5 + addr_cells + interrupt_cells) * 4; 519 index++; 520 } 521 522 return EINVAL; 523 } 524 525 static const u_int * 526 pcihost_find_intr(struct pcihost_softc *sc, pci_intr_handle_t ih, int *pihandle) 527 { 528 u_int addr_cells, interrupt_cells; 529 int imaplen, index; 530 const u_int *imap; 531 532 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen); 533 KASSERT(imap != NULL); 534 535 index = 0; 536 while (imaplen >= 20) { 537 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4])); 538 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells)) 539 addr_cells = 2; 540 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells)) 541 interrupt_cells = 0; 542 if (imaplen < (addr_cells + interrupt_cells) * 4) 543 return NULL; 544 545 if (index == ih) { 546 *pihandle = map_ihandle; 547 return imap + 5 + addr_cells; 548 } 549 550 imap += (5 + addr_cells + interrupt_cells); 551 imaplen -= (5 + addr_cells + interrupt_cells) * 4; 552 index++; 553 } 554 555 return NULL; 556 } 557 558 static const char * 559 pcihost_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 560 { 561 const int irq = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ); 562 const int vec = __SHIFTOUT(ih, ARM_PCI_INTR_MSI_VEC); 563 struct pcihost_softc *sc = v; 564 const u_int *specifier; 565 int ihandle; 566 567 if (ih & ARM_PCI_INTR_MSIX) { 568 snprintf(buf, len, "irq %d (MSI-X vec %d)", irq, vec); 569 } else if (ih & ARM_PCI_INTR_MSI) { 570 snprintf(buf, len, "irq %d (MSI vec %d)", irq, vec); 571 } else { 572 specifier = pcihost_find_intr(sc, ih & ARM_PCI_INTR_IRQ, &ihandle); 573 if (specifier == NULL) 574 return NULL; 575 576 if (!fdtbus_intr_str_raw(ihandle, specifier, buf, len)) 577 return NULL; 578 } 579 580 return buf; 581 } 582 583 const struct evcnt * 584 pcihost_intr_evcnt(void *v, pci_intr_handle_t ih) 585 { 586 return NULL; 587 } 588 589 static int 590 pcihost_intr_setattr(void *v, pci_intr_handle_t *ih, int attr, uint64_t data) 591 { 592 switch (attr) { 593 case PCI_INTR_MPSAFE: 594 if (data) 595 *ih |= ARM_PCI_INTR_MPSAFE; 596 else 597 *ih &= ~ARM_PCI_INTR_MPSAFE; 598 return 0; 599 default: 600 return ENODEV; 601 } 602 } 603 604 static void * 605 pcihost_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 606 int (*callback)(void *), void *arg, const char *xname) 607 { 608 struct pcihost_softc *sc = v; 609 const int flags = (ih & ARM_PCI_INTR_MPSAFE) ? FDT_INTR_MPSAFE : 0; 610 const u_int *specifier; 611 int ihandle; 612 613 if ((ih & (ARM_PCI_INTR_MSI | ARM_PCI_INTR_MSIX)) != 0) 614 return arm_pci_msi_intr_establish(&sc->sc_pc, ih, ipl, callback, arg, xname); 615 616 specifier = pcihost_find_intr(sc, ih & ARM_PCI_INTR_IRQ, &ihandle); 617 if (specifier == NULL) 618 return NULL; 619 620 return fdtbus_intr_establish_raw(ihandle, specifier, ipl, flags, callback, arg); 621 } 622 623 static void 624 pcihost_intr_disestablish(void *v, void *vih) 625 { 626 struct pcihost_softc *sc = v; 627 628 fdtbus_intr_disestablish(sc->sc_phandle, vih); 629 } 630 631 static int 632 pcihost_bus_space_map(void *t, bus_addr_t bpa, bus_size_t size, int flag, 633 bus_space_handle_t *bshp) 634 { 635 struct pcih_bus_space * const pbs = t; 636 637 for (size_t i = 0; i < pbs->nranges; i++) { 638 const bus_addr_t rmin = pbs->ranges[i].bpci; 639 const bus_addr_t rmax = pbs->ranges[i].bpci - 1 + pbs->ranges[i].size; 640 if ((bpa >= rmin) && ((bpa - 1 + size) <= rmax)) { 641 return pbs->map(t, bpa - pbs->ranges[i].bpci + pbs->ranges[i].bbus, size, flag, bshp); 642 } 643 } 644 645 return ERANGE; 646 } 647