1 /* $NetBSD: cpu_fdt.c,v 1.42 2022/03/03 06:26:05 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_multiprocessor.h" 30 #include "psci_fdt.h" 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: cpu_fdt.c,v 1.42 2022/03/03 06:26:05 riastradh Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/atomic.h> 37 #include <sys/bus.h> 38 #include <sys/device.h> 39 #include <sys/lwp.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 43 #include <dev/fdt/fdtvar.h> 44 45 #include <arm/armreg.h> 46 #include <arm/cpu.h> 47 #include <arm/cpufunc.h> 48 #include <arm/cpuvar.h> 49 #include <arm/locore.h> 50 51 #include <arm/arm/psci.h> 52 #include <arm/fdt/arm_fdtvar.h> 53 #include <arm/fdt/psci_fdtvar.h> 54 55 #include <uvm/uvm_extern.h> 56 57 static int cpu_fdt_match(device_t, cfdata_t, void *); 58 static void cpu_fdt_attach(device_t, device_t, void *); 59 60 CFATTACH_DECL_NEW(cpu_fdt, 0, 61 cpu_fdt_match, cpu_fdt_attach, NULL, NULL); 62 63 static int 64 cpu_fdt_match(device_t parent, cfdata_t cf, void *aux) 65 { 66 struct fdt_attach_args * const faa = aux; 67 const int phandle = faa->faa_phandle; 68 const char *device_type; 69 70 device_type = fdtbus_get_string(phandle, "device_type"); 71 72 return device_type != NULL && strcmp(device_type, "cpu") == 0; 73 } 74 75 static void 76 cpu_fdt_attach(device_t parent, device_t self, void *aux) 77 { 78 struct fdt_attach_args * const faa = aux; 79 const int phandle = faa->faa_phandle; 80 bus_addr_t cpuid; 81 const uint32_t *cap_ptr; 82 int len; 83 84 cap_ptr = fdtbus_get_prop(phandle, "capacity-dmips-mhz", &len); 85 if (cap_ptr && len == 4) { 86 prop_dictionary_t dict = device_properties(self); 87 uint32_t capacity_dmips_mhz = be32toh(*cap_ptr); 88 89 prop_dictionary_set_uint32(dict, "capacity_dmips_mhz", 90 capacity_dmips_mhz); 91 } 92 93 if (fdtbus_get_reg(phandle, 0, &cpuid, NULL) != 0) 94 cpuid = 0; 95 96 /* Attach the CPU */ 97 cpu_attach(self, cpuid); 98 99 /* Attach CPU frequency scaling provider */ 100 config_found(self, faa, NULL, CFARGS_NONE); 101 } 102 103 #if defined(MULTIPROCESSOR) && (NPSCI_FDT > 0 || defined(__aarch64__)) 104 static register_t 105 cpu_fdt_mpstart_pa(void) 106 { 107 bool ok __diagused; 108 paddr_t pa; 109 110 ok = pmap_extract(pmap_kernel(), (vaddr_t)cpu_mpstart, &pa); 111 KASSERT(ok); 112 113 return pa; 114 } 115 #endif 116 117 #ifdef MULTIPROCESSOR 118 static bool 119 arm_fdt_cpu_okay(const int child) 120 { 121 const char *s; 122 123 s = fdtbus_get_string(child, "device_type"); 124 if (!s || strcmp(s, "cpu") != 0) 125 return false; 126 127 s = fdtbus_get_string(child, "status"); 128 if (s) { 129 if (strcmp(s, "okay") == 0) 130 return false; 131 if (strcmp(s, "disabled") == 0) 132 return of_hasprop(child, "enable-method"); 133 return false; 134 } else { 135 return true; 136 } 137 } 138 #endif /* MULTIPROCESSOR */ 139 140 void 141 arm_fdt_cpu_bootstrap(void) 142 { 143 #ifdef MULTIPROCESSOR 144 uint64_t mpidr, bp_mpidr; 145 u_int cpuindex; 146 int child; 147 148 const int cpus = OF_finddevice("/cpus"); 149 if (cpus == -1) { 150 aprint_error("%s: no /cpus node found\n", __func__); 151 arm_cpu_max = 1; 152 return; 153 } 154 155 /* Count CPUs */ 156 arm_cpu_max = 0; 157 158 /* MPIDR affinity levels of boot processor. */ 159 bp_mpidr = cpu_mpidr_aff_read(); 160 161 /* Add APs to cpu_mpidr array */ 162 cpuindex = 1; 163 for (child = OF_child(cpus); child; child = OF_peer(child)) { 164 if (!arm_fdt_cpu_okay(child)) 165 continue; 166 167 arm_cpu_max++; 168 if (fdtbus_get_reg64(child, 0, &mpidr, NULL) != 0) 169 continue; 170 if (mpidr == bp_mpidr) 171 continue; /* BP already started */ 172 173 KASSERT(cpuindex < MAXCPUS); 174 cpu_mpidr[cpuindex] = mpidr; 175 cpu_dcache_wb_range((vaddr_t)&cpu_mpidr[cpuindex], 176 sizeof(cpu_mpidr[cpuindex])); 177 178 cpuindex++; 179 } 180 #endif 181 } 182 183 #ifdef MULTIPROCESSOR 184 static struct arm_cpu_method * 185 arm_fdt_cpu_enable_method_byname(const char *method) 186 { 187 __link_set_decl(arm_cpu_methods, struct arm_cpu_method); 188 struct arm_cpu_method * const *acmp; 189 190 __link_set_foreach(acmp, arm_cpu_methods) { 191 if (strcmp(method, (*acmp)->acm_compat) == 0) 192 return *acmp; 193 } 194 195 return NULL; 196 } 197 198 static struct arm_cpu_method * 199 arm_fdt_cpu_enable_method(int phandle) 200 { 201 const char *method; 202 203 method = fdtbus_get_string(phandle, "enable-method"); 204 if (method == NULL) 205 return NULL; 206 207 return arm_fdt_cpu_enable_method_byname(method); 208 } 209 210 static int 211 arm_fdt_cpu_enable(int phandle, struct arm_cpu_method *acm) 212 { 213 return acm->acm_enable(phandle); 214 } 215 #endif 216 217 int 218 arm_fdt_cpu_mpstart(void) 219 { 220 int ret = 0; 221 #ifdef MULTIPROCESSOR 222 uint64_t mpidr, bp_mpidr; 223 u_int cpuindex, i; 224 int child, error; 225 struct arm_cpu_method *acm; 226 227 const int cpus = OF_finddevice("/cpus"); 228 if (cpus == -1) { 229 aprint_error("%s: no /cpus node found\n", __func__); 230 return 0; 231 } 232 233 /* MPIDR affinity levels of boot processor. */ 234 bp_mpidr = cpu_mpidr_aff_read(); 235 236 /* Boot APs */ 237 cpuindex = 1; 238 for (child = OF_child(cpus); child; child = OF_peer(child)) { 239 if (!arm_fdt_cpu_okay(child)) 240 continue; 241 242 if (fdtbus_get_reg64(child, 0, &mpidr, NULL) != 0) 243 continue; 244 245 if (mpidr == bp_mpidr) 246 continue; /* BP already started */ 247 248 acm = arm_fdt_cpu_enable_method(child); 249 if (acm == NULL) 250 acm = arm_fdt_cpu_enable_method(cpus); 251 if (acm == NULL) 252 acm = arm_fdt_cpu_enable_method_byname("psci"); 253 if (acm == NULL) 254 continue; 255 256 error = arm_fdt_cpu_enable(child, acm); 257 if (error != 0) { 258 aprint_error("%s: failed to enable CPU %#" PRIx64 "\n", 259 __func__, mpidr); 260 continue; 261 } 262 263 /* Wake up AP in case firmware has placed it in WFE state */ 264 sev(); 265 266 /* Wait for AP to start */ 267 for (i = 0x10000000; i > 0; i--) { 268 if (cpu_hatched_p(cpuindex)) 269 break; 270 } 271 272 if (i == 0) { 273 ret++; 274 aprint_error("cpu%d: WARNING: AP failed to start\n", cpuindex); 275 } 276 277 cpuindex++; 278 } 279 #endif /* MULTIPROCESSOR */ 280 return ret; 281 } 282 283 static int 284 cpu_enable_nullop(int phandle) 285 { 286 return ENXIO; 287 } 288 ARM_CPU_METHOD(default, "", cpu_enable_nullop); 289 290 #if defined(MULTIPROCESSOR) && NPSCI_FDT > 0 291 static int 292 cpu_enable_psci(int phandle) 293 { 294 static bool psci_probed, psci_p; 295 uint64_t mpidr; 296 int ret; 297 298 if (!psci_probed) { 299 psci_probed = true; 300 psci_p = psci_fdt_preinit() == 0; 301 } 302 if (!psci_p) 303 return ENXIO; 304 305 fdtbus_get_reg64(phandle, 0, &mpidr, NULL); 306 307 #if !defined(AARCH64) 308 /* 309 * not necessary on AARCH64. beside there it hangs the system 310 * because cache ops are only functional after cpu_attach() 311 * was called. 312 */ 313 cpu_dcache_wbinv_all(); 314 #endif 315 ret = psci_cpu_on(mpidr, cpu_fdt_mpstart_pa(), 0); 316 if (ret != PSCI_SUCCESS) 317 return EIO; 318 319 return 0; 320 } 321 ARM_CPU_METHOD(psci, "psci", cpu_enable_psci); 322 #endif 323 324 #if defined(MULTIPROCESSOR) && defined(__aarch64__) 325 static int 326 spintable_cpu_on(const int phandle, u_int cpuindex, 327 paddr_t entry_point_address, paddr_t cpu_release_addr) 328 { 329 /* 330 * we need devmap for cpu-release-addr in advance. 331 * __HAVE_MM_MD_DIRECT_MAPPED_PHYS nor pmap work at this point. 332 */ 333 if (pmap_devmap_find_pa(cpu_release_addr, sizeof(paddr_t)) == NULL) { 334 aprint_error("%s: devmap for cpu-release-addr" 335 " 0x%08"PRIxPADDR" required\n", __func__, cpu_release_addr); 336 return -1; 337 } else { 338 extern struct bus_space arm_generic_bs_tag; 339 bus_space_handle_t ioh; 340 341 const int parent = OF_parent(phandle); 342 const int addr_cells = fdtbus_get_addr_cells(parent); 343 344 bus_space_map(&arm_generic_bs_tag, cpu_release_addr, 345 sizeof(paddr_t), 0, &ioh); 346 if (addr_cells == 1) { 347 bus_space_write_4(&arm_generic_bs_tag, ioh, 0, 348 entry_point_address); 349 } else { 350 bus_space_write_8(&arm_generic_bs_tag, ioh, 0, 351 entry_point_address); 352 } 353 bus_space_unmap(&arm_generic_bs_tag, ioh, sizeof(paddr_t)); 354 } 355 356 return 0; 357 } 358 359 static int 360 cpu_enable_spin_table(int phandle) 361 { 362 uint64_t mpidr, addr; 363 int ret; 364 365 fdtbus_get_reg64(phandle, 0, &mpidr, NULL); 366 367 if (of_getprop_uint64(phandle, "cpu-release-addr", &addr) != 0) 368 return ENXIO; 369 370 ret = spintable_cpu_on(phandle, mpidr, cpu_fdt_mpstart_pa(), 371 (paddr_t)addr); 372 if (ret != 0) 373 return EIO; 374 375 return 0; 376 } 377 ARM_CPU_METHOD(spin_table, "spin-table", cpu_enable_spin_table); 378 #endif 379