xref: /netbsd-src/sys/arch/arm/fdt/cpu_fdt.c (revision 796c32c94f6e154afc9de0f63da35c91bb739b45)
1 /* $NetBSD: cpu_fdt.c,v 1.3 2017/09/18 16:58:04 jmcneill Exp $ */
2 
3 /*-
4  * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: cpu_fdt.c,v 1.3 2017/09/18 16:58:04 jmcneill Exp $");
31 
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/device.h>
35 #include <sys/systm.h>
36 #include <sys/kernel.h>
37 
38 #include <dev/fdt/fdtvar.h>
39 
40 #include <arm/cpu.h>
41 
42 static int	cpu_fdt_match(device_t, cfdata_t, void *);
43 static void	cpu_fdt_attach(device_t, device_t, void *);
44 
45 enum cpu_fdt_type {
46 	ARM_CPU_UP = 1,
47 	ARM_CPU_ARMV7,
48 	ARM_CPU_ARMV8,
49 };
50 
51 struct cpu_fdt_softc {
52 	device_t		sc_dev;
53 	int			sc_phandle;
54 };
55 
56 static const struct of_compat_data compat_data[] = {
57 	{ "arm,arm1176jzf-s",		ARM_CPU_UP },
58 
59 	{ "arm,cortex-a5",		ARM_CPU_ARMV7 },
60 	{ "arm,cortex-a7",		ARM_CPU_ARMV7 },
61 	{ "arm,cortex-a8",		ARM_CPU_ARMV7 },
62 	{ "arm,cortex-a9",		ARM_CPU_ARMV7 },
63 	{ "arm,cortex-a12",		ARM_CPU_ARMV7 },
64 	{ "arm,cortex-a15",		ARM_CPU_ARMV7 },
65 	{ "arm,cortex-a17",		ARM_CPU_ARMV7 },
66 
67 	{ "arm,cortex-a53",		ARM_CPU_ARMV8 },
68 	{ "arm,cortex-a57",		ARM_CPU_ARMV8 },
69 	{ "arm,cortex-a72",		ARM_CPU_ARMV8 },
70 	{ "arm,cortex-a73",		ARM_CPU_ARMV8 },
71 	{ NULL }
72 };
73 
74 CFATTACH_DECL_NEW(cpu_fdt, sizeof(struct cpu_fdt_softc),
75 	cpu_fdt_match, cpu_fdt_attach, NULL, NULL);
76 
77 static int
78 cpu_fdt_match(device_t parent, cfdata_t cf, void *aux)
79 {
80 	struct fdt_attach_args * const faa = aux;
81 	const int phandle = faa->faa_phandle;
82 	enum cpu_fdt_type type;
83 	int is_compatible;
84 	bus_addr_t mpidr;
85 
86 	is_compatible = of_match_compat_data(phandle, compat_data);
87 	if (!is_compatible)
88 		return 0;
89 
90 	type = of_search_compatible(phandle, compat_data)->data;
91 	switch (type) {
92 	case ARM_CPU_ARMV7:
93 	case ARM_CPU_ARMV8:
94 		/* XXX NetBSD requires all CPUs to be in the same cluster */
95 		if (fdtbus_get_reg(phandle, 0, &mpidr, NULL) != 0)
96 			return 0;
97 		const uint32_t bp_mpidr = armreg_mpidr_read();
98 		const u_int bp_clid = __SHIFTOUT(bp_mpidr, CORTEXA9_MPIDR_CLID);
99 		const u_int clid = __SHIFTOUT(mpidr, CORTEXA9_MPIDR_CLID);
100 		if (bp_clid != clid)
101 			return 0;
102 		break;
103 	default:
104 		break;
105 	}
106 
107 	return is_compatible;
108 }
109 
110 static void
111 cpu_fdt_attach(device_t parent, device_t self, void *aux)
112 {
113 	struct cpu_fdt_softc * const sc = device_private(self);
114 	struct fdt_attach_args * const faa = aux;
115 	const int phandle = faa->faa_phandle;
116 	enum cpu_fdt_type type;
117 	bus_addr_t mpidr;
118 	cpuid_t cpuid;
119 
120 	sc->sc_dev = self;
121 	sc->sc_phandle = phandle;
122 
123 	type = of_search_compatible(phandle, compat_data)->data;
124 
125 	switch (type) {
126 	case ARM_CPU_ARMV7:
127 	case ARM_CPU_ARMV8:
128 		if (fdtbus_get_reg(phandle, 0, &mpidr, NULL) != 0) {
129 			aprint_error(": missing 'reg' property\n");
130 			return;
131 		}
132 		cpuid = __SHIFTOUT(mpidr, CORTEXA9_MPIDR_CPUID);
133 		break;
134 	default:
135 		cpuid = 0;
136 		break;
137 	}
138 
139 	/* Attach the CPU */
140 	cpu_attach(self, cpuid);
141 }
142