1 /* $NetBSD: epcomreg.h,v 1.2 2005/12/11 12:16:45 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Jesse Off 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Ichiro FUKUHARA. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA AND CONTRIBUTORS ``AS IS'' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS 25 * HEAD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 26 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _EPCOMREG_H_ 35 #define _EPCOMREG_H_ 36 37 #define EPCOM_FREQ 7372800 38 #define EPCOMSPEED2BRD(b) ((EPCOM_FREQ / (16 * (b))) - 1) 39 40 41 /* UART Data Register */ 42 #define EPCOM_Data 0x00000000UL 43 44 /* UART Receive Status/Error Clear Register */ 45 #define EPCOM_RXSts 0x00000004UL 46 #define RXSts_FE 0x01 47 #define RXSts_PE 0x02 48 #define RXSts_BE 0x04 49 #define RXSts_OE 0x08 50 51 /* UART Line Control Register High */ 52 #define EPCOM_LinCtrlHigh 0x00000008UL 53 #define LinCtrlHigh_BRK 0x01 54 #define LinCtrlHigh_PEN 0x02 55 #define LinCtrlHigh_EPS 0x04 56 #define LinCtrlHigh_STP2 0x08 57 #define LinCtrlHigh_FEN 0x10 58 #define LinCtrlHigh_WLEN 0x60 59 60 /* UART Line Control Register Middle */ 61 #define EPCOM_LinCtrlMid 0x0000000cUL 62 63 /* UART Line Control Register Low */ 64 #define EPCOM_LinCtrlLow 0x00000010UL 65 66 /* UART control register */ 67 #define EPCOM_Ctrl 0x00000014UL 68 #define Ctrl_UARTE 0x01 /* UART Enable */ 69 #define Ctrl_MSIE 0x08 /* Modem Status Interrupt Enable */ 70 #define Ctrl_RIE 0x10 /* Receive Interrupt Enable */ 71 #define Ctrl_TIE 0x20 /* Transmit Interrupt Enable */ 72 #define Ctrl_RTIE 0x40 /* Receive Timeout Enable */ 73 #define Ctrl_LBE 0x80 /* Loopback Enable */ 74 75 /* UART Flag register */ 76 #define EPCOM_Flag 0x00000018UL 77 #define Flag_CTS 0x01 /* Clear To Send status */ 78 #define Flag_DSR 0x02 /* Data Set Ready status */ 79 #define Flag_DCD 0x04 /* Data Carrier Detect status */ 80 #define Flag_BUSY 0x08 /* UART Busy */ 81 #define Flag_RXFE 0x10 /* Receive FIFO Empty */ 82 #define Flag_TXFF 0x20 /* Transmit FIFO Full */ 83 #define Flag_RXFF 0x40 /* Receive FIFO Full */ 84 #define Flag_TXFE 0x80 /* Transmit FIFO Empty */ 85 86 /* UART Interrupt Identification and Interrupt Clear Register */ 87 #define EPCOM_IntIDIntClr 0x0000001cUL 88 #define IntIDIntClr_MIS 0x01 /* Modem Interrupt Status */ 89 #define IntIDIntClr_RIS 0x01 /* Receive Interrupt Status */ 90 #define IntIDIntClr_TIS 0x01 /* Transmit Interrupt Status */ 91 #define IntIDIntClr_RTIS 0x01 /* Receive Timeout Interrupt Status */ 92 93 /* UART Modem Control Register */ 94 #define EPCOM_ModemCtrl 0x00000100UL 95 #define ModemCtrl_DTR 0x01 /* DTR output signal */ 96 #define ModemCtrl_RTS 0x02 /* RTS output signal */ 97 98 /* UART Modem Status Register */ 99 #define EPCOM_ModemSts 0x00000104UL 100 #define ModemSts_DCTS 0x01 /* Delta CTS */ 101 #define ModemSts_DDSR 0x02 /* Delta DSR */ 102 #define ModemSts_TERI 0x04 /* Trailing Edge Ring Indicator */ 103 #define ModemSts_DDCD 0x08 /* Delta DCD */ 104 #define ModemSts_CTS 0x10 /* Inverse CTSn input pin */ 105 #define ModemSts_DSR 0x20 /* Inverse of the DSRn pin */ 106 #define ModemSts_RI 0x40 /* Inverse of RI input pin */ 107 #define ModemSts_DCD 0x80 /* Inverse of DCDn input pin */ 108 109 #endif /* _EPCOMREG_H_ */ 110