1 /* $NetBSD: pl310.c,v 1.17 2015/02/27 20:40:09 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: pl310.c,v 1.17 2015/02/27 20:40:09 jmcneill Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/cpu.h> 38 #include <sys/device.h> 39 #include <sys/atomic.h> 40 41 #include <arm/locore.h> 42 43 #include <arm/cortex/mpcore_var.h> 44 #include <arm/cortex/pl310_reg.h> 45 #include <arm/cortex/pl310_var.h> 46 47 static int arml2cc_match(device_t, cfdata_t, void *); 48 static void arml2cc_attach(device_t, device_t, void *); 49 50 #define L2CC_BASE 0x2000 51 #define L2CC_SIZE 0x1000 52 53 struct arml2cc_softc { 54 device_t sc_dev; 55 bus_space_tag_t sc_memt; 56 bus_space_handle_t sc_memh; 57 kmutex_t sc_lock; 58 uint32_t sc_waymask; 59 struct evcnt sc_ev_inv __aligned(8); 60 struct evcnt sc_ev_wb; 61 struct evcnt sc_ev_wbinv; 62 bool sc_enabled; 63 }; 64 65 __CTASSERT(offsetof(struct arml2cc_softc, sc_ev_inv.ev_count) % 8 == 0); 66 __CTASSERT(offsetof(struct arml2cc_softc, sc_ev_wb.ev_count) % 8 == 0); 67 __CTASSERT(offsetof(struct arml2cc_softc, sc_ev_wbinv.ev_count) % 8 == 0); 68 69 CFATTACH_DECL_NEW(arml2cc, sizeof(struct arml2cc_softc), 70 arml2cc_match, arml2cc_attach, NULL, NULL); 71 72 static inline void arml2cc_disable(struct arml2cc_softc *); 73 static inline void arml2cc_enable(struct arml2cc_softc *); 74 static void arml2cc_sdcache_wb_range(vaddr_t, paddr_t, psize_t); 75 static void arml2cc_sdcache_inv_range(vaddr_t, paddr_t, psize_t); 76 static void arml2cc_sdcache_wbinv_range(vaddr_t, paddr_t, psize_t); 77 78 static struct arml2cc_softc *arml2cc_sc; 79 80 static inline uint32_t 81 arml2cc_read_4(struct arml2cc_softc *sc, bus_size_t o) 82 { 83 return bus_space_read_4(sc->sc_memt, sc->sc_memh, o); 84 } 85 86 static inline void 87 arml2cc_write_4(struct arml2cc_softc *sc, bus_size_t o, uint32_t v) 88 { 89 bus_space_write_4(sc->sc_memt, sc->sc_memh, o, v); 90 } 91 92 93 /* ARGSUSED */ 94 static int 95 arml2cc_match(device_t parent, cfdata_t cf, void *aux) 96 { 97 struct mpcore_attach_args * const mpcaa = aux; 98 99 if (arml2cc_sc) 100 return 0; 101 102 if (!CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid) && 103 !CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid)) 104 return 0; 105 106 if (strcmp(mpcaa->mpcaa_name, cf->cf_name) != 0) 107 return 0; 108 109 /* 110 * This isn't present on UP A9s (since CBAR isn't present). 111 */ 112 uint32_t mpidr = armreg_mpidr_read(); 113 if (mpidr == 0 || (mpidr & MPIDR_U)) 114 return 0; 115 116 return 1; 117 } 118 119 static const struct { 120 uint8_t rev; 121 uint8_t str[7]; 122 } pl310_revs[] = { 123 { 0, " r0p0" }, 124 { 2, " r1p0" }, 125 { 4, " r2p0" }, 126 { 5, " r3p0" }, 127 { 6, " r3p1" }, 128 { 7, " r3p1a" }, 129 { 8, " r3p2" }, 130 { 9, " r3p3" }, 131 }; 132 133 static void 134 arml2cc_attach(device_t parent, device_t self, void *aux) 135 { 136 struct arml2cc_softc * const sc = device_private(self); 137 struct mpcore_attach_args * const mpcaa = aux; 138 const char * const xname = device_xname(self); 139 prop_dictionary_t dict = device_properties(self); 140 uint32_t off; 141 142 aprint_naive("\n"); 143 144 if (!prop_dictionary_get_uint32(dict, "offset", &off)) { 145 if (CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid)) { 146 /* 147 * PL310 on Cortex-A5 is external to PERIPHBASE, so 148 * "offset" property is required. 149 */ 150 aprint_normal(": not configured\n"); 151 return; 152 } 153 off = L2CC_BASE; 154 } 155 156 arml2cc_sc = sc; 157 sc->sc_dev = self; 158 sc->sc_memt = mpcaa->mpcaa_memt; 159 sc->sc_waymask = __BIT(arm_scache.dcache_ways) - 1; 160 161 evcnt_attach_dynamic(&sc->sc_ev_inv, EVCNT_TYPE_MISC, NULL, 162 xname, "L2 inv requests"); 163 evcnt_attach_dynamic(&sc->sc_ev_wb, EVCNT_TYPE_MISC, NULL, 164 xname, "L2 wb requests"); 165 evcnt_attach_dynamic(&sc->sc_ev_wbinv, EVCNT_TYPE_MISC, NULL, 166 xname, "L2 wbinv requests"); 167 168 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 169 170 bus_space_subregion(sc->sc_memt, mpcaa->mpcaa_memh, 171 off, L2CC_SIZE, &sc->sc_memh); 172 173 uint32_t id = arml2cc_read_4(sc, L2C_CACHE_ID); 174 u_int rev = __SHIFTOUT(id, CACHE_ID_REV); 175 176 const char *revstr = ""; 177 for (size_t i = 0; i < __arraycount(pl310_revs); i++) { 178 if (rev == pl310_revs[i].rev) { 179 revstr = pl310_revs[i].str; 180 break; 181 } 182 } 183 184 const bool enabled_p = arml2cc_read_4(sc, L2C_CTL) != 0; 185 186 aprint_normal(": ARM PL310%s L2 Cache Controller%s\n", 187 revstr, enabled_p ? "" : " (disabled)"); 188 189 if (enabled_p) { 190 if (device_cfdata(self)->cf_flags & 1) { 191 arml2cc_disable(sc); 192 aprint_normal_dev(self, "cache %s\n", 193 arml2cc_read_4(sc, L2C_CTL) ? "enabled" : "disabled"); 194 sc->sc_enabled = false; 195 } else { 196 cpufuncs.cf_sdcache_wb_range = arml2cc_sdcache_wb_range; 197 cpufuncs.cf_sdcache_inv_range = arml2cc_sdcache_inv_range; 198 cpufuncs.cf_sdcache_wbinv_range = arml2cc_sdcache_wbinv_range; 199 sc->sc_enabled = true; 200 } 201 } else if ((device_cfdata(self)->cf_flags & 1) == 0) { 202 if (!enabled_p) { 203 arml2cc_enable(sc); 204 aprint_normal_dev(self, "cache %s\n", 205 arml2cc_read_4(sc, L2C_CTL) ? "enabled" : "disabled"); 206 } 207 cpufuncs.cf_sdcache_wb_range = arml2cc_sdcache_wb_range; 208 cpufuncs.cf_sdcache_inv_range = arml2cc_sdcache_inv_range; 209 cpufuncs.cf_sdcache_wbinv_range = arml2cc_sdcache_wbinv_range; 210 sc->sc_enabled = true; 211 } 212 213 KASSERTMSG(arm_pcache.dcache_line_size == arm_scache.dcache_line_size, 214 "pcache %u scache %u", 215 arm_pcache.dcache_line_size, arm_scache.dcache_line_size); 216 } 217 218 static inline void 219 arml2cc_cache_op(struct arml2cc_softc *sc, bus_size_t off, uint32_t val, 220 bool wait) 221 { 222 arml2cc_write_4(sc, off, val); 223 if (wait) { 224 while (arml2cc_read_4(sc, off) & 1) { 225 /* spin */ 226 } 227 } 228 } 229 230 static inline void 231 arml2cc_cache_way_op(struct arml2cc_softc *sc, bus_size_t off, uint32_t way_mask) 232 { 233 arml2cc_write_4(sc, off, way_mask); 234 while (arml2cc_read_4(sc, off) & way_mask) { 235 /* spin */ 236 } 237 } 238 239 static inline void 240 arml2cc_cache_sync(struct arml2cc_softc *sc) 241 { 242 arml2cc_cache_op(sc, L2C_CACHE_SYNC, 0, true); 243 } 244 245 static inline void 246 arml2cc_disable(struct arml2cc_softc *sc) 247 { 248 mutex_spin_enter(&sc->sc_lock); 249 250 arml2cc_cache_way_op(sc, L2C_CLEAN_INV_WAY, sc->sc_waymask); 251 arml2cc_cache_sync(sc); 252 253 arml2cc_write_4(sc, L2C_CTL, 0); // turn it off 254 mutex_spin_exit(&sc->sc_lock); 255 } 256 257 static inline void 258 arml2cc_enable(struct arml2cc_softc *sc) 259 { 260 mutex_spin_enter(&sc->sc_lock); 261 262 arml2cc_cache_way_op(sc, L2C_INV_WAY, sc->sc_waymask); 263 arml2cc_cache_sync(sc); 264 265 arml2cc_write_4(sc, L2C_CTL, 1); // turn it on 266 267 mutex_spin_exit(&sc->sc_lock); 268 } 269 270 void 271 arml2cc_init(bus_space_tag_t bst, bus_space_handle_t bsh, bus_size_t o) 272 { 273 struct arm_cache_info * const info = &arm_scache; 274 275 uint32_t cfg = bus_space_read_4(bst, bsh, o + L2C_CACHE_TYPE); 276 277 info->cache_type = __SHIFTOUT(cfg, CACHE_TYPE_CTYPE); 278 info->cache_unified = __SHIFTOUT(cfg, CACHE_TYPE_HARVARD) == 0; 279 u_int cfg_dsize = __SHIFTOUT(cfg, CACHE_TYPE_DSIZE); 280 281 u_int d_waysize = 8192 << __SHIFTOUT(cfg_dsize, CACHE_TYPE_xWAYSIZE); 282 info->dcache_ways = 8 << __SHIFTOUT(cfg_dsize, CACHE_TYPE_xASSOC); 283 info->dcache_line_size = 32 << __SHIFTOUT(cfg_dsize, CACHE_TYPE_xLINESIZE); 284 info->dcache_size = info->dcache_ways * d_waysize; 285 info->dcache_type = CACHE_TYPE_PIPT; 286 info->icache_type = CACHE_TYPE_PIPT; 287 288 if (info->cache_unified) { 289 info->icache_ways = info->dcache_ways; 290 info->icache_line_size = info->dcache_line_size; 291 info->icache_size = info->dcache_size; 292 } else { 293 u_int cfg_isize = __SHIFTOUT(cfg, CACHE_TYPE_ISIZE); 294 u_int i_waysize = 8192 << __SHIFTOUT(cfg_isize, CACHE_TYPE_xWAYSIZE); 295 info->icache_ways = 8 << __SHIFTOUT(cfg_isize, CACHE_TYPE_xASSOC); 296 info->icache_line_size = 32 << __SHIFTOUT(cfg_isize, CACHE_TYPE_xLINESIZE); 297 info->icache_size = i_waysize * info->icache_ways; 298 } 299 } 300 301 static void 302 arml2cc_cache_range_op(paddr_t pa, psize_t len, bus_size_t cache_op) 303 { 304 struct arml2cc_softc * const sc = arml2cc_sc; 305 const size_t line_size = arm_scache.dcache_line_size; 306 const size_t line_mask = line_size - 1; 307 size_t off = pa & line_mask; 308 if (off) { 309 len += off; 310 pa -= off; 311 } 312 len = roundup2(len, line_size); 313 mutex_spin_enter(&sc->sc_lock); 314 if (__predict_false(!sc->sc_enabled)) { 315 mutex_spin_exit(&sc->sc_lock); 316 return; 317 } 318 for (const paddr_t endpa = pa + len; pa < endpa; pa += line_size) { 319 arml2cc_cache_op(sc, cache_op, pa, false); 320 } 321 arml2cc_cache_sync(sc); 322 mutex_spin_exit(&sc->sc_lock); 323 } 324 325 static void 326 arml2cc_sdcache_inv_range(vaddr_t va, paddr_t pa, psize_t len) 327 { 328 atomic_inc_64(&arml2cc_sc->sc_ev_inv.ev_count); 329 arml2cc_cache_range_op(pa, len, L2C_INV_PA); 330 } 331 332 static void 333 arml2cc_sdcache_wb_range(vaddr_t va, paddr_t pa, psize_t len) 334 { 335 atomic_inc_64(&arml2cc_sc->sc_ev_wb.ev_count); 336 arml2cc_cache_range_op(pa, len, L2C_CLEAN_PA); 337 } 338 339 static void 340 arml2cc_sdcache_wbinv_range(vaddr_t va, paddr_t pa, psize_t len) 341 { 342 atomic_inc_64(&arml2cc_sc->sc_ev_wbinv.ev_count); 343 arml2cc_cache_range_op(pa, len, L2C_CLEAN_INV_PA); 344 } 345