1 /* $NetBSD: gtmr.c,v 1.23 2017/11/30 14:50:34 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.23 2017/11/30 14:50:34 skrll Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/kernel.h> 40 #include <sys/percpu.h> 41 #include <sys/proc.h> 42 #include <sys/systm.h> 43 #include <sys/timetc.h> 44 45 #include <prop/proplib.h> 46 47 #include <arm/locore.h> 48 49 #include <arm/cortex/gtmr_var.h> 50 51 #include <arm/cortex/mpcore_var.h> 52 53 static int gtmr_match(device_t, cfdata_t, void *); 54 static void gtmr_attach(device_t, device_t, void *); 55 56 static u_int gtmr_get_timecount(struct timecounter *); 57 58 static struct gtmr_softc gtmr_sc; 59 60 struct gtmr_percpu { 61 uint32_t pc_delta; 62 }; 63 64 static struct timecounter gtmr_timecounter = { 65 .tc_get_timecount = gtmr_get_timecount, 66 .tc_poll_pps = 0, 67 .tc_counter_mask = ~0u, 68 .tc_frequency = 0, /* set by cpu_initclocks() */ 69 .tc_name = NULL, /* set by attach */ 70 .tc_quality = 500, 71 .tc_priv = >mr_sc, 72 .tc_next = NULL, 73 }; 74 75 CFATTACH_DECL_NEW(armgtmr, 0, gtmr_match, gtmr_attach, NULL, NULL); 76 77 /* ARGSUSED */ 78 static int 79 gtmr_match(device_t parent, cfdata_t cf, void *aux) 80 { 81 struct mpcore_attach_args * const mpcaa = aux; 82 83 if (gtmr_sc.sc_dev != NULL) 84 return 0; 85 86 if ((armreg_pfr1_read() & ARM_PFR1_GTIMER_MASK) == 0) 87 return 0; 88 89 if (strcmp(mpcaa->mpcaa_name, cf->cf_name) != 0) 90 return 0; 91 92 return 1; 93 } 94 95 static void 96 gtmr_attach(device_t parent, device_t self, void *aux) 97 { 98 struct mpcore_attach_args * const mpcaa = aux; 99 struct gtmr_softc *sc = >mr_sc; 100 prop_dictionary_t dict = device_properties(self); 101 char freqbuf[sizeof("X.XXX SHz")]; 102 103 /* 104 * This runs at a fixed frequency of 1 to 50MHz. 105 */ 106 if (!prop_dictionary_get_uint32(dict, "frequency", &sc->sc_freq)) 107 sc->sc_freq = armreg_cnt_frq_read(); 108 109 KASSERT(sc->sc_freq != 0); 110 111 humanize_number(freqbuf, sizeof(freqbuf), sc->sc_freq, "Hz", 1000); 112 113 aprint_naive("\n"); 114 aprint_normal(": ARMv7 Generic 64-bit Timer (%s)\n", freqbuf); 115 116 /* 117 * Enable the virtual counter to be accessed from usermode. 118 */ 119 armreg_cntk_ctl_write(armreg_cntk_ctl_read() | 120 ARM_CNTKCTL_PL0VCTEN | ARM_CNTKCTL_PL0PCTEN); 121 122 self->dv_private = sc; 123 sc->sc_dev = self; 124 125 #ifdef DIAGNOSTIC 126 sc->sc_percpu = percpu_alloc(sizeof(struct gtmr_percpu)); 127 #endif 128 129 evcnt_attach_dynamic(&sc->sc_ev_missing_ticks, EVCNT_TYPE_MISC, NULL, 130 device_xname(self), "missing interrupts"); 131 132 if (mpcaa->mpcaa_irq != -1) { 133 sc->sc_global_ih = intr_establish(mpcaa->mpcaa_irq, IPL_CLOCK, 134 IST_LEVEL | IST_MPSAFE, gtmr_intr, NULL); 135 if (sc->sc_global_ih == NULL) 136 panic("%s: unable to register timer interrupt", __func__); 137 aprint_normal_dev(self, "interrupting on irq %d\n", 138 mpcaa->mpcaa_irq); 139 } 140 141 const uint32_t cnt_frq = armreg_cnt_frq_read(); 142 if (cnt_frq == 0) { 143 aprint_verbose_dev(self, "cp15 CNT_FRQ not set\n"); 144 } else if (cnt_frq != sc->sc_freq) { 145 aprint_verbose_dev(self, 146 "cp15 CNT_FRQ (%u) differs from supplied frequency\n", 147 cnt_frq); 148 } 149 150 gtmr_timecounter.tc_name = device_xname(sc->sc_dev); 151 gtmr_timecounter.tc_frequency = sc->sc_freq; 152 153 tc_init(>mr_timecounter); 154 155 /* Disable the timer until we are ready */ 156 armreg_cntv_ctl_write(0); 157 armreg_cntp_ctl_write(0); 158 } 159 160 void 161 gtmr_init_cpu_clock(struct cpu_info *ci) 162 { 163 struct gtmr_softc * const sc = >mr_sc; 164 165 KASSERT(ci == curcpu()); 166 167 int s = splsched(); 168 169 /* 170 * enable timer and stop masking the timer. 171 */ 172 armreg_cntv_ctl_write(ARM_CNTCTL_ENABLE); 173 armreg_cntp_ctl_write(ARM_CNTCTL_ENABLE); 174 #if 0 175 printf("%s: cntctl=%#x\n", __func__, armreg_cntv_ctl_read()); 176 #endif 177 178 /* 179 * Get now and update the compare timer. 180 */ 181 arm_isb(); 182 ci->ci_lastintr = armreg_cntv_ct_read(); 183 armreg_cntv_tval_write(sc->sc_autoinc); 184 #if 0 185 printf("%s: %s: delta cval = %"PRIu64"\n", 186 __func__, ci->ci_data.cpu_name, 187 armreg_cntv_cval_read() - ci->ci_lastintr); 188 #endif 189 splx(s); 190 KASSERT(armreg_cntv_ct_read() != 0); 191 #if 0 192 printf("%s: %s: ctl %#x cmp %#"PRIx64" now %#"PRIx64"\n", 193 __func__, ci->ci_data.cpu_name, armreg_cntv_ctl_read(), 194 armreg_cntv_cval_read(), armreg_cntv_ct_read()); 195 196 s = splsched(); 197 198 arm_isb(); 199 uint64_t now64; 200 uint64_t start64 = armreg_cntv_ct_read(); 201 do { 202 arm_isb(); 203 now64 = armreg_cntv_ct_read(); 204 } while (start64 == now64); 205 start64 = now64; 206 uint64_t end64 = start64 + 64; 207 uint32_t start32 = armreg_pmccntr_read(); 208 do { 209 arm_isb(); 210 now64 = armreg_cntv_ct_read(); 211 } while (end64 != now64); 212 uint32_t end32 = armreg_pmccntr_read(); 213 214 uint32_t diff32 = end64 - start64; 215 printf("%s: %s: %u cycles per tick\n", 216 __func__, ci->ci_data.cpu_name, (end32 - start32) / diff32); 217 218 printf("%s: %s: status %#x cmp %#"PRIx64" now %#"PRIx64"\n", 219 __func__, ci->ci_data.cpu_name, armreg_cntv_ctl_read(), 220 armreg_cntv_cval_read(), armreg_cntv_ct_read()); 221 splx(s); 222 #elif 0 223 delay(1000000 / hz + 1000); 224 #endif 225 } 226 227 void 228 gtmr_cpu_initclocks(void) 229 { 230 struct gtmr_softc * const sc = >mr_sc; 231 232 KASSERT(sc->sc_dev != NULL); 233 KASSERT(sc->sc_freq != 0); 234 235 sc->sc_autoinc = sc->sc_freq / hz; 236 237 gtmr_init_cpu_clock(curcpu()); 238 } 239 240 void 241 gtmr_delay(unsigned int n) 242 { 243 struct gtmr_softc * const sc = >mr_sc; 244 245 KASSERT(sc != NULL); 246 247 uint32_t freq = sc->sc_freq ? sc->sc_freq : armreg_cnt_frq_read(); 248 KASSERT(freq != 0); 249 250 const unsigned int incr_per_us = howmany(freq, 1000000); 251 unsigned int delta = 0, usecs = 0; 252 253 arm_isb(); 254 uint64_t last = armreg_cntp_ct_read(); 255 256 while (n > usecs) { 257 arm_isb(); 258 uint64_t curr = armreg_cntp_ct_read(); 259 if (curr < last) 260 delta += curr + (UINT64_MAX - last); 261 else 262 delta += curr - last; 263 264 last = curr; 265 if (delta >= incr_per_us) { 266 usecs += delta / incr_per_us; 267 delta %= incr_per_us; 268 } 269 } 270 } 271 272 void 273 gtmr_bootdelay(unsigned int ticks) 274 { 275 const uint32_t ctl = armreg_cntv_ctl_read(); 276 armreg_cntv_ctl_write(ctl | ARM_CNTCTL_ENABLE | ARM_CNTCTL_IMASK); 277 278 /* Write Timer/Value to set new compare time */ 279 armreg_cntv_tval_write(ticks); 280 281 /* Spin until compare time is hit */ 282 while ((armreg_cntv_ctl_read() & ARM_CNTCTL_ISTATUS) == 0) { 283 /* spin */ 284 } 285 286 armreg_cntv_ctl_write(ctl); 287 } 288 289 /* 290 * gtmr_intr: 291 * 292 * Handle the hardclock interrupt. 293 */ 294 int 295 gtmr_intr(void *arg) 296 { 297 struct cpu_info * const ci = curcpu(); 298 struct clockframe * const cf = arg; 299 struct gtmr_softc * const sc = >mr_sc; 300 301 arm_isb(); 302 303 const uint32_t ctl = armreg_cntv_ctl_read(); 304 if ((ctl & ARM_CNTCTL_ISTATUS) == 0) 305 return 0; 306 307 const uint64_t now = armreg_cntv_ct_read(); 308 uint64_t delta = now - ci->ci_lastintr; 309 310 #ifdef DIAGNOSTIC 311 const uint64_t then = armreg_cntv_cval_read(); 312 struct gtmr_percpu * const pc = percpu_getref(sc->sc_percpu); 313 KASSERTMSG(then <= now, "%"PRId64, now - then); 314 KASSERTMSG(then + pc->pc_delta >= ci->ci_lastintr + sc->sc_autoinc, 315 "%"PRId64, then + pc->pc_delta - ci->ci_lastintr - sc->sc_autoinc); 316 #endif 317 318 #if 0 319 printf("%s(%p): %s: now %#"PRIx64" delta %"PRIu64"\n", 320 __func__, cf, ci->ci_data.cpu_name, now, delta); 321 #endif 322 KASSERTMSG(delta > sc->sc_autoinc / 100, 323 "%s: interrupting too quickly (delta=%"PRIu64") autoinc=%lu", 324 ci->ci_data.cpu_name, delta, sc->sc_autoinc); 325 326 /* 327 * If we got interrupted too soon (delta < sc->sc_autoinc) 328 * or we missed (or almost missed) a tick 329 * (delta >= 7 * sc->sc_autoinc / 4), don't try to adjust for jitter. 330 */ 331 if (delta >= sc->sc_autoinc && delta <= 7 * sc->sc_autoinc / 4) { 332 delta -= sc->sc_autoinc; 333 } else { 334 delta = 0; 335 } 336 armreg_cntv_tval_write(sc->sc_autoinc - delta); 337 338 ci->ci_lastintr = now; 339 340 #ifdef DIAGNOSTIC 341 KASSERT(delta == (uint32_t) delta); 342 pc->pc_delta = delta; 343 percpu_putref(sc->sc_percpu); 344 #endif 345 346 hardclock(cf); 347 348 sc->sc_ev_missing_ticks.ev_count += delta / sc->sc_autoinc; 349 350 return 1; 351 } 352 353 void 354 setstatclockrate(int newhz) 355 { 356 } 357 358 static u_int 359 gtmr_get_timecount(struct timecounter *tc) 360 { 361 arm_isb(); // we want the time NOW, not some instructions later. 362 return (u_int) armreg_cntp_ct_read(); 363 } 364