1 /* $NetBSD: gtmr.c,v 1.16 2015/04/20 20:19:52 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.16 2015/04/20 20:19:52 matt Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/kernel.h> 40 #include <sys/percpu.h> 41 #include <sys/proc.h> 42 #include <sys/systm.h> 43 #include <sys/timetc.h> 44 45 #include <prop/proplib.h> 46 47 #include <arm/locore.h> 48 49 #include <arm/cortex/gtmr_var.h> 50 51 #include <arm/cortex/mpcore_var.h> 52 53 static int gtmr_match(device_t, cfdata_t, void *); 54 static void gtmr_attach(device_t, device_t, void *); 55 56 static u_int gtmr_get_timecount(struct timecounter *); 57 58 static struct gtmr_softc gtmr_sc; 59 60 struct gtmr_percpu { 61 uint32_t pc_delta; 62 }; 63 64 static struct timecounter gtmr_timecounter = { 65 .tc_get_timecount = gtmr_get_timecount, 66 .tc_poll_pps = 0, 67 .tc_counter_mask = ~0u, 68 .tc_frequency = 0, /* set by cpu_initclocks() */ 69 .tc_name = NULL, /* set by attach */ 70 .tc_quality = 500, 71 .tc_priv = >mr_sc, 72 .tc_next = NULL, 73 }; 74 75 CFATTACH_DECL_NEW(armgtmr, 0, gtmr_match, gtmr_attach, NULL, NULL); 76 77 /* ARGSUSED */ 78 static int 79 gtmr_match(device_t parent, cfdata_t cf, void *aux) 80 { 81 struct mpcore_attach_args * const mpcaa = aux; 82 83 if (gtmr_sc.sc_dev != NULL) 84 return 0; 85 86 if ((armreg_pfr1_read() & ARM_PFR1_GTIMER_MASK) == 0) 87 return 0; 88 89 if (strcmp(mpcaa->mpcaa_name, cf->cf_name) != 0) 90 return 0; 91 92 return 1; 93 } 94 95 static void 96 gtmr_attach(device_t parent, device_t self, void *aux) 97 { 98 struct mpcore_attach_args * const mpcaa = aux; 99 struct gtmr_softc *sc = >mr_sc; 100 prop_dictionary_t dict = device_properties(self); 101 char freqbuf[sizeof("X.XXX SHz")]; 102 103 /* 104 * This runs at a fixed frequency of 1 to 50MHz. 105 */ 106 prop_dictionary_get_uint32(dict, "frequency", &sc->sc_freq); 107 KASSERT(sc->sc_freq != 0); 108 109 humanize_number(freqbuf, sizeof(freqbuf), sc->sc_freq, "Hz", 1000); 110 111 aprint_naive("\n"); 112 aprint_normal(": ARMv7 Generic 64-bit Timer (%s)\n", freqbuf); 113 114 /* 115 * Enable the virtual counter to be accessed from usermode. 116 */ 117 armreg_cntk_ctl_write(armreg_cntk_ctl_read() | 118 ARM_CNTKCTL_PL0VCTEN | ARM_CNTKCTL_PL0PCTEN); 119 120 self->dv_private = sc; 121 sc->sc_dev = self; 122 123 #ifdef DIAGNOSTIC 124 sc->sc_percpu = percpu_alloc(sizeof(struct gtmr_percpu)); 125 #endif 126 127 evcnt_attach_dynamic(&sc->sc_ev_missing_ticks, EVCNT_TYPE_MISC, NULL, 128 device_xname(self), "missing interrupts"); 129 130 sc->sc_global_ih = intr_establish(mpcaa->mpcaa_irq, IPL_CLOCK, 131 IST_LEVEL | IST_MPSAFE, gtmr_intr, NULL); 132 if (sc->sc_global_ih == NULL) 133 panic("%s: unable to register timer interrupt", __func__); 134 aprint_normal_dev(self, "interrupting on irq %d\n", 135 mpcaa->mpcaa_irq); 136 137 const uint32_t cnt_frq = armreg_cnt_frq_read(); 138 if (cnt_frq == 0) { 139 aprint_verbose_dev(self, "cp15 CNT_FRQ not set\n"); 140 } else if (cnt_frq != sc->sc_freq) { 141 aprint_verbose_dev(self, 142 "cp15 CNT_FRQ (%u) differs from supplied frequency\n", 143 cnt_frq); 144 } 145 146 gtmr_timecounter.tc_name = device_xname(sc->sc_dev); 147 gtmr_timecounter.tc_frequency = sc->sc_freq; 148 149 tc_init(>mr_timecounter); 150 } 151 152 void 153 gtmr_init_cpu_clock(struct cpu_info *ci) 154 { 155 struct gtmr_softc * const sc = >mr_sc; 156 157 KASSERT(ci == curcpu()); 158 159 int s = splsched(); 160 161 /* 162 * enable timer and stop masking the timer. 163 */ 164 armreg_cntv_ctl_write(ARM_CNTCTL_ENABLE); 165 armreg_cntp_ctl_write(ARM_CNTCTL_ENABLE); 166 #if 0 167 printf("%s: cntctl=%#x\n", __func__, armreg_cntv_ctl_read()); 168 #endif 169 170 /* 171 * Get now and update the compare timer. 172 */ 173 arm_isb(); 174 ci->ci_lastintr = armreg_cntv_ct_read(); 175 armreg_cntv_tval_write(sc->sc_autoinc); 176 #if 0 177 printf("%s: %s: delta cval = %"PRIu64"\n", 178 __func__, ci->ci_data.cpu_name, 179 armreg_cntv_cval_read() - ci->ci_lastintr); 180 #endif 181 splx(s); 182 KASSERT(armreg_cntv_ct_read() != 0); 183 #if 0 184 printf("%s: %s: ctl %#x cmp %#"PRIx64" now %#"PRIx64"\n", 185 __func__, ci->ci_data.cpu_name, armreg_cntv_ctl_read(), 186 armreg_cntv_cval_read(), armreg_cntv_ct_read()); 187 188 s = splsched(); 189 190 arm_isb(); 191 uint64_t now64; 192 uint64_t start64 = armreg_cntv_ct_read(); 193 do { 194 arm_isb(); 195 now64 = armreg_cntv_ct_read(); 196 } while (start64 == now64); 197 start64 = now64; 198 uint64_t end64 = start64 + 64; 199 uint32_t start32 = armreg_pmccntr_read(); 200 do { 201 arm_isb(); 202 now64 = armreg_cntv_ct_read(); 203 } while (end64 != now64); 204 uint32_t end32 = armreg_pmccntr_read(); 205 206 uint32_t diff32 = end64 - start64; 207 printf("%s: %s: %u cycles per tick\n", 208 __func__, ci->ci_data.cpu_name, (end32 - start32) / diff32); 209 210 printf("%s: %s: status %#x cmp %#"PRIx64" now %#"PRIx64"\n", 211 __func__, ci->ci_data.cpu_name, armreg_cntv_ctl_read(), 212 armreg_cntv_cval_read(), armreg_cntv_ct_read()); 213 splx(s); 214 #elif 0 215 delay(1000000 / hz + 1000); 216 #endif 217 } 218 219 void 220 cpu_initclocks(void) 221 { 222 struct gtmr_softc * const sc = >mr_sc; 223 224 KASSERT(sc->sc_dev != NULL); 225 KASSERT(sc->sc_freq != 0); 226 227 sc->sc_autoinc = sc->sc_freq / hz; 228 229 gtmr_init_cpu_clock(curcpu()); 230 } 231 232 void 233 gtmr_delay(unsigned int n) 234 { 235 struct gtmr_softc * const sc = >mr_sc; 236 237 KASSERT(sc != NULL); 238 239 uint32_t freq = sc->sc_freq ? sc->sc_freq : armreg_cnt_frq_read(); 240 KASSERT(freq != 0); 241 242 /* 243 * not quite divide by 1000000 but close enough 244 * (higher by 1.3% which means we wait 1.3% longer). 245 */ 246 const uint64_t incr_per_us = (freq >> 20) + (freq >> 24); 247 248 arm_isb(); 249 const uint64_t base = armreg_cntp_ct_read(); 250 const uint64_t delta = n * incr_per_us; 251 const uint64_t finish = base + delta; 252 253 while (armreg_cntp_ct_read() < finish) { 254 arm_isb(); /* spin */ 255 } 256 } 257 258 void 259 gtmr_bootdelay(unsigned int ticks) 260 { 261 const uint32_t ctl = armreg_cntv_ctl_read(); 262 armreg_cntv_ctl_write(ctl | ARM_CNTCTL_ENABLE | ARM_CNTCTL_IMASK); 263 264 /* Write Timer/Value to set new compare time */ 265 armreg_cntv_tval_write(ticks); 266 267 /* Spin until compare time is hit */ 268 while ((armreg_cntv_ctl_read() & ARM_CNTCTL_ISTATUS) == 0) { 269 /* spin */ 270 } 271 272 armreg_cntv_ctl_write(ctl); 273 } 274 275 /* 276 * gtmr_intr: 277 * 278 * Handle the hardclock interrupt. 279 */ 280 int 281 gtmr_intr(void *arg) 282 { 283 struct cpu_info * const ci = curcpu(); 284 struct clockframe * const cf = arg; 285 struct gtmr_softc * const sc = >mr_sc; 286 287 arm_isb(); 288 289 const uint64_t now = armreg_cntv_ct_read(); 290 uint64_t delta = now - ci->ci_lastintr; 291 292 #ifdef DIAGNOSTIC 293 const uint64_t then = armreg_cntv_cval_read(); 294 struct gtmr_percpu * const pc = percpu_getref(sc->sc_percpu); 295 KASSERTMSG(then <= now, "%"PRId64, now - then); 296 KASSERTMSG(then + pc->pc_delta >= ci->ci_lastintr + sc->sc_autoinc, 297 "%"PRId64, then + pc->pc_delta - ci->ci_lastintr - sc->sc_autoinc); 298 #endif 299 300 #if 0 301 printf("%s(%p): %s: now %#"PRIx64" delta %"PRIu64"\n", 302 __func__, cf, ci->ci_data.cpu_name, now, delta); 303 #endif 304 KASSERTMSG(delta > sc->sc_autoinc / 100, 305 "%s: interrupting too quickly (delta=%"PRIu64") autoinc=%lu", 306 ci->ci_data.cpu_name, delta, sc->sc_autoinc); 307 308 /* 309 * If we got interrupted too soon (delta < sc->sc_autoinc) 310 * or we missed (or almost missed) a tick 311 * (delta >= 7 * sc->sc_autoinc / 4), don't try to adjust for jitter. 312 */ 313 if (delta >= sc->sc_autoinc && delta <= 7 * sc->sc_autoinc / 4) { 314 delta -= sc->sc_autoinc; 315 } else { 316 delta = 0; 317 } 318 armreg_cntv_tval_write(sc->sc_autoinc - delta); 319 320 ci->ci_lastintr = now; 321 322 #ifdef DIAGNOSTIC 323 KASSERT(delta == (uint32_t) delta); 324 pc->pc_delta = delta; 325 percpu_putref(sc->sc_percpu); 326 #endif 327 328 hardclock(cf); 329 330 sc->sc_ev_missing_ticks.ev_count += delta / sc->sc_autoinc; 331 332 return 1; 333 } 334 335 void 336 setstatclockrate(int newhz) 337 { 338 } 339 340 static u_int 341 gtmr_get_timecount(struct timecounter *tc) 342 { 343 arm_isb(); // we want the time NOW, not some instructions later. 344 return (u_int) armreg_cntp_ct_read(); 345 } 346