1 /* $NetBSD: gtmr.c,v 1.48 2021/11/13 18:30:27 jakllsch Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.48 2021/11/13 18:30:27 jakllsch Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/kernel.h> 40 #include <sys/percpu.h> 41 #include <sys/proc.h> 42 #include <sys/systm.h> 43 #include <sys/timetc.h> 44 #include <sys/cpu.h> 45 46 #include <prop/proplib.h> 47 48 #include <arm/locore.h> 49 #include <arm/cpufunc.h> 50 51 #include <arm/cortex/gtmr_var.h> 52 #include <arm/cortex/mpcore_var.h> 53 54 static int gtmr_match(device_t, cfdata_t, void *); 55 static void gtmr_attach(device_t, device_t, void *); 56 57 static u_int gtmr_get_timecount(struct timecounter *); 58 59 static uint64_t gtmr_read_cntct(struct gtmr_softc *); 60 static uint32_t gtmr_read_ctl(struct gtmr_softc *); 61 static void gtmr_write_ctl(struct gtmr_softc *, uint32_t); 62 static void gtmr_write_tval(struct gtmr_softc *, uint32_t); 63 static void gtmr_write_cval(struct gtmr_softc *, uint64_t); 64 65 static struct gtmr_softc gtmr_sc; 66 67 struct gtmr_percpu { 68 uint32_t pc_delta; 69 }; 70 71 static struct timecounter gtmr_timecounter = { 72 .tc_get_timecount = gtmr_get_timecount, 73 .tc_poll_pps = 0, 74 .tc_counter_mask = ~0u, 75 .tc_frequency = 0, /* set by cpu_initclocks() */ 76 .tc_name = NULL, /* set by attach */ 77 .tc_quality = 500, 78 .tc_priv = >mr_sc, 79 .tc_next = NULL, 80 }; 81 82 CFATTACH_DECL_NEW(armgtmr, 0, gtmr_match, gtmr_attach, NULL, NULL); 83 84 /* ARGSUSED */ 85 static int 86 gtmr_match(device_t parent, cfdata_t cf, void *aux) 87 { 88 struct mpcore_attach_args * const mpcaa = aux; 89 90 if (gtmr_sc.sc_dev != NULL) 91 return 0; 92 93 /* Generic Timer is always implemented in ARMv8-A */ 94 if (!cpu_gtmr_exists_p()) 95 return 0; 96 97 if (strcmp(mpcaa->mpcaa_name, cf->cf_name) != 0) 98 return 0; 99 100 return 1; 101 } 102 103 static void 104 gtmr_attach(device_t parent, device_t self, void *aux) 105 { 106 struct mpcore_attach_args * const mpcaa = aux; 107 struct gtmr_softc *sc = >mr_sc; 108 prop_dictionary_t dict = device_properties(self); 109 prop_dictionary_t pdict = device_properties(device_parent(self)); 110 char freqbuf[sizeof("X.XXX SHz")]; 111 bool flag; 112 113 /* 114 * This runs at a fixed frequency of 1 to 50MHz. 115 */ 116 if (!prop_dictionary_get_uint32(dict, "frequency", &sc->sc_freq)) 117 sc->sc_freq = gtmr_cntfrq_read(); 118 119 if (!prop_dictionary_get_bool(dict, "physical", &sc->sc_physical)) 120 prop_dictionary_get_bool(pdict, "physical", &sc->sc_physical); 121 122 KASSERT(sc->sc_freq != 0); 123 124 humanize_number(freqbuf, sizeof(freqbuf), sc->sc_freq, "Hz", 1000); 125 126 aprint_naive("\n"); 127 aprint_normal(": Generic Timer (%s, %s)\n", freqbuf, 128 sc->sc_physical ? "physical" : "virtual"); 129 130 #if defined(__arm__) 131 if (prop_dictionary_get_bool(dict, "arm,cpu-registers-not-fw-configured", &flag) && flag) { 132 sc->sc_flags |= GTMR_FLAG_CPU_REGISTERS_NOT_FW_CONFIGURED; 133 aprint_debug_dev(self, "CPU registers not initialized by firmware\n"); 134 } 135 #endif 136 137 if (prop_dictionary_get_bool(dict, "sun50i-a64-unstable-timer", &flag) && flag) { 138 sc->sc_flags |= GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER; 139 aprint_debug_dev(self, "enabling Allwinner A64 timer workaround\n"); 140 } 141 142 self->dv_private = sc; 143 sc->sc_dev = self; 144 145 #ifdef DIAGNOSTIC 146 sc->sc_percpu = percpu_alloc(sizeof(struct gtmr_percpu)); 147 #endif 148 149 evcnt_attach_dynamic(&sc->sc_ev_missing_ticks, EVCNT_TYPE_MISC, NULL, 150 device_xname(self), "missing interrupts"); 151 152 if (mpcaa->mpcaa_irq != -1) { 153 sc->sc_global_ih = intr_establish(mpcaa->mpcaa_irq, IPL_CLOCK, 154 IST_LEVEL | IST_MPSAFE, gtmr_intr, NULL); 155 if (sc->sc_global_ih == NULL) 156 panic("%s: unable to register timer interrupt", __func__); 157 aprint_normal_dev(self, "interrupting on irq %d\n", 158 mpcaa->mpcaa_irq); 159 } 160 161 const uint32_t cnt_frq = gtmr_cntfrq_read(); 162 if (cnt_frq == 0) { 163 aprint_verbose_dev(self, "cp15 CNT_FRQ not set\n"); 164 } else if (cnt_frq != sc->sc_freq) { 165 aprint_verbose_dev(self, 166 "cp15 CNT_FRQ (%u) differs from supplied frequency\n", 167 cnt_frq); 168 } 169 170 gtmr_timecounter.tc_name = device_xname(sc->sc_dev); 171 gtmr_timecounter.tc_frequency = sc->sc_freq; 172 gtmr_timecounter.tc_priv = sc; 173 174 tc_init(>mr_timecounter); 175 176 /* Disable the timer until we are ready */ 177 gtmr_write_ctl(sc, 0); 178 } 179 180 static uint64_t 181 gtmr_read_cntct(struct gtmr_softc *sc) 182 { 183 isb(); 184 185 if (ISSET(sc->sc_flags, GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER)) { 186 /* 187 * The Allwinner A64 SoC has an unstable architectural timer. 188 * To workaround this problem, ignore reads where the lower 189 * 10 bits are all 0s or 1s. 190 */ 191 uint64_t val; 192 u_int bits; 193 do { 194 val = sc->sc_physical ? gtmr_cntpct_read() : gtmr_cntvct_read(); 195 bits = val & __BITS(9,0); 196 } while (bits == 0 || bits == __BITS(9,0)); 197 return val; 198 } 199 200 return sc->sc_physical ? gtmr_cntpct_read() : gtmr_cntvct_read(); 201 } 202 203 static uint32_t 204 gtmr_read_ctl(struct gtmr_softc *sc) 205 { 206 isb(); 207 208 if (sc->sc_physical) 209 return gtmr_cntp_ctl_read(); 210 else 211 return gtmr_cntv_ctl_read(); 212 } 213 214 static void 215 gtmr_write_ctl(struct gtmr_softc *sc, uint32_t val) 216 { 217 if (sc->sc_physical) 218 gtmr_cntp_ctl_write(val); 219 else 220 gtmr_cntv_ctl_write(val); 221 222 isb(); 223 } 224 225 static void 226 gtmr_write_tval(struct gtmr_softc *sc, uint32_t val) 227 { 228 if (sc->sc_physical) 229 gtmr_cntp_tval_write(val); 230 else 231 gtmr_cntv_tval_write(val); 232 233 isb(); 234 } 235 236 static void 237 gtmr_write_cval(struct gtmr_softc *sc, uint64_t val) 238 { 239 if (sc->sc_physical) 240 gtmr_cntp_cval_write(val); 241 else 242 gtmr_cntv_cval_write(val); 243 244 isb(); 245 } 246 247 248 void 249 gtmr_init_cpu_clock(struct cpu_info *ci) 250 { 251 struct gtmr_softc * const sc = >mr_sc; 252 uint32_t cntk; 253 uint64_t ctl; 254 255 KASSERT(ci == curcpu()); 256 257 /* XXX hmm... called from cpu_hatch which hasn't lowered ipl yet */ 258 int s = splsched(); 259 260 #if defined(__arm__) 261 if ((sc->sc_flags & GTMR_FLAG_CPU_REGISTERS_NOT_FW_CONFIGURED) != 0) { 262 armreg_cnt_frq_write(sc->sc_freq); 263 } 264 #endif 265 266 /* 267 * Allow the virtual and physical counters to be accessed from 268 * usermode. (PL0) 269 */ 270 cntk = gtmr_cntk_ctl_read(); 271 cntk &= ~(CNTKCTL_PL0PTEN | CNTKCTL_PL0VTEN | CNTKCTL_EVNTEN); 272 if (sc->sc_physical) { 273 cntk |= CNTKCTL_PL0PCTEN; 274 cntk &= ~CNTKCTL_PL0VCTEN; 275 } else { 276 cntk |= CNTKCTL_PL0VCTEN; 277 cntk &= ~CNTKCTL_PL0PCTEN; 278 } 279 gtmr_cntk_ctl_write(cntk); 280 isb(); 281 282 /* 283 * enable timer and stop masking the timer. 284 */ 285 ctl = gtmr_read_ctl(sc); 286 ctl &= ~CNTCTL_IMASK; 287 ctl |= CNTCTL_ENABLE; 288 gtmr_write_ctl(sc, ctl); 289 290 /* 291 * Get now and update the compare timer. 292 */ 293 ci->ci_lastintr = gtmr_read_cntct(sc); 294 gtmr_write_tval(sc, sc->sc_autoinc); 295 296 splx(s); 297 298 KASSERT(gtmr_read_cntct(sc) != 0); 299 } 300 301 void 302 gtmr_cpu_initclocks(void) 303 { 304 struct gtmr_softc * const sc = >mr_sc; 305 306 KASSERT(sc->sc_dev != NULL); 307 KASSERT(sc->sc_freq != 0); 308 309 sc->sc_autoinc = sc->sc_freq / hz; 310 311 gtmr_init_cpu_clock(curcpu()); 312 } 313 314 void 315 gtmr_delay(unsigned int n) 316 { 317 struct gtmr_softc * const sc = >mr_sc; 318 319 KASSERT(sc != NULL); 320 321 uint32_t freq = sc->sc_freq ? sc->sc_freq : gtmr_cntfrq_read(); 322 KASSERT(freq != 0); 323 324 const unsigned int incr_per_us = howmany(freq, 1000000); 325 int64_t ticks = (int64_t)n * incr_per_us; 326 327 uint64_t last = gtmr_read_cntct(sc); 328 329 while (ticks > 0) { 330 uint64_t curr = gtmr_read_cntct(sc); 331 if (curr >= last) 332 ticks -= (curr - last); 333 else 334 ticks -= (UINT64_MAX - curr + last); 335 last = curr; 336 } 337 } 338 339 /* 340 * gtmr_intr: 341 * 342 * Handle the hardclock interrupt. 343 */ 344 int 345 gtmr_intr(void *arg) 346 { 347 struct cpu_info * const ci = curcpu(); 348 struct clockframe * const cf = arg; 349 struct gtmr_softc * const sc = >mr_sc; 350 351 const uint32_t ctl = gtmr_read_ctl(sc); 352 if ((ctl & (CNTCTL_ENABLE|CNTCTL_ISTATUS)) != (CNTCTL_ENABLE|CNTCTL_ISTATUS)) { 353 aprint_debug_dev(ci->ci_dev, "spurious timer interrupt (ctl=%#x)\n", ctl); 354 return 0; 355 } 356 357 const uint64_t now = gtmr_read_cntct(sc); 358 uint64_t delta = now - ci->ci_lastintr; 359 360 #ifdef DIAGNOSTIC 361 struct gtmr_percpu *pc = NULL; 362 if (!ISSET(sc->sc_flags, GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER)) { 363 const uint64_t then = sc->sc_physical ? gtmr_cntp_cval_read() : gtmr_cntv_cval_read(); 364 pc = percpu_getref(sc->sc_percpu); 365 KASSERTMSG(then <= now, "%"PRId64, now - then); 366 KASSERTMSG(then + pc->pc_delta >= ci->ci_lastintr + sc->sc_autoinc, 367 "%"PRId64, then + pc->pc_delta - ci->ci_lastintr - sc->sc_autoinc); 368 } 369 #endif 370 371 if (!ISSET(sc->sc_flags, GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER)) { 372 KASSERTMSG(delta > sc->sc_autoinc / 100, 373 "%s: interrupting too quickly (delta=%"PRIu64") autoinc=%lu", 374 ci->ci_data.cpu_name, delta, sc->sc_autoinc); 375 } 376 377 /* 378 * If we got interrupted too soon (delta < sc->sc_autoinc) 379 * or we missed (or almost missed) a tick 380 * (delta >= 7 * sc->sc_autoinc / 4), don't try to adjust for jitter. 381 */ 382 if (delta >= sc->sc_autoinc && delta <= 7 * sc->sc_autoinc / 4) { 383 delta -= sc->sc_autoinc; 384 } else { 385 delta = 0; 386 } 387 388 isb(); 389 if (ISSET(sc->sc_flags, GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER)) { 390 gtmr_write_cval(sc, now + sc->sc_autoinc - delta); 391 } else { 392 gtmr_write_tval(sc, sc->sc_autoinc - delta); 393 } 394 395 ci->ci_lastintr = now; 396 397 #ifdef DIAGNOSTIC 398 if (!ISSET(sc->sc_flags, GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER)) { 399 KASSERT(delta == (uint32_t) delta); 400 pc->pc_delta = delta; 401 percpu_putref(sc->sc_percpu); 402 } 403 #endif 404 405 hardclock(cf); 406 407 sc->sc_ev_missing_ticks.ev_count += delta / sc->sc_autoinc; 408 409 return 1; 410 } 411 412 void 413 setstatclockrate(int newhz) 414 { 415 } 416 417 static u_int 418 gtmr_get_timecount(struct timecounter *tc) 419 { 420 struct gtmr_softc * const sc = tc->tc_priv; 421 422 return (u_int) gtmr_read_cntct(sc); 423 } 424