1 /* $NetBSD: gicv3_its.c,v 1.32 2021/01/16 21:05:15 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jared McNeill <jmcneill@invisible.ca>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #define _INTR_PRIVATE 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.32 2021/01/16 21:05:15 jmcneill Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/kmem.h> 39 #include <sys/bus.h> 40 #include <sys/cpu.h> 41 #include <sys/bitops.h> 42 43 #include <uvm/uvm.h> 44 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcivar.h> 47 48 #include <arm/pic/picvar.h> 49 #include <arm/cortex/gicv3_its.h> 50 51 /* 52 * ITS translation table sizes 53 */ 54 #define GITS_COMMANDS_SIZE 0x1000 55 #define GITS_COMMANDS_ALIGN 0x10000 56 57 #define GITS_ITT_ALIGN 0x100 58 59 /* 60 * IIDR values used for errata 61 */ 62 #define GITS_IIDR_PID_CAVIUM_THUNDERX 0xa1 63 #define GITS_IIDR_IMP_CAVIUM 0x34c 64 #define GITS_IIDR_CAVIUM_ERRATA_MASK (GITS_IIDR_Implementor|GITS_IIDR_ProductID|GITS_IIDR_Variant) 65 #define GITS_IIDR_CAVIUM_ERRATA_VALUE \ 66 (__SHIFTIN(GITS_IIDR_IMP_CAVIUM, GITS_IIDR_Implementor) | \ 67 __SHIFTIN(GITS_IIDR_PID_CAVIUM_THUNDERX, GITS_IIDR_ProductID) | \ 68 __SHIFTIN(0, GITS_IIDR_Variant)) 69 70 static const char * gits_cache_type[] = { 71 [GITS_Cache_DEVICE_nGnRnE] = "Device-nGnRnE", 72 [GITS_Cache_NORMAL_NC] = "Non-cacheable", 73 [GITS_Cache_NORMAL_RA_WT] = "Cacheable RA WT", 74 [GITS_Cache_NORMAL_RA_WB] = "Cacheable RA WB", 75 [GITS_Cache_NORMAL_WA_WT] = "Cacheable WA WT", 76 [GITS_Cache_NORMAL_WA_WB] = "Cacheable WA WB", 77 [GITS_Cache_NORMAL_RA_WA_WT] = "Cacheable RA WA WT", 78 [GITS_Cache_NORMAL_RA_WA_WB] = "Cacheable RA WA WB", 79 }; 80 81 static const char * gits_share_type[] = { 82 [GITS_Shareability_NS] = "Non-shareable", 83 [GITS_Shareability_IS] = "Inner shareable", 84 [GITS_Shareability_OS] = "Outer shareable", 85 [3] = "(Reserved)", 86 }; 87 88 static inline uint32_t 89 gits_read_4(struct gicv3_its *its, bus_size_t reg) 90 { 91 return bus_space_read_4(its->its_bst, its->its_bsh, reg); 92 } 93 94 static inline void 95 gits_write_4(struct gicv3_its *its, bus_size_t reg, uint32_t val) 96 { 97 bus_space_write_4(its->its_bst, its->its_bsh, reg, val); 98 } 99 100 static inline uint64_t 101 gits_read_8(struct gicv3_its *its, bus_size_t reg) 102 { 103 return bus_space_read_8(its->its_bst, its->its_bsh, reg); 104 } 105 106 static inline void 107 gits_write_8(struct gicv3_its *its, bus_size_t reg, uint64_t val) 108 { 109 bus_space_write_8(its->its_bst, its->its_bsh, reg, val); 110 } 111 112 static inline void 113 gits_command(struct gicv3_its *its, const struct gicv3_its_command *cmd) 114 { 115 uint64_t cwriter; 116 u_int woff; 117 118 cwriter = gits_read_8(its, GITS_CWRITER); 119 woff = cwriter & GITS_CWRITER_Offset; 120 121 uint64_t *dw = (uint64_t *)(its->its_cmd.base + woff); 122 for (int i = 0; i < __arraycount(cmd->dw); i++) 123 dw[i] = htole64(cmd->dw[i]); 124 bus_dmamap_sync(its->its_dmat, its->its_cmd.map, woff, sizeof(cmd->dw), BUS_DMASYNC_PREWRITE); 125 126 woff += sizeof(cmd->dw); 127 if (woff == its->its_cmd.len) 128 woff = 0; 129 130 gits_write_8(its, GITS_CWRITER, woff); 131 } 132 133 static inline void 134 gits_command_mapc(struct gicv3_its *its, uint16_t icid, uint64_t rdbase, bool v) 135 { 136 struct gicv3_its_command cmd; 137 138 KASSERT((rdbase & 0xffff) == 0); 139 140 /* 141 * Map a collection table entry (ICID) to the target redistributor (RDbase). 142 */ 143 memset(&cmd, 0, sizeof(cmd)); 144 cmd.dw[0] = GITS_CMD_MAPC; 145 cmd.dw[2] = icid; 146 if (v) { 147 cmd.dw[2] |= rdbase; 148 cmd.dw[2] |= __BIT(63); 149 } 150 151 gits_command(its, &cmd); 152 } 153 154 static inline void 155 gits_command_mapd(struct gicv3_its *its, uint32_t deviceid, uint64_t itt_addr, u_int size, bool v) 156 { 157 struct gicv3_its_command cmd; 158 159 KASSERT((itt_addr & 0xff) == 0); 160 161 /* 162 * Map a device table entry (DeviceID) to its associated ITT (ITT_addr). 163 */ 164 memset(&cmd, 0, sizeof(cmd)); 165 cmd.dw[0] = GITS_CMD_MAPD | ((uint64_t)deviceid << 32); 166 cmd.dw[1] = size; 167 if (v) { 168 cmd.dw[2] = itt_addr | __BIT(63); 169 } 170 171 gits_command(its, &cmd); 172 } 173 174 static inline void 175 gits_command_mapti(struct gicv3_its *its, uint32_t deviceid, uint32_t eventid, uint32_t pintid, uint16_t icid) 176 { 177 struct gicv3_its_command cmd; 178 179 /* 180 * Map the event defined by EventID and DeviceID to its associated ITE, defined by ICID and pINTID 181 * in the ITT associated with DeviceID. 182 */ 183 memset(&cmd, 0, sizeof(cmd)); 184 cmd.dw[0] = GITS_CMD_MAPTI | ((uint64_t)deviceid << 32); 185 cmd.dw[1] = eventid | ((uint64_t)pintid << 32); 186 cmd.dw[2] = icid; 187 188 gits_command(its, &cmd); 189 } 190 191 static inline void 192 gits_command_movi(struct gicv3_its *its, uint32_t deviceid, uint32_t eventid, uint16_t icid) 193 { 194 struct gicv3_its_command cmd; 195 196 /* 197 * Update the ICID field in the ITT entry for the event defined by DeviceID and 198 * EventID. 199 */ 200 memset(&cmd, 0, sizeof(cmd)); 201 cmd.dw[0] = GITS_CMD_MOVI | ((uint64_t)deviceid << 32); 202 cmd.dw[1] = eventid; 203 cmd.dw[2] = icid; 204 205 gits_command(its, &cmd); 206 } 207 208 static inline void 209 gits_command_inv(struct gicv3_its *its, uint32_t deviceid, uint32_t eventid) 210 { 211 struct gicv3_its_command cmd; 212 213 /* 214 * Ensure any caching in the redistributors associated with the specified 215 * EventID is consistent with the LPI configuration tables. 216 */ 217 memset(&cmd, 0, sizeof(cmd)); 218 cmd.dw[0] = GITS_CMD_INV | ((uint64_t)deviceid << 32); 219 cmd.dw[1] = eventid; 220 221 gits_command(its, &cmd); 222 } 223 224 static inline void 225 gits_command_invall(struct gicv3_its *its, uint16_t icid) 226 { 227 struct gicv3_its_command cmd; 228 229 /* 230 * Ensure any caching associated with this ICID is consistent with LPI 231 * configuration tables for all redistributors. 232 */ 233 memset(&cmd, 0, sizeof(cmd)); 234 cmd.dw[0] = GITS_CMD_INVALL; 235 cmd.dw[2] = icid; 236 237 gits_command(its, &cmd); 238 } 239 240 static inline void 241 gits_command_sync(struct gicv3_its *its, uint64_t rdbase) 242 { 243 struct gicv3_its_command cmd; 244 245 KASSERT((rdbase & 0xffff) == 0); 246 247 /* 248 * Ensure all outstanding ITS operations associated with physical interrupts 249 * for the specified redistributor (RDbase) are globally observed before 250 * further ITS commands are executed. 251 */ 252 memset(&cmd, 0, sizeof(cmd)); 253 cmd.dw[0] = GITS_CMD_SYNC; 254 cmd.dw[2] = rdbase; 255 256 gits_command(its, &cmd); 257 } 258 259 static inline int 260 gits_wait(struct gicv3_its *its) 261 { 262 u_int woff, roff; 263 int retry = 100000; 264 265 /* 266 * The ITS command queue is empty when CWRITER and CREADR specify the 267 * same base address offset value. 268 */ 269 for (retry = 1000; retry > 0; retry--) { 270 woff = gits_read_8(its, GITS_CWRITER) & GITS_CWRITER_Offset; 271 roff = gits_read_8(its, GITS_CREADR) & GITS_CREADR_Offset; 272 if (woff == roff) 273 break; 274 delay(100); 275 } 276 if (retry == 0) { 277 device_printf(its->its_gic->sc_dev, "ITS command queue timeout\n"); 278 return ETIMEDOUT; 279 } 280 281 return 0; 282 } 283 284 static int 285 gicv3_its_msi_alloc_lpi(struct gicv3_its *its, 286 const struct pci_attach_args *pa) 287 { 288 struct pci_attach_args *new_pa; 289 vmem_addr_t n; 290 291 KASSERT(its->its_gic->sc_lpi_pool != NULL); 292 293 if (vmem_alloc(its->its_gic->sc_lpi_pool, 1, VM_INSTANTFIT|VM_SLEEP, &n) != 0) 294 return -1; 295 296 KASSERT(its->its_pa[n] == NULL); 297 298 new_pa = kmem_alloc(sizeof(*new_pa), KM_SLEEP); 299 memcpy(new_pa, pa, sizeof(*new_pa)); 300 its->its_pa[n] = new_pa; 301 return n + its->its_pic->pic_irqbase; 302 } 303 304 static void 305 gicv3_its_msi_free_lpi(struct gicv3_its *its, int lpi) 306 { 307 struct pci_attach_args *pa; 308 309 KASSERT(its->its_gic->sc_lpi_pool != NULL); 310 KASSERT(lpi >= its->its_pic->pic_irqbase); 311 312 pa = its->its_pa[lpi - its->its_pic->pic_irqbase]; 313 its->its_pa[lpi - its->its_pic->pic_irqbase] = NULL; 314 kmem_free(pa, sizeof(*pa)); 315 316 vmem_free(its->its_gic->sc_lpi_pool, lpi - its->its_pic->pic_irqbase, 1); 317 } 318 319 static uint32_t 320 gicv3_its_devid(pci_chipset_tag_t pc, pcitag_t tag) 321 { 322 uint32_t devid; 323 int b, d, f; 324 325 pci_decompose_tag(pc, tag, &b, &d, &f); 326 327 devid = (b << 8) | (d << 3) | f; 328 329 return pci_get_devid(pc, devid); 330 } 331 332 static int 333 gicv3_its_device_map(struct gicv3_its *its, uint32_t devid, u_int count) 334 { 335 struct gicv3_its_device *dev; 336 u_int vectors; 337 338 vectors = MAX(2, count); 339 while (!powerof2(vectors)) 340 vectors++; 341 342 const uint64_t typer = gits_read_8(its, GITS_TYPER); 343 const u_int itt_entry_size = __SHIFTOUT(typer, GITS_TYPER_ITT_entry_size) + 1; 344 const u_int itt_size = roundup(vectors * itt_entry_size, GITS_ITT_ALIGN); 345 346 LIST_FOREACH(dev, &its->its_devices, dev_list) 347 if (dev->dev_id == devid) { 348 return itt_size <= dev->dev_size ? 0 : EEXIST; 349 } 350 351 dev = kmem_alloc(sizeof(*dev), KM_SLEEP); 352 dev->dev_id = devid; 353 dev->dev_size = itt_size; 354 gicv3_dma_alloc(its->its_gic, &dev->dev_itt, itt_size, GITS_ITT_ALIGN); 355 LIST_INSERT_HEAD(&its->its_devices, dev, dev_list); 356 357 /* 358 * Map the device to the ITT 359 */ 360 const u_int id_bits = __SHIFTOUT(typer, GITS_TYPER_ID_bits) + 1; 361 gits_command_mapd(its, devid, dev->dev_itt.segs[0].ds_addr, id_bits - 1, true); 362 gits_wait(its); 363 364 return 0; 365 } 366 367 static void 368 gicv3_its_msi_enable(struct gicv3_its *its, int lpi, int count) 369 { 370 const struct pci_attach_args *pa = its->its_pa[lpi - its->its_pic->pic_irqbase]; 371 pci_chipset_tag_t pc = pa->pa_pc; 372 pcitag_t tag = pa->pa_tag; 373 pcireg_t ctl; 374 int off; 375 376 if (!pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL)) 377 panic("gicv3_its_msi_enable: device is not MSI-capable"); 378 379 ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 380 ctl &= ~PCI_MSI_CTL_MME_MASK; 381 ctl |= __SHIFTIN(ilog2(count), PCI_MSI_CTL_MME_MASK); 382 pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl); 383 384 const uint64_t addr = its->its_base + GITS_TRANSLATER; 385 ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 386 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 387 pci_conf_write(pc, tag, off + PCI_MSI_MADDR64_LO, 388 addr & 0xffffffff); 389 pci_conf_write(pc, tag, off + PCI_MSI_MADDR64_HI, 390 (addr >> 32) & 0xffffffff); 391 pci_conf_write(pc, tag, off + PCI_MSI_MDATA64, 392 lpi - its->its_pic->pic_irqbase); 393 } else { 394 pci_conf_write(pc, tag, off + PCI_MSI_MADDR, 395 addr & 0xffffffff); 396 pci_conf_write(pc, tag, off + PCI_MSI_MDATA, 397 lpi - its->its_pic->pic_irqbase); 398 } 399 ctl |= PCI_MSI_CTL_MSI_ENABLE; 400 pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl); 401 } 402 403 static void 404 gicv3_its_msi_disable(struct gicv3_its *its, int lpi) 405 { 406 const struct pci_attach_args *pa = its->its_pa[lpi - its->its_pic->pic_irqbase]; 407 pci_chipset_tag_t pc = pa->pa_pc; 408 pcitag_t tag = pa->pa_tag; 409 pcireg_t ctl; 410 int off; 411 412 if (!pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL)) 413 panic("gicv3_its_msi_enable: device is not MSI-capable"); 414 415 ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 416 ctl &= ~PCI_MSI_CTL_MSI_ENABLE; 417 pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl); 418 } 419 420 static void 421 gicv3_its_msix_enable(struct gicv3_its *its, int lpi, int msix_vec, 422 bus_space_tag_t bst, bus_space_handle_t bsh) 423 { 424 const struct pci_attach_args *pa = its->its_pa[lpi - its->its_pic->pic_irqbase]; 425 pci_chipset_tag_t pc = pa->pa_pc; 426 pcitag_t tag = pa->pa_tag; 427 pcireg_t ctl; 428 uint32_t val; 429 int off; 430 431 if (!pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL)) 432 panic("gicv3_its_msix_enable: device is not MSI-X-capable"); 433 434 const uint64_t addr = its->its_base + GITS_TRANSLATER; 435 const uint64_t entry_base = PCI_MSIX_TABLE_ENTRY_SIZE * msix_vec; 436 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_LO, (uint32_t)addr); 437 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_HI, (uint32_t)(addr >> 32)); 438 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_DATA, lpi - its->its_pic->pic_irqbase); 439 val = bus_space_read_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL); 440 val &= ~PCI_MSIX_VECTCTL_MASK; 441 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, val); 442 443 ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL); 444 ctl |= PCI_MSIX_CTL_ENABLE; 445 pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl); 446 } 447 448 static void 449 gicv3_its_msix_disable(struct gicv3_its *its, int lpi) 450 { 451 const struct pci_attach_args *pa = its->its_pa[lpi - its->its_pic->pic_irqbase]; 452 pci_chipset_tag_t pc = pa->pa_pc; 453 pcitag_t tag = pa->pa_tag; 454 pcireg_t ctl; 455 int off; 456 457 if (!pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL)) 458 panic("gicv3_its_msix_disable: device is not MSI-X-capable"); 459 460 ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL); 461 ctl &= ~PCI_MSIX_CTL_ENABLE; 462 pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl); 463 } 464 465 static pci_intr_handle_t * 466 gicv3_its_msi_alloc(struct arm_pci_msi *msi, int *count, 467 const struct pci_attach_args *pa, bool exact) 468 { 469 struct gicv3_its * const its = msi->msi_priv; 470 struct cpu_info * const ci = cpu_lookup(0); 471 pci_intr_handle_t *vectors; 472 int n, off; 473 474 if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSI, &off, NULL)) 475 return NULL; 476 477 const uint64_t typer = gits_read_8(its, GITS_TYPER); 478 const u_int id_bits = __SHIFTOUT(typer, GITS_TYPER_ID_bits) + 1; 479 if (*count == 0 || *count > (1 << id_bits)) 480 return NULL; 481 482 const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag); 483 484 if (gicv3_its_device_map(its, devid, *count) != 0) 485 return NULL; 486 487 vectors = kmem_alloc(sizeof(*vectors) * *count, KM_SLEEP); 488 for (n = 0; n < *count; n++) { 489 const int lpi = gicv3_its_msi_alloc_lpi(its, pa); 490 vectors[n] = ARM_PCI_INTR_MSI | 491 __SHIFTIN(lpi, ARM_PCI_INTR_IRQ) | 492 __SHIFTIN(n, ARM_PCI_INTR_MSI_VEC) | 493 __SHIFTIN(msi->msi_id, ARM_PCI_INTR_FRAME); 494 495 if (n == 0) 496 gicv3_its_msi_enable(its, lpi, *count); 497 498 /* 499 * Record target PE 500 */ 501 its->its_targets[lpi - its->its_pic->pic_irqbase] = ci; 502 503 /* 504 * Map event 505 */ 506 gits_command_mapti(its, devid, lpi - its->its_pic->pic_irqbase, lpi, cpu_index(ci)); 507 gits_command_sync(its, its->its_rdbase[cpu_index(ci)]); 508 } 509 gits_wait(its); 510 511 return vectors; 512 } 513 514 static pci_intr_handle_t * 515 gicv3_its_msix_alloc(struct arm_pci_msi *msi, u_int *table_indexes, int *count, 516 const struct pci_attach_args *pa, bool exact) 517 { 518 struct gicv3_its * const its = msi->msi_priv; 519 struct cpu_info *ci = cpu_lookup(0); 520 pci_intr_handle_t *vectors; 521 bus_space_tag_t bst; 522 bus_space_handle_t bsh; 523 bus_size_t bsz; 524 uint32_t table_offset, table_size; 525 int n, off, bar, error; 526 pcireg_t tbl; 527 528 if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSIX, &off, NULL)) 529 return NULL; 530 531 const uint64_t typer = gits_read_8(its, GITS_TYPER); 532 const u_int id_bits = __SHIFTOUT(typer, GITS_TYPER_ID_bits) + 1; 533 if (*count == 0 || *count > (1 << id_bits)) 534 return NULL; 535 536 tbl = pci_conf_read(pa->pa_pc, pa->pa_tag, off + PCI_MSIX_TBLOFFSET); 537 bar = PCI_BAR0 + (4 * (tbl & PCI_MSIX_TBLBIR_MASK)); 538 table_offset = tbl & PCI_MSIX_TBLOFFSET_MASK; 539 table_size = pci_msix_count(pa->pa_pc, pa->pa_tag) * PCI_MSIX_TABLE_ENTRY_SIZE; 540 if (table_size == 0) 541 return NULL; 542 543 error = pci_mapreg_submap(pa, bar, pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar), 544 BUS_SPACE_MAP_LINEAR, roundup(table_size, PAGE_SIZE), table_offset, 545 &bst, &bsh, NULL, &bsz); 546 if (error) 547 return NULL; 548 549 const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag); 550 551 if (gicv3_its_device_map(its, devid, *count) != 0) { 552 bus_space_unmap(bst, bsh, bsz); 553 return NULL; 554 } 555 556 vectors = kmem_alloc(sizeof(*vectors) * *count, KM_SLEEP); 557 for (n = 0; n < *count; n++) { 558 const int lpi = gicv3_its_msi_alloc_lpi(its, pa); 559 const int msix_vec = table_indexes ? table_indexes[n] : n; 560 vectors[msix_vec] = ARM_PCI_INTR_MSIX | 561 __SHIFTIN(lpi, ARM_PCI_INTR_IRQ) | 562 __SHIFTIN(msix_vec, ARM_PCI_INTR_MSI_VEC) | 563 __SHIFTIN(msi->msi_id, ARM_PCI_INTR_FRAME); 564 565 gicv3_its_msix_enable(its, lpi, msix_vec, bst, bsh); 566 567 /* 568 * Record target PE 569 */ 570 its->its_targets[lpi - its->its_pic->pic_irqbase] = ci; 571 572 /* 573 * Map event 574 */ 575 gits_command_mapti(its, devid, lpi - its->its_pic->pic_irqbase, lpi, cpu_index(ci)); 576 gits_command_sync(its, its->its_rdbase[cpu_index(ci)]); 577 } 578 gits_wait(its); 579 580 bus_space_unmap(bst, bsh, bsz); 581 582 return vectors; 583 } 584 585 static void * 586 gicv3_its_msi_intr_establish(struct arm_pci_msi *msi, 587 pci_intr_handle_t ih, int ipl, int (*func)(void *), void *arg, const char *xname) 588 { 589 struct gicv3_its * const its = msi->msi_priv; 590 const struct pci_attach_args *pa; 591 void *intrh; 592 593 const int lpi = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ); 594 const int mpsafe = (ih & ARM_PCI_INTR_MPSAFE) ? IST_MPSAFE : 0; 595 596 intrh = pic_establish_intr(its->its_pic, lpi - its->its_pic->pic_irqbase, ipl, 597 IST_EDGE | mpsafe, func, arg, xname); 598 if (intrh == NULL) 599 return NULL; 600 601 /* Invalidate LPI configuration tables */ 602 pa = its->its_pa[lpi - its->its_pic->pic_irqbase]; 603 KASSERT(pa != NULL); 604 const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag); 605 gits_command_inv(its, devid, lpi - its->its_pic->pic_irqbase); 606 607 return intrh; 608 } 609 610 static void 611 gicv3_its_msi_intr_release(struct arm_pci_msi *msi, pci_intr_handle_t *pih, 612 int count) 613 { 614 struct gicv3_its * const its = msi->msi_priv; 615 int n; 616 617 for (n = 0; n < count; n++) { 618 const int lpi = __SHIFTOUT(pih[n], ARM_PCI_INTR_IRQ); 619 KASSERT(lpi >= its->its_pic->pic_irqbase); 620 if (pih[n] & ARM_PCI_INTR_MSIX) 621 gicv3_its_msix_disable(its, lpi); 622 if (pih[n] & ARM_PCI_INTR_MSI) 623 gicv3_its_msi_disable(its, lpi); 624 gicv3_its_msi_free_lpi(its, lpi); 625 its->its_targets[lpi - its->its_pic->pic_irqbase] = NULL; 626 struct intrsource * const is = 627 its->its_pic->pic_sources[lpi - its->its_pic->pic_irqbase]; 628 if (is != NULL) 629 pic_disestablish_source(is); 630 } 631 } 632 633 static void 634 gicv3_its_command_init(struct gicv3_softc *sc, struct gicv3_its *its) 635 { 636 uint64_t cbaser; 637 638 gicv3_dma_alloc(sc, &its->its_cmd, GITS_COMMANDS_SIZE, GITS_COMMANDS_ALIGN); 639 640 cbaser = its->its_cmd.segs[0].ds_addr; 641 cbaser |= __SHIFTIN(GITS_Cache_NORMAL_NC, GITS_CBASER_InnerCache); 642 cbaser |= __SHIFTIN(GITS_Shareability_NS, GITS_CBASER_Shareability); 643 cbaser |= __SHIFTIN((its->its_cmd.len / 4096) - 1, GITS_CBASER_Size); 644 cbaser |= GITS_CBASER_Valid; 645 646 gits_write_8(its, GITS_CBASER, cbaser); 647 gits_write_8(its, GITS_CWRITER, 0); 648 } 649 650 static void 651 gicv3_its_table_params(struct gicv3_softc *sc, struct gicv3_its *its, 652 u_int *devbits, u_int *innercache, u_int *share) 653 { 654 655 const uint64_t typer = gits_read_8(its, GITS_TYPER); 656 const uint32_t iidr = gits_read_4(its, GITS_IIDR); 657 658 /* Default values */ 659 *devbits = __SHIFTOUT(typer, GITS_TYPER_Devbits) + 1; 660 *innercache = GITS_Cache_NORMAL_WA_WB; 661 *share = GITS_Shareability_IS; 662 663 /* Cavium ThunderX errata */ 664 if ((iidr & GITS_IIDR_CAVIUM_ERRATA_MASK) == GITS_IIDR_CAVIUM_ERRATA_VALUE) { 665 *devbits = 20; /* 8Mb */ 666 *innercache = GITS_Cache_DEVICE_nGnRnE; 667 aprint_normal_dev(sc->sc_dev, "Cavium ThunderX errata detected\n"); 668 } 669 } 670 671 static void 672 gicv3_its_table_init(struct gicv3_softc *sc, struct gicv3_its *its) 673 { 674 u_int table_size, page_size, table_align; 675 u_int devbits, innercache, share; 676 const char *table_type; 677 uint64_t baser; 678 int tab; 679 680 gicv3_its_table_params(sc, its, &devbits, &innercache, &share); 681 682 for (tab = 0; tab < 8; tab++) { 683 baser = gits_read_8(its, GITS_BASERn(tab)); 684 685 const u_int entry_size = __SHIFTOUT(baser, GITS_BASER_Entry_Size) + 1; 686 687 switch (__SHIFTOUT(baser, GITS_BASER_Page_Size)) { 688 case GITS_Page_Size_4KB: 689 page_size = 4096; 690 table_align = 4096; 691 break; 692 case GITS_Page_Size_16KB: 693 page_size = 16384; 694 table_align = 4096; 695 break; 696 case GITS_Page_Size_64KB: 697 default: 698 page_size = 65536; 699 table_align = 65536; 700 break; 701 } 702 703 switch (__SHIFTOUT(baser, GITS_BASER_Type)) { 704 case GITS_Type_Devices: 705 /* 706 * Table size scales with the width of the DeviceID. 707 */ 708 table_size = roundup(entry_size * (1 << devbits), page_size); 709 table_type = "Devices"; 710 break; 711 case GITS_Type_InterruptCollections: 712 /* 713 * Allocate space for one interrupt collection per CPU. 714 */ 715 table_size = roundup(entry_size * ncpu, page_size); 716 table_type = "Collections"; 717 break; 718 default: 719 table_size = 0; 720 break; 721 } 722 723 if (table_size == 0) 724 continue; 725 726 gicv3_dma_alloc(sc, &its->its_tab[tab], table_size, table_align); 727 728 baser &= ~GITS_BASER_Size; 729 baser |= __SHIFTIN(table_size / page_size - 1, GITS_BASER_Size); 730 baser &= ~GITS_BASER_Physical_Address; 731 baser |= its->its_tab[tab].segs[0].ds_addr; 732 baser &= ~GITS_BASER_InnerCache; 733 baser |= __SHIFTIN(innercache, GITS_BASER_InnerCache); 734 baser &= ~GITS_BASER_Shareability; 735 baser |= __SHIFTIN(share, GITS_BASER_Shareability); 736 baser |= GITS_BASER_Valid; 737 738 gits_write_8(its, GITS_BASERn(tab), baser); 739 740 baser = gits_read_8(its, GITS_BASERn(tab)); 741 if (__SHIFTOUT(baser, GITS_BASER_Shareability) == GITS_Shareability_NS) { 742 baser &= ~GITS_BASER_InnerCache; 743 baser |= __SHIFTIN(GITS_Cache_NORMAL_NC, GITS_BASER_InnerCache); 744 745 gits_write_8(its, GITS_BASERn(tab), baser); 746 } 747 748 baser = gits_read_8(its, GITS_BASERn(tab)); 749 aprint_normal_dev(sc->sc_dev, "ITS [#%d] %s table @ %#lx/%#x, %s, %s\n", 750 tab, table_type, its->its_tab[tab].segs[0].ds_addr, table_size, 751 gits_cache_type[__SHIFTOUT(baser, GITS_BASER_InnerCache)], 752 gits_share_type[__SHIFTOUT(baser, GITS_BASER_Shareability)]); 753 } 754 } 755 756 static void 757 gicv3_its_enable(struct gicv3_softc *sc, struct gicv3_its *its) 758 { 759 uint32_t ctlr; 760 761 ctlr = gits_read_4(its, GITS_CTLR); 762 ctlr |= GITS_CTLR_Enabled; 763 gits_write_4(its, GITS_CTLR, ctlr); 764 } 765 766 static void 767 gicv3_its_cpu_init(void *priv, struct cpu_info *ci) 768 { 769 struct gicv3_its * const its = priv; 770 struct gicv3_softc * const sc = its->its_gic; 771 const struct pci_attach_args *pa; 772 uint64_t rdbase; 773 size_t irq; 774 775 const uint64_t typer = bus_space_read_8(sc->sc_bst, its->its_bsh, GITS_TYPER); 776 if (typer & GITS_TYPER_PTA) { 777 void *va = bus_space_vaddr(sc->sc_bst, sc->sc_bsh_r[ci->ci_gic_redist]); 778 rdbase = vtophys((vaddr_t)va); 779 } else { 780 rdbase = (uint64_t)sc->sc_processor_id[cpu_index(ci)] << 16; 781 } 782 its->its_rdbase[cpu_index(ci)] = rdbase; 783 784 /* 785 * Map collection ID of this CPU's index to this CPU's redistributor. 786 */ 787 gits_command_mapc(its, cpu_index(ci), rdbase, true); 788 gits_command_invall(its, cpu_index(ci)); 789 gits_wait(its); 790 791 /* 792 * Update routing for LPIs targetting this CPU 793 */ 794 for (irq = 0; irq < its->its_pic->pic_maxsources; irq++) { 795 if (its->its_targets[irq] != ci) 796 continue; 797 pa = its->its_pa[irq]; 798 KASSERT(pa != NULL); 799 800 const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag); 801 gits_command_movi(its, devid, irq, cpu_index(ci)); 802 gits_command_sync(its, its->its_rdbase[cpu_index(ci)]); 803 } 804 805 its->its_cpuonline[cpu_index(ci)] = true; 806 } 807 808 static void 809 gicv3_its_get_affinity(void *priv, size_t irq, kcpuset_t *affinity) 810 { 811 struct gicv3_its * const its = priv; 812 struct cpu_info *ci; 813 814 ci = its->its_targets[irq]; 815 if (ci) 816 kcpuset_set(affinity, cpu_index(ci)); 817 } 818 819 static int 820 gicv3_its_set_affinity(void *priv, size_t irq, const kcpuset_t *affinity) 821 { 822 struct gicv3_its * const its = priv; 823 const struct pci_attach_args *pa; 824 struct cpu_info *ci; 825 826 const int set = kcpuset_countset(affinity); 827 if (set != 1) 828 return EINVAL; 829 830 pa = its->its_pa[irq]; 831 if (pa == NULL) 832 return EPASSTHROUGH; 833 834 ci = cpu_lookup(kcpuset_ffs(affinity) - 1); 835 its->its_targets[irq] = ci; 836 837 if (its->its_cpuonline[cpu_index(ci)] == true) { 838 const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag); 839 gits_command_movi(its, devid, irq, cpu_index(ci)); 840 gits_command_sync(its, its->its_rdbase[cpu_index(ci)]); 841 } 842 843 return 0; 844 } 845 846 int 847 gicv3_its_init(struct gicv3_softc *sc, bus_space_handle_t bsh, 848 uint64_t its_base, uint32_t its_id) 849 { 850 struct gicv3_its *its; 851 struct arm_pci_msi *msi; 852 853 const uint64_t typer = bus_space_read_8(sc->sc_bst, bsh, GITS_TYPER); 854 if ((typer & GITS_TYPER_Physical) == 0) 855 return ENXIO; 856 857 its = kmem_zalloc(sizeof(*its), KM_SLEEP); 858 its->its_id = its_id; 859 its->its_bst = sc->sc_bst; 860 its->its_bsh = bsh; 861 its->its_dmat = sc->sc_dmat; 862 its->its_base = its_base; 863 its->its_pic = &sc->sc_lpi; 864 snprintf(its->its_pic->pic_name, sizeof(its->its_pic->pic_name), "gicv3-its"); 865 KASSERT(its->its_pic->pic_maxsources > 0); 866 its->its_pa = kmem_zalloc(sizeof(struct pci_attach_args *) * its->its_pic->pic_maxsources, KM_SLEEP); 867 its->its_targets = kmem_zalloc(sizeof(struct cpu_info *) * its->its_pic->pic_maxsources, KM_SLEEP); 868 its->its_gic = sc; 869 its->its_rdbase = kmem_zalloc(sizeof(*its->its_rdbase) * ncpu, KM_SLEEP); 870 its->its_cpuonline = kmem_zalloc(sizeof(*its->its_cpuonline) * ncpu, KM_SLEEP); 871 its->its_cb.cpu_init = gicv3_its_cpu_init; 872 its->its_cb.get_affinity = gicv3_its_get_affinity; 873 its->its_cb.set_affinity = gicv3_its_set_affinity; 874 its->its_cb.priv = its; 875 LIST_INIT(&its->its_devices); 876 LIST_INSERT_HEAD(&sc->sc_lpi_callbacks, &its->its_cb, list); 877 878 gicv3_its_command_init(sc, its); 879 gicv3_its_table_init(sc, its); 880 881 gicv3_its_enable(sc, its); 882 883 gicv3_its_cpu_init(its, curcpu()); 884 885 msi = &its->its_msi; 886 msi->msi_id = its_id; 887 msi->msi_dev = sc->sc_dev; 888 msi->msi_priv = its; 889 msi->msi_alloc = gicv3_its_msi_alloc; 890 msi->msix_alloc = gicv3_its_msix_alloc; 891 msi->msi_intr_establish = gicv3_its_msi_intr_establish; 892 msi->msi_intr_release = gicv3_its_msi_intr_release; 893 894 return arm_pci_msi_add(msi); 895 } 896