1 /* $NetBSD: gicv3.c,v 1.32 2020/11/01 14:30:12 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_multiprocessor.h" 30 31 #define _INTR_PRIVATE 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.32 2020/11/01 14:30:12 jmcneill Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/kernel.h> 38 #include <sys/bus.h> 39 #include <sys/device.h> 40 #include <sys/intr.h> 41 #include <sys/systm.h> 42 #include <sys/cpu.h> 43 #include <sys/vmem.h> 44 #include <sys/atomic.h> 45 46 #include <machine/cpufunc.h> 47 48 #include <arm/locore.h> 49 #include <arm/armreg.h> 50 51 #include <arm/cortex/gicv3.h> 52 #include <arm/cortex/gic_reg.h> 53 54 #define PICTOSOFTC(pic) \ 55 ((void *)((uintptr_t)(pic) - offsetof(struct gicv3_softc, sc_pic))) 56 #define LPITOSOFTC(lpi) \ 57 ((void *)((uintptr_t)(lpi) - offsetof(struct gicv3_softc, sc_lpi))) 58 59 #define IPL_TO_PRIORITY(sc, ipl) (((0xff - (ipl)) << (sc)->sc_priority_shift) & 0xff) 60 #define IPL_TO_PMR(sc, ipl) (((0xff - (ipl)) << (sc)->sc_pmr_shift) & 0xff) 61 #define IPL_TO_LPIPRIO(sc, ipl) (((0xff - (ipl)) << 4) & 0xff) 62 63 static struct gicv3_softc *gicv3_softc; 64 65 static inline uint32_t 66 gicd_read_4(struct gicv3_softc *sc, bus_size_t reg) 67 { 68 return bus_space_read_4(sc->sc_bst, sc->sc_bsh_d, reg); 69 } 70 71 static inline void 72 gicd_write_4(struct gicv3_softc *sc, bus_size_t reg, uint32_t val) 73 { 74 bus_space_write_4(sc->sc_bst, sc->sc_bsh_d, reg, val); 75 } 76 77 static inline uint64_t 78 gicd_read_8(struct gicv3_softc *sc, bus_size_t reg) 79 { 80 return bus_space_read_8(sc->sc_bst, sc->sc_bsh_d, reg); 81 } 82 83 static inline void 84 gicd_write_8(struct gicv3_softc *sc, bus_size_t reg, uint64_t val) 85 { 86 bus_space_write_8(sc->sc_bst, sc->sc_bsh_d, reg, val); 87 } 88 89 static inline uint32_t 90 gicr_read_4(struct gicv3_softc *sc, u_int index, bus_size_t reg) 91 { 92 KASSERT(index < sc->sc_bsh_r_count); 93 return bus_space_read_4(sc->sc_bst, sc->sc_bsh_r[index], reg); 94 } 95 96 static inline void 97 gicr_write_4(struct gicv3_softc *sc, u_int index, bus_size_t reg, uint32_t val) 98 { 99 KASSERT(index < sc->sc_bsh_r_count); 100 bus_space_write_4(sc->sc_bst, sc->sc_bsh_r[index], reg, val); 101 } 102 103 static inline uint64_t 104 gicr_read_8(struct gicv3_softc *sc, u_int index, bus_size_t reg) 105 { 106 KASSERT(index < sc->sc_bsh_r_count); 107 return bus_space_read_8(sc->sc_bst, sc->sc_bsh_r[index], reg); 108 } 109 110 static inline void 111 gicr_write_8(struct gicv3_softc *sc, u_int index, bus_size_t reg, uint64_t val) 112 { 113 KASSERT(index < sc->sc_bsh_r_count); 114 bus_space_write_8(sc->sc_bst, sc->sc_bsh_r[index], reg, val); 115 } 116 117 static void 118 gicv3_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t mask) 119 { 120 struct gicv3_softc * const sc = PICTOSOFTC(pic); 121 struct cpu_info * const ci = curcpu(); 122 const u_int group = irqbase / 32; 123 124 if (group == 0) { 125 atomic_or_32(&sc->sc_enabled_sgippi, mask); 126 gicr_write_4(sc, ci->ci_gic_redist, GICR_ISENABLER0, mask); 127 while (gicr_read_4(sc, ci->ci_gic_redist, GICR_CTLR) & GICR_CTLR_RWP) 128 ; 129 } else { 130 gicd_write_4(sc, GICD_ISENABLERn(group), mask); 131 while (gicd_read_4(sc, GICD_CTRL) & GICD_CTRL_RWP) 132 ; 133 } 134 } 135 136 static void 137 gicv3_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t mask) 138 { 139 struct gicv3_softc * const sc = PICTOSOFTC(pic); 140 struct cpu_info * const ci = curcpu(); 141 const u_int group = irqbase / 32; 142 143 if (group == 0) { 144 atomic_and_32(&sc->sc_enabled_sgippi, ~mask); 145 gicr_write_4(sc, ci->ci_gic_redist, GICR_ICENABLER0, mask); 146 while (gicr_read_4(sc, ci->ci_gic_redist, GICR_CTLR) & GICR_CTLR_RWP) 147 ; 148 } else { 149 gicd_write_4(sc, GICD_ICENABLERn(group), mask); 150 while (gicd_read_4(sc, GICD_CTRL) & GICD_CTRL_RWP) 151 ; 152 } 153 } 154 155 static void 156 gicv3_establish_irq(struct pic_softc *pic, struct intrsource *is) 157 { 158 struct gicv3_softc * const sc = PICTOSOFTC(pic); 159 const u_int group = is->is_irq / 32; 160 uint32_t ipriority, icfg; 161 uint64_t irouter; 162 u_int n; 163 164 const u_int ipriority_val = IPL_TO_PRIORITY(sc, is->is_ipl); 165 const u_int ipriority_shift = (is->is_irq & 0x3) * 8; 166 const u_int icfg_shift = (is->is_irq & 0xf) * 2; 167 168 if (group == 0) { 169 /* SGIs and PPIs are always MP-safe */ 170 is->is_mpsafe = true; 171 172 /* Update interrupt configuration and priority on all redistributors */ 173 for (n = 0; n < sc->sc_bsh_r_count; n++) { 174 icfg = gicr_read_4(sc, n, GICR_ICFGRn(is->is_irq / 16)); 175 if (is->is_type == IST_LEVEL) 176 icfg &= ~(0x2 << icfg_shift); 177 if (is->is_type == IST_EDGE) 178 icfg |= (0x2 << icfg_shift); 179 gicr_write_4(sc, n, GICR_ICFGRn(is->is_irq / 16), icfg); 180 181 ipriority = gicr_read_4(sc, n, GICR_IPRIORITYRn(is->is_irq / 4)); 182 ipriority &= ~(0xffU << ipriority_shift); 183 ipriority |= (ipriority_val << ipriority_shift); 184 gicr_write_4(sc, n, GICR_IPRIORITYRn(is->is_irq / 4), ipriority); 185 } 186 } else { 187 if (is->is_mpsafe) { 188 /* Route MP-safe interrupts to all participating PEs */ 189 irouter = GICD_IROUTER_Interrupt_Routing_mode; 190 } else { 191 /* Route non-MP-safe interrupts to the primary PE only */ 192 irouter = sc->sc_irouter[0]; 193 } 194 gicd_write_8(sc, GICD_IROUTER(is->is_irq), irouter); 195 196 /* Update interrupt configuration */ 197 icfg = gicd_read_4(sc, GICD_ICFGRn(is->is_irq / 16)); 198 if (is->is_type == IST_LEVEL) 199 icfg &= ~(0x2 << icfg_shift); 200 if (is->is_type == IST_EDGE) 201 icfg |= (0x2 << icfg_shift); 202 gicd_write_4(sc, GICD_ICFGRn(is->is_irq / 16), icfg); 203 204 /* Update interrupt priority */ 205 ipriority = gicd_read_4(sc, GICD_IPRIORITYRn(is->is_irq / 4)); 206 ipriority &= ~(0xffU << ipriority_shift); 207 ipriority |= (ipriority_val << ipriority_shift); 208 gicd_write_4(sc, GICD_IPRIORITYRn(is->is_irq / 4), ipriority); 209 } 210 } 211 212 static void 213 gicv3_set_priority(struct pic_softc *pic, int ipl) 214 { 215 struct gicv3_softc * const sc = PICTOSOFTC(pic); 216 217 icc_pmr_write(IPL_TO_PMR(sc, ipl)); 218 } 219 220 static void 221 gicv3_dist_enable(struct gicv3_softc *sc) 222 { 223 uint32_t gicd_ctrl; 224 u_int n; 225 226 /* Disable the distributor */ 227 gicd_write_4(sc, GICD_CTRL, 0); 228 229 /* Wait for register write to complete */ 230 while (gicd_read_4(sc, GICD_CTRL) & GICD_CTRL_RWP) 231 ; 232 233 /* Clear all INTID enable bits */ 234 for (n = 32; n < sc->sc_pic.pic_maxsources; n += 32) 235 gicd_write_4(sc, GICD_ICENABLERn(n / 32), ~0); 236 237 /* Set default priorities to lowest */ 238 for (n = 32; n < sc->sc_pic.pic_maxsources; n += 4) 239 gicd_write_4(sc, GICD_IPRIORITYRn(n / 4), ~0); 240 241 /* Set all interrupts to G1NS */ 242 for (n = 32; n < sc->sc_pic.pic_maxsources; n += 32) { 243 gicd_write_4(sc, GICD_IGROUPRn(n / 32), ~0); 244 gicd_write_4(sc, GICD_IGRPMODRn(n / 32), 0); 245 } 246 247 /* Set all interrupts level-sensitive by default */ 248 for (n = 32; n < sc->sc_pic.pic_maxsources; n += 16) 249 gicd_write_4(sc, GICD_ICFGRn(n / 16), 0); 250 251 /* Wait for register writes to complete */ 252 while (gicd_read_4(sc, GICD_CTRL) & GICD_CTRL_RWP) 253 ; 254 255 /* Enable Affinity routing and G1NS interrupts */ 256 gicd_ctrl = GICD_CTRL_EnableGrp1A | GICD_CTRL_ARE_NS; 257 gicd_write_4(sc, GICD_CTRL, gicd_ctrl); 258 } 259 260 static void 261 gicv3_redist_enable(struct gicv3_softc *sc, struct cpu_info *ci) 262 { 263 uint32_t icfg; 264 u_int n, o; 265 266 /* Clear INTID enable bits */ 267 gicr_write_4(sc, ci->ci_gic_redist, GICR_ICENABLER0, ~0); 268 269 /* Wait for register write to complete */ 270 while (gicr_read_4(sc, ci->ci_gic_redist, GICR_CTLR) & GICR_CTLR_RWP) 271 ; 272 273 /* Set default priorities */ 274 for (n = 0; n < 32; n += 4) { 275 uint32_t priority = 0; 276 size_t byte_shift = 0; 277 for (o = 0; o < 4; o++, byte_shift += 8) { 278 struct intrsource * const is = sc->sc_pic.pic_sources[n + o]; 279 if (is == NULL) 280 priority |= (0xffU << byte_shift); 281 else { 282 const u_int ipriority_val = IPL_TO_PRIORITY(sc, is->is_ipl); 283 priority |= ipriority_val << byte_shift; 284 } 285 } 286 gicr_write_4(sc, ci->ci_gic_redist, GICR_IPRIORITYRn(n / 4), priority); 287 } 288 289 /* Set all interrupts to G1NS */ 290 gicr_write_4(sc, ci->ci_gic_redist, GICR_IGROUPR0, ~0); 291 gicr_write_4(sc, ci->ci_gic_redist, GICR_IGRPMODR0, 0); 292 293 /* Restore PPI configs */ 294 for (n = 0, icfg = 0; n < 16; n++) { 295 struct intrsource * const is = sc->sc_pic.pic_sources[16 + n]; 296 if (is != NULL && is->is_type == IST_EDGE) 297 icfg |= (0x2 << (n * 2)); 298 } 299 gicr_write_4(sc, ci->ci_gic_redist, GICR_ICFGRn(1), icfg); 300 301 /* Restore current enable bits */ 302 gicr_write_4(sc, ci->ci_gic_redist, GICR_ISENABLER0, sc->sc_enabled_sgippi); 303 304 /* Wait for register write to complete */ 305 while (gicr_read_4(sc, ci->ci_gic_redist, GICR_CTLR) & GICR_CTLR_RWP) 306 ; 307 } 308 309 static uint64_t 310 gicv3_cpu_identity(void) 311 { 312 u_int aff3, aff2, aff1, aff0; 313 314 const register_t mpidr = cpu_mpidr_aff_read(); 315 aff0 = __SHIFTOUT(mpidr, MPIDR_AFF0); 316 aff1 = __SHIFTOUT(mpidr, MPIDR_AFF1); 317 aff2 = __SHIFTOUT(mpidr, MPIDR_AFF2); 318 aff3 = __SHIFTOUT(mpidr, MPIDR_AFF3); 319 320 return __SHIFTIN(aff0, GICR_TYPER_Affinity_Value_Aff0) | 321 __SHIFTIN(aff1, GICR_TYPER_Affinity_Value_Aff1) | 322 __SHIFTIN(aff2, GICR_TYPER_Affinity_Value_Aff2) | 323 __SHIFTIN(aff3, GICR_TYPER_Affinity_Value_Aff3); 324 } 325 326 static u_int 327 gicv3_find_redist(struct gicv3_softc *sc) 328 { 329 uint64_t gicr_typer; 330 u_int n; 331 332 const uint64_t cpu_identity = gicv3_cpu_identity(); 333 334 for (n = 0; n < sc->sc_bsh_r_count; n++) { 335 gicr_typer = gicr_read_8(sc, n, GICR_TYPER); 336 if ((gicr_typer & GICR_TYPER_Affinity_Value) == cpu_identity) 337 return n; 338 } 339 340 const u_int aff0 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff0); 341 const u_int aff1 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff1); 342 const u_int aff2 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff2); 343 const u_int aff3 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff3); 344 345 panic("%s: could not find GICv3 redistributor for cpu %d.%d.%d.%d", 346 cpu_name(curcpu()), aff3, aff2, aff1, aff0); 347 } 348 349 static uint64_t 350 gicv3_sgir(struct gicv3_softc *sc) 351 { 352 const uint64_t cpu_identity = gicv3_cpu_identity(); 353 354 const u_int aff0 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff0); 355 const u_int aff1 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff1); 356 const u_int aff2 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff2); 357 const u_int aff3 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff3); 358 359 return __SHIFTIN(__BIT(aff0), ICC_SGIR_EL1_TargetList) | 360 __SHIFTIN(aff1, ICC_SGIR_EL1_Aff1) | 361 __SHIFTIN(aff2, ICC_SGIR_EL1_Aff2) | 362 __SHIFTIN(aff3, ICC_SGIR_EL1_Aff3); 363 } 364 365 static void 366 gicv3_cpu_init(struct pic_softc *pic, struct cpu_info *ci) 367 { 368 struct gicv3_softc * const sc = PICTOSOFTC(pic); 369 uint32_t icc_sre, icc_ctlr, gicr_waker; 370 371 ci->ci_gic_redist = gicv3_find_redist(sc); 372 ci->ci_gic_sgir = gicv3_sgir(sc); 373 374 /* Store route to CPU for SPIs */ 375 const uint64_t cpu_identity = gicv3_cpu_identity(); 376 const u_int aff0 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff0); 377 const u_int aff1 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff1); 378 const u_int aff2 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff2); 379 const u_int aff3 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff3); 380 sc->sc_irouter[cpu_index(ci)] = 381 __SHIFTIN(aff0, GICD_IROUTER_Aff0) | 382 __SHIFTIN(aff1, GICD_IROUTER_Aff1) | 383 __SHIFTIN(aff2, GICD_IROUTER_Aff2) | 384 __SHIFTIN(aff3, GICD_IROUTER_Aff3); 385 386 /* Enable System register access and disable IRQ/FIQ bypass */ 387 icc_sre = ICC_SRE_EL1_SRE | ICC_SRE_EL1_DFB | ICC_SRE_EL1_DIB; 388 icc_sre_write(icc_sre); 389 390 /* Mark the connected PE as being awake */ 391 gicr_waker = gicr_read_4(sc, ci->ci_gic_redist, GICR_WAKER); 392 gicr_waker &= ~GICR_WAKER_ProcessorSleep; 393 gicr_write_4(sc, ci->ci_gic_redist, GICR_WAKER, gicr_waker); 394 while (gicr_read_4(sc, ci->ci_gic_redist, GICR_WAKER) & GICR_WAKER_ChildrenAsleep) 395 ; 396 397 /* Set initial priority mask */ 398 gicv3_set_priority(pic, IPL_HIGH); 399 400 /* Set the binary point field to the minimum value */ 401 icc_bpr1_write(0); 402 403 /* Enable group 1 interrupt signaling */ 404 icc_igrpen1_write(ICC_IGRPEN_EL1_Enable); 405 406 /* Set EOI mode */ 407 icc_ctlr = icc_ctlr_read(); 408 icc_ctlr &= ~ICC_CTLR_EL1_EOImode; 409 icc_ctlr_write(icc_ctlr); 410 411 /* Enable redistributor */ 412 gicv3_redist_enable(sc, ci); 413 414 /* Allow IRQ exceptions */ 415 cpsie(I32_bit); 416 } 417 418 #ifdef MULTIPROCESSOR 419 static void 420 gicv3_ipi_send(struct pic_softc *pic, const kcpuset_t *kcp, u_long ipi) 421 { 422 struct cpu_info *ci; 423 uint64_t sgir; 424 425 sgir = __SHIFTIN(ipi, ICC_SGIR_EL1_INTID); 426 if (kcp == NULL) { 427 /* Interrupts routed to all PEs, excluding "self" */ 428 if (ncpu == 1) 429 return; 430 sgir |= ICC_SGIR_EL1_IRM; 431 } else { 432 /* Interrupt to exactly one PE */ 433 ci = cpu_lookup(kcpuset_ffs(kcp) - 1); 434 if (ci == curcpu()) 435 return; 436 sgir |= ci->ci_gic_sgir; 437 } 438 icc_sgi1r_write(sgir); 439 isb(); 440 } 441 442 static void 443 gicv3_get_affinity(struct pic_softc *pic, size_t irq, kcpuset_t *affinity) 444 { 445 struct gicv3_softc * const sc = PICTOSOFTC(pic); 446 const size_t group = irq / 32; 447 int n; 448 449 kcpuset_zero(affinity); 450 if (group == 0) { 451 /* All CPUs are targets for group 0 (SGI/PPI) */ 452 for (n = 0; n < ncpu; n++) { 453 if (sc->sc_irouter[n] != UINT64_MAX) 454 kcpuset_set(affinity, n); 455 } 456 } else { 457 /* Find distributor targets (SPI) */ 458 const uint64_t irouter = gicd_read_8(sc, GICD_IROUTER(irq)); 459 for (n = 0; n < ncpu; n++) { 460 if (irouter == GICD_IROUTER_Interrupt_Routing_mode || 461 irouter == sc->sc_irouter[n]) 462 kcpuset_set(affinity, n); 463 } 464 } 465 } 466 467 static int 468 gicv3_set_affinity(struct pic_softc *pic, size_t irq, const kcpuset_t *affinity) 469 { 470 struct gicv3_softc * const sc = PICTOSOFTC(pic); 471 const size_t group = irq / 32; 472 uint64_t irouter; 473 474 if (group == 0) 475 return EINVAL; 476 477 const int set = kcpuset_countset(affinity); 478 if (set == ncpu) 479 irouter = GICD_IROUTER_Interrupt_Routing_mode; 480 else if (set == 1) 481 irouter = sc->sc_irouter[kcpuset_ffs(affinity) - 1]; 482 else 483 return EINVAL; 484 485 gicd_write_8(sc, GICD_IROUTER(irq), irouter); 486 487 return 0; 488 } 489 #endif 490 491 static const struct pic_ops gicv3_picops = { 492 .pic_unblock_irqs = gicv3_unblock_irqs, 493 .pic_block_irqs = gicv3_block_irqs, 494 .pic_establish_irq = gicv3_establish_irq, 495 .pic_set_priority = gicv3_set_priority, 496 #ifdef MULTIPROCESSOR 497 .pic_cpu_init = gicv3_cpu_init, 498 .pic_ipi_send = gicv3_ipi_send, 499 .pic_get_affinity = gicv3_get_affinity, 500 .pic_set_affinity = gicv3_set_affinity, 501 #endif 502 }; 503 504 static void 505 gicv3_lpi_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t mask) 506 { 507 struct gicv3_softc * const sc = LPITOSOFTC(pic); 508 int bit; 509 510 while ((bit = ffs(mask)) != 0) { 511 sc->sc_lpiconf.base[irqbase + bit - 1] |= GIC_LPICONF_Enable; 512 if (sc->sc_lpiconf_flush) 513 cpu_dcache_wb_range((vaddr_t)&sc->sc_lpiconf.base[irqbase + bit - 1], 1); 514 mask &= ~__BIT(bit - 1); 515 } 516 517 if (!sc->sc_lpiconf_flush) 518 dsb(ishst); 519 } 520 521 static void 522 gicv3_lpi_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t mask) 523 { 524 struct gicv3_softc * const sc = LPITOSOFTC(pic); 525 int bit; 526 527 while ((bit = ffs(mask)) != 0) { 528 sc->sc_lpiconf.base[irqbase + bit - 1] &= ~GIC_LPICONF_Enable; 529 if (sc->sc_lpiconf_flush) 530 cpu_dcache_wb_range((vaddr_t)&sc->sc_lpiconf.base[irqbase + bit - 1], 1); 531 mask &= ~__BIT(bit - 1); 532 } 533 534 if (!sc->sc_lpiconf_flush) 535 dsb(ishst); 536 } 537 538 static void 539 gicv3_lpi_establish_irq(struct pic_softc *pic, struct intrsource *is) 540 { 541 struct gicv3_softc * const sc = LPITOSOFTC(pic); 542 543 sc->sc_lpiconf.base[is->is_irq] = IPL_TO_LPIPRIO(sc, is->is_ipl) | GIC_LPICONF_Res1; 544 545 if (sc->sc_lpiconf_flush) 546 cpu_dcache_wb_range((vaddr_t)&sc->sc_lpiconf.base[is->is_irq], 1); 547 else 548 dsb(ishst); 549 } 550 551 static void 552 gicv3_lpi_cpu_init(struct pic_softc *pic, struct cpu_info *ci) 553 { 554 struct gicv3_softc * const sc = LPITOSOFTC(pic); 555 struct gicv3_lpi_callback *cb; 556 uint64_t propbase, pendbase; 557 uint32_t ctlr; 558 559 /* If physical LPIs are not supported on this redistributor, just return. */ 560 const uint64_t typer = gicr_read_8(sc, ci->ci_gic_redist, GICR_TYPER); 561 if ((typer & GICR_TYPER_PLPIS) == 0) 562 return; 563 564 /* Interrupt target address for this CPU, used by ITS when GITS_TYPER.PTA == 0 */ 565 sc->sc_processor_id[cpu_index(ci)] = __SHIFTOUT(typer, GICR_TYPER_Processor_Number); 566 567 /* Disable LPIs before making changes */ 568 ctlr = gicr_read_4(sc, ci->ci_gic_redist, GICR_CTLR); 569 ctlr &= ~GICR_CTLR_Enable_LPIs; 570 gicr_write_4(sc, ci->ci_gic_redist, GICR_CTLR, ctlr); 571 dsb(sy); 572 573 /* Setup the LPI configuration table */ 574 propbase = sc->sc_lpiconf.segs[0].ds_addr | 575 __SHIFTIN(ffs(pic->pic_maxsources) - 1, GICR_PROPBASER_IDbits) | 576 __SHIFTIN(GICR_Shareability_IS, GICR_PROPBASER_Shareability) | 577 __SHIFTIN(GICR_Cache_NORMAL_RA_WA_WB, GICR_PROPBASER_InnerCache); 578 gicr_write_8(sc, ci->ci_gic_redist, GICR_PROPBASER, propbase); 579 propbase = gicr_read_8(sc, ci->ci_gic_redist, GICR_PROPBASER); 580 if (__SHIFTOUT(propbase, GICR_PROPBASER_Shareability) != GICR_Shareability_IS) { 581 if (__SHIFTOUT(propbase, GICR_PROPBASER_Shareability) == GICR_Shareability_NS) { 582 propbase &= ~GICR_PROPBASER_Shareability; 583 propbase |= __SHIFTIN(GICR_Shareability_NS, GICR_PROPBASER_Shareability); 584 propbase &= ~GICR_PROPBASER_InnerCache; 585 propbase |= __SHIFTIN(GICR_Cache_NORMAL_NC, GICR_PROPBASER_InnerCache); 586 gicr_write_8(sc, ci->ci_gic_redist, GICR_PROPBASER, propbase); 587 } 588 sc->sc_lpiconf_flush = true; 589 } 590 591 /* Setup the LPI pending table */ 592 pendbase = sc->sc_lpipend[cpu_index(ci)].segs[0].ds_addr | 593 __SHIFTIN(GICR_Shareability_IS, GICR_PENDBASER_Shareability) | 594 __SHIFTIN(GICR_Cache_NORMAL_RA_WA_WB, GICR_PENDBASER_InnerCache); 595 gicr_write_8(sc, ci->ci_gic_redist, GICR_PENDBASER, pendbase); 596 pendbase = gicr_read_8(sc, ci->ci_gic_redist, GICR_PENDBASER); 597 if (__SHIFTOUT(pendbase, GICR_PENDBASER_Shareability) == GICR_Shareability_NS) { 598 pendbase &= ~GICR_PENDBASER_Shareability; 599 pendbase |= __SHIFTIN(GICR_Shareability_NS, GICR_PENDBASER_Shareability); 600 pendbase &= ~GICR_PENDBASER_InnerCache; 601 pendbase |= __SHIFTIN(GICR_Cache_NORMAL_NC, GICR_PENDBASER_InnerCache); 602 gicr_write_8(sc, ci->ci_gic_redist, GICR_PENDBASER, pendbase); 603 } 604 605 /* Enable LPIs */ 606 ctlr = gicr_read_4(sc, ci->ci_gic_redist, GICR_CTLR); 607 ctlr |= GICR_CTLR_Enable_LPIs; 608 gicr_write_4(sc, ci->ci_gic_redist, GICR_CTLR, ctlr); 609 dsb(sy); 610 611 /* Setup ITS if present */ 612 LIST_FOREACH(cb, &sc->sc_lpi_callbacks, list) 613 cb->cpu_init(cb->priv, ci); 614 } 615 616 #ifdef MULTIPROCESSOR 617 static void 618 gicv3_lpi_get_affinity(struct pic_softc *pic, size_t irq, kcpuset_t *affinity) 619 { 620 struct gicv3_softc * const sc = LPITOSOFTC(pic); 621 struct gicv3_lpi_callback *cb; 622 623 kcpuset_zero(affinity); 624 LIST_FOREACH(cb, &sc->sc_lpi_callbacks, list) 625 cb->get_affinity(cb->priv, irq, affinity); 626 } 627 628 static int 629 gicv3_lpi_set_affinity(struct pic_softc *pic, size_t irq, const kcpuset_t *affinity) 630 { 631 struct gicv3_softc * const sc = LPITOSOFTC(pic); 632 struct gicv3_lpi_callback *cb; 633 int error = EINVAL; 634 635 LIST_FOREACH(cb, &sc->sc_lpi_callbacks, list) { 636 error = cb->set_affinity(cb->priv, irq, affinity); 637 if (error != EPASSTHROUGH) 638 return error; 639 } 640 641 return EINVAL; 642 } 643 #endif 644 645 static const struct pic_ops gicv3_lpiops = { 646 .pic_unblock_irqs = gicv3_lpi_unblock_irqs, 647 .pic_block_irqs = gicv3_lpi_block_irqs, 648 .pic_establish_irq = gicv3_lpi_establish_irq, 649 #ifdef MULTIPROCESSOR 650 .pic_cpu_init = gicv3_lpi_cpu_init, 651 .pic_get_affinity = gicv3_lpi_get_affinity, 652 .pic_set_affinity = gicv3_lpi_set_affinity, 653 #endif 654 }; 655 656 void 657 gicv3_dma_alloc(struct gicv3_softc *sc, struct gicv3_dma *dma, bus_size_t len, bus_size_t align) 658 { 659 int nsegs, error; 660 661 dma->len = len; 662 error = bus_dmamem_alloc(sc->sc_dmat, dma->len, align, 0, dma->segs, 1, &nsegs, BUS_DMA_WAITOK); 663 if (error) 664 panic("bus_dmamem_alloc failed: %d", error); 665 error = bus_dmamem_map(sc->sc_dmat, dma->segs, nsegs, len, (void **)&dma->base, BUS_DMA_WAITOK); 666 if (error) 667 panic("bus_dmamem_map failed: %d", error); 668 error = bus_dmamap_create(sc->sc_dmat, len, 1, len, 0, BUS_DMA_WAITOK, &dma->map); 669 if (error) 670 panic("bus_dmamap_create failed: %d", error); 671 error = bus_dmamap_load(sc->sc_dmat, dma->map, dma->base, dma->len, NULL, BUS_DMA_WAITOK); 672 if (error) 673 panic("bus_dmamap_load failed: %d", error); 674 675 memset(dma->base, 0, dma->len); 676 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, dma->len, BUS_DMASYNC_PREWRITE); 677 } 678 679 static void 680 gicv3_lpi_init(struct gicv3_softc *sc) 681 { 682 /* 683 * Allocate LPI configuration table 684 */ 685 gicv3_dma_alloc(sc, &sc->sc_lpiconf, sc->sc_lpi.pic_maxsources, 0x1000); 686 KASSERT((sc->sc_lpiconf.segs[0].ds_addr & ~GICR_PROPBASER_Physical_Address) == 0); 687 688 /* 689 * Allocate LPI pending tables 690 */ 691 const bus_size_t lpipend_sz = (8192 + sc->sc_lpi.pic_maxsources) / NBBY; 692 for (int cpuindex = 0; cpuindex < ncpu; cpuindex++) { 693 gicv3_dma_alloc(sc, &sc->sc_lpipend[cpuindex], lpipend_sz, 0x10000); 694 KASSERT((sc->sc_lpipend[cpuindex].segs[0].ds_addr & ~GICR_PENDBASER_Physical_Address) == 0); 695 } 696 } 697 698 void 699 gicv3_irq_handler(void *frame) 700 { 701 struct cpu_info * const ci = curcpu(); 702 struct gicv3_softc * const sc = gicv3_softc; 703 struct pic_softc *pic; 704 const int oldipl = ci->ci_cpl; 705 706 ci->ci_data.cpu_nintr++; 707 708 for (;;) { 709 const uint32_t iar = icc_iar1_read(); 710 dsb(sy); 711 const uint32_t irq = __SHIFTOUT(iar, ICC_IAR_INTID); 712 if (irq == ICC_IAR_INTID_SPURIOUS) 713 break; 714 715 pic = irq >= GIC_LPI_BASE ? &sc->sc_lpi : &sc->sc_pic; 716 if (irq - pic->pic_irqbase >= pic->pic_maxsources) 717 continue; 718 719 struct intrsource * const is = pic->pic_sources[irq - pic->pic_irqbase]; 720 KASSERT(is != NULL); 721 722 const bool early_eoi = irq < GIC_LPI_BASE && is->is_type == IST_EDGE; 723 724 const int ipl = is->is_ipl; 725 if (__predict_false(ipl < ci->ci_cpl)) { 726 pic_do_pending_ints(I32_bit, ipl, frame); 727 } else if (ci->ci_cpl != ipl) { 728 gicv3_set_priority(pic, ipl); 729 ci->ci_cpl = ipl; 730 } 731 732 if (early_eoi) { 733 icc_eoi1r_write(iar); 734 isb(); 735 } 736 737 cpsie(I32_bit); 738 pic_dispatch(is, frame); 739 cpsid(I32_bit); 740 741 if (!early_eoi) { 742 icc_eoi1r_write(iar); 743 isb(); 744 } 745 } 746 747 pic_do_pending_ints(I32_bit, oldipl, frame); 748 } 749 750 static int 751 gicv3_detect_pmr_bits(struct gicv3_softc *sc) 752 { 753 const uint32_t opmr = icc_pmr_read(); 754 icc_pmr_write(0xbf); 755 const uint32_t npmr = icc_pmr_read(); 756 icc_pmr_write(opmr); 757 758 return NBBY - (ffs(npmr) - 1); 759 } 760 761 static int 762 gicv3_detect_ipriority_bits(struct gicv3_softc *sc) 763 { 764 const uint32_t oipriorityr = gicd_read_4(sc, GICD_IPRIORITYRn(8)); 765 gicd_write_4(sc, GICD_IPRIORITYRn(8), oipriorityr | 0xff); 766 const uint32_t nipriorityr = gicd_read_4(sc, GICD_IPRIORITYRn(8)); 767 gicd_write_4(sc, GICD_IPRIORITYRn(8), oipriorityr); 768 769 return NBBY - (ffs(nipriorityr & 0xff) - 1); 770 } 771 772 int 773 gicv3_init(struct gicv3_softc *sc) 774 { 775 const uint32_t gicd_typer = gicd_read_4(sc, GICD_TYPER); 776 const uint32_t gicd_ctrl = gicd_read_4(sc, GICD_CTRL); 777 int n; 778 779 KASSERT(CPU_IS_PRIMARY(curcpu())); 780 781 LIST_INIT(&sc->sc_lpi_callbacks); 782 783 for (n = 0; n < MAXCPUS; n++) 784 sc->sc_irouter[n] = UINT64_MAX; 785 786 sc->sc_priority_shift = 4; 787 sc->sc_pmr_shift = 4; 788 789 if ((gicd_ctrl & GICD_CTRL_DS) == 0) { 790 const int pmr_bits = gicv3_detect_pmr_bits(sc); 791 const int ipriority_bits = gicv3_detect_ipriority_bits(sc); 792 793 if (ipriority_bits != pmr_bits) 794 --sc->sc_priority_shift; 795 796 aprint_verbose_dev(sc->sc_dev, "%d pmr bits, %d ipriority bits\n", 797 pmr_bits, ipriority_bits); 798 } else { 799 aprint_verbose_dev(sc->sc_dev, "security disabled\n"); 800 } 801 802 aprint_verbose_dev(sc->sc_dev, "priority shift %d, pmr shift %d\n", 803 sc->sc_priority_shift, sc->sc_pmr_shift); 804 805 sc->sc_pic.pic_ops = &gicv3_picops; 806 sc->sc_pic.pic_maxsources = GICD_TYPER_LINES(gicd_typer); 807 snprintf(sc->sc_pic.pic_name, sizeof(sc->sc_pic.pic_name), "gicv3"); 808 #ifdef MULTIPROCESSOR 809 sc->sc_pic.pic_cpus = kcpuset_running; 810 #endif 811 pic_add(&sc->sc_pic, 0); 812 813 if ((gicd_typer & GICD_TYPER_LPIS) != 0) { 814 sc->sc_lpi.pic_ops = &gicv3_lpiops; 815 sc->sc_lpi.pic_maxsources = 8192; /* Min. required by GICv3 spec */ 816 snprintf(sc->sc_lpi.pic_name, sizeof(sc->sc_lpi.pic_name), "gicv3-lpi"); 817 pic_add(&sc->sc_lpi, GIC_LPI_BASE); 818 819 sc->sc_lpi_pool = vmem_create("gicv3-lpi", 0, sc->sc_lpi.pic_maxsources, 820 1, NULL, NULL, NULL, 0, VM_SLEEP, IPL_HIGH); 821 if (sc->sc_lpi_pool == NULL) 822 panic("failed to create gicv3 lpi pool\n"); 823 824 gicv3_lpi_init(sc); 825 } 826 827 KASSERT(gicv3_softc == NULL); 828 gicv3_softc = sc; 829 830 for (int i = 0; i < sc->sc_bsh_r_count; i++) { 831 const uint64_t gicr_typer = gicr_read_8(sc, i, GICR_TYPER); 832 const u_int aff0 = __SHIFTOUT(gicr_typer, GICR_TYPER_Affinity_Value_Aff0); 833 const u_int aff1 = __SHIFTOUT(gicr_typer, GICR_TYPER_Affinity_Value_Aff1); 834 const u_int aff2 = __SHIFTOUT(gicr_typer, GICR_TYPER_Affinity_Value_Aff2); 835 const u_int aff3 = __SHIFTOUT(gicr_typer, GICR_TYPER_Affinity_Value_Aff3); 836 837 aprint_debug_dev(sc->sc_dev, "redist %d: cpu %d.%d.%d.%d\n", 838 i, aff3, aff2, aff1, aff0); 839 } 840 841 gicv3_dist_enable(sc); 842 843 gicv3_cpu_init(&sc->sc_pic, curcpu()); 844 if ((gicd_typer & GICD_TYPER_LPIS) != 0) 845 gicv3_lpi_cpu_init(&sc->sc_lpi, curcpu()); 846 847 #ifdef MULTIPROCESSOR 848 intr_establish_xname(IPI_AST, IPL_VM, IST_MPSAFE | IST_EDGE, pic_ipi_ast, (void *)-1, "IPI ast"); 849 intr_establish_xname(IPI_XCALL, IPL_HIGH, IST_MPSAFE | IST_EDGE, pic_ipi_xcall, (void *)-1, "IPI xcall"); 850 intr_establish_xname(IPI_GENERIC, IPL_HIGH, IST_MPSAFE | IST_EDGE, pic_ipi_generic, (void *)-1, "IPI generic"); 851 intr_establish_xname(IPI_NOP, IPL_VM, IST_MPSAFE | IST_EDGE, pic_ipi_nop, (void *)-1, "IPI nop"); 852 intr_establish_xname(IPI_SHOOTDOWN, IPL_SCHED, IST_MPSAFE | IST_EDGE, pic_ipi_shootdown, (void *)-1, "IPI shootdown"); 853 #ifdef DDB 854 intr_establish_xname(IPI_DDB, IPL_HIGH, IST_MPSAFE | IST_EDGE, pic_ipi_ddb, NULL, "IPI ddb"); 855 #endif 856 #ifdef __HAVE_PREEMPTION 857 intr_establish_xname(IPI_KPREEMPT, IPL_VM, IST_MPSAFE | IST_EDGE, pic_ipi_kpreempt, (void *)-1, "IPI kpreempt"); 858 #endif 859 #endif 860 861 return 0; 862 } 863