1 /* $NetBSD: gic_reg.h,v 1.1 2012/09/01 00:03:14 matt Exp $ */ 2 /*- 3 * Copyright (c) 2012 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas of 3am Software Foundry. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * ARM Generic Interrupt Controller Register Definitions 33 * 34 * These registers are accessible through a dedicated internal bus. 35 * All accesses must be done in a little-endian manner. 36 * The base address of the pages containing these registers is defined 37 * by the pins PERIPHBASE[31:13] which can be obtained by doing a 38 * MRC p15,4,<Rd>,c15,c0,0; Read Configuration Base Address Register 39 * (except cortex-A9 uniprocessor) 40 * 41 * GIC is used by all Cortex-A cores except the A8. 42 */ 43 44 #ifndef _ARM_CORTEX_GICREG_H_ 45 #define _ARM_CORTEX_GICREG_H_ 46 47 #define GICC_BASE 0x0100 // Offset in PeriphBase 48 49 #define GICC_CTRL 0x0000 // CPU Interface Control Register 50 #define GICC_PMR 0x0004 // Interrupt Priority Mask Register 51 #define GICC_BPR 0x0008 // Aliased Binary Point Register 52 #define GICC_IAR 0x000C // Interrupt Acknowledge Register 53 #define GICC_EOIR 0x0010 // End Of Interrupt Register (WO) 54 #define GICC_RPR 0x0014 // Running Priority Register 55 #define GICC_HPPIR 0x0018 // Highest Priority Pending Interrupt Registers 56 #define GICC_ABPR 0x001C // Aliased Binary Point Register 57 #define GICC_AIAR 0x0020 // Aliased Interrupt Acknowledge Register 58 #define GICC_AEOIR 0x0024 // Aliased End Of Interrupt Register 59 #define GICC_AHPPIR 0x0028 // Aliased Highest Priority Pending Interrupt Registers 60 #define GICC_APR0 0x00D0 // Active Priorites Register 0 61 #define GICC_APR1 0x00D4 // Active Priorites Register 1 62 #define GICC_APR2 0x00D8 // Active Priorites Register 2 63 #define GICC_APR3 0x00DC // Active Priorites Register 3 64 #define GICC_NSAPR0 0x00E0 // Non-secure Active Priorities Register 0 65 #define GICC_NSAPR1 0x00E4 // Non-secure Active Priorities Register 1 66 #define GICC_NSAPR2 0x00E8 // Non-secure Active Priorities Register 2 67 #define GICC_NSAPR3 0x00EC // Non-secure Active Priorities Register 3 68 #define GICC_IIDR 0x00FC // CPU Interface Identification Register 69 #define GICC_DIR 0x1000 // Deactivate Interrupt Register 70 71 72 #define GICC_CTRL_V1_Enable __BIT(0) // GICv1 73 74 #define GICC_CTRL_V2_EnableGrp0 __BIT(0) // GICv2 !Secure | Secure 75 #define GICC_CTRL_V2_EnableGrp1 __BIT(1) // GICv2 !Secure | Secure 76 77 #define GICC_CTRL_V2S_EOImodeNS __BIT(9) // GICv2 Secure 78 #define GICC_CTRL_V2S_IRQBypDisGrp1 __BIT(6) // GICv2 Secure 79 #define GICC_CTRL_V2S_FIQBypDisGrp1 __BIT(4) // GICv2 Secure 80 81 #define GICC_CTRL_V2NS_EOImodeNS __BIT(10) // GICv2 !Secure 82 #define GICC_CTRL_V2NS_EOImodeS __BIT(9) // GICv2 !Secure 83 #define GICC_CTRL_V2NS_IRQBypDisGrp1 __BIT(8) // GICv2 !Secure 84 #define GICC_CTRL_V2NS_FIQBypDisGrp1 __BIT(7) // GICv2 !Secure 85 #define GICC_CTRL_V2NS_IRQBypDisGrp0 __BIT(6) // GICv2 !Secure 86 #define GICC_CTRL_V2NS_FIQBypDisGrp0 __BIT(5) // GICv2 !Secure 87 #define GICC_CTRL_V2NS_CPBR __BIT(4) // GICv2 !Secure 88 #define GICC_CTRL_V2NS_FIQEn __BIT(3) // GICv2 !Secure 89 #define GICC_CTRL_V2NS_AckCtl __BIT(2) // GICv2 !Secure 90 91 #define GICC_PMR_PRIORITY __BITS(7,0) 92 #define GICC_PMR_PRIORITIES 256 93 #define GICC_PMR_8_LEVELS 0x1f 94 #define GICC_PMR_16_LEVELS 0x0f 95 #define GICC_PMR_32_LEVELS 0x07 96 #define GICC_PMR_64_LEVELS 0x03 97 #define GICC_PMR_128_LEVELS 0x01 98 99 #define GICC_IAR_CPUID __BITS(12,10) 100 #define GICC_IAR_IRQ __BITS(9,0) 101 #define GICC_IAR_IRQ_SPURIOUS 1023 102 103 #define GICC_EOIR_CPUID __BITS(12,10) 104 #define GICC_EOIR_InterruptID __BITS(9,0) 105 106 #define GICC_HPPIR_CPUID __BITS(12,10) 107 #define GICC_HPPIR_PendIntID __BITS(9,0) 108 109 #define GICC_IIDR_ProductID __BITS(31,20) 110 #define GICC_IIDR_ArchVersion __BITS(19,16) 111 #define GICC_IIDR_Revision __BITS(15,12) 112 #define GICC_IIDR_Implementer __BITS(11,0) 113 114 #define GICC_DIR_CPUID __BITS(12,10) 115 #define GICC_DIR_InterruptID __BITS(9,0) 116 117 #define GICD_BASE 0x1000 // Offset from PeriphBase 118 119 #define GICD_CTRL 0x000 // Distributor Control Register 120 #define GICD_TYPER 0x004 // Interrupt Controller Type Register 121 #define GICD_IIDR 0x008 // Distributor Implementer Identification Register 122 #define GICD_IGROUPRn(n) (0x080+4*(n)) // Interrupt Group Registers 123 #define GICD_ISENABLERn(n) (0x100+4*(n)) // Interrupt Set-Enable Registers 124 #define GICD_ICENABLERn(n) (0x180+4*(n)) // Interrupt Clear-Enable Registers 125 #define GICD_ISPENDRn(n) (0x200+4*(n)) // Interrupt Set-Pending Registers 126 #define GICD_ICPENDRn(n) (0x280+4*(n)) // Interrupt Clear-Pending Registers 127 #define GICD_ISACTIVERn(n) (0x300+4*(n)) // GICv2 Interrupt Set-Active Registers 128 #define GICD_ICACTIVERn(n) (0x380+4*(n)) // Interrupt Clear-Active Registers 129 #define GICD_IPRIORITYRn(n) (0x400+4*(n)) // Interrupt Priority Registers 130 131 #define GICD_ITARGETSRn(n) (0x800+4*(n)) // Interrupt Processor Targets Registers 132 #define GICD_ICFGRn(n) (0xC00+4*(n)) // Interrupt Configuration Registers 133 #define GICD_NSACRn(n) (0xE00+4*(n)) // Non-secure Access Control Registers, optional 134 #define GICD_SGIR 0xF00 // Software Generated Interrupt Register 135 #define GICD_CPENDSGIR(n) (0xF10+4*(n)) // SGI Clear-Pending Registers 136 #define GICD_SPENDSGIR(n) (0xF20+4*(n)) // SGI Set-Pending Registers 137 138 #define GICD_CTRL_Enable __BIT(0) 139 140 #define GICD_TYPER_LSPI __BITS(15,11) 141 #define GICD_TYPER_SecurityExtn __BIT(10) 142 #define GICD_TYPER_CPUNumber __BITS(7,5) 143 #define GICD_TYPER_ITLinesNumber __BITS(4,0) // 32*(N+1) 144 #define GICD_TYPER_LINES(n) MIN(32*(__SHIFTOUT((n), GICD_TYPER_ITLinesNumber) + 1), 1020) 145 146 #define GICD_IIDR_ProductId __BITS(31,24) 147 #define GICD_IIDR_Variant __BITS(19,16) 148 #define GICD_IIDR_Revision __BITS(15,12) 149 #define GICD_IIDR_Implementer __BITS(11,0) 150 151 /* 152 * This register is byte-accessible but always little-endian. 153 */ 154 #define GICD_IPRIORITYR_Byte3 __BITS(31,24) 155 #define GICD_IPRIORITYR_Byte1 __BITS(23,16) 156 #define GICD_IPRIORITYR_Byte2 __BITS(15,8) 157 #define GICD_IPRIORITYR_Byte0 __BITS(7,0) 158 159 /* 160 * This register is byte-accessible but always little-endian. 161 */ 162 #define GICD_ITARGETSR_Byte3 __BITS(31,24) 163 #define GICD_ITARGETSR_Byte1 __BITS(23,16) 164 #define GICD_ITARGETSR_Byte2 __BITS(15,8) 165 #define GICD_ITARGETSR_Byte0 __BITS(7,0) 166 167 #define GICD_SGIR_TargetListFilter __BITS(25,24) 168 #define GICD_SGIR_TargetListFilter_List __SHIFTIN(0, GICD_SGIR_TargetListFilter) 169 #define GICD_SGIR_TargetListFilter_NotMe __SHIFTIN(1, GICD_SGIR_TargetListFilter) 170 #define GICD_SGIR_TargetListFilter_Me __SHIFTIN(2, GICD_SGIR_TargetListFilter) 171 #define GICD_SGIR_TargetList __BITS(23,16) 172 #define GICD_SGIR_NSATT __BIT(15) 173 #define GICD_SGIR_SGIINTID __BITS(3,0) 174 175 /* 176 * GICv1 names 177 */ 178 #define GICv1_ICDDCR GICD_CTLR 179 #define GICv1_ICDICTR GICD_TYPER 180 #define GICv1_ICDIIDR GICD_IIDR 181 #define GICv1_ICDISRn(n) GICD_IGROUPRn(n) 182 #define GICv1_ICDABRn(n) GICD_ISACTIVERn(n) 183 #define GICv1_ICDISERn(n) GICD_ISENABLERn(n) 184 #define GICv1_ICDICERn(n) GICD_ICENABLERn(n) 185 #define GICv1_ICDISPRn(n) GICD_ISPENDRn(n) 186 #define GICv1_ICDICPRn(n) GICD_ICPENDRn(n) 187 #define GICv1_ICDIPRn(n) GICD_IPRIORITYRn(n) 188 #define GICv1_ICDIPTRn(n) GICD_ITARGETSRn(n) 189 #define GICv1_ICDICRn(n) GICD_ICFGRn(n) 190 #define GICv1_ICDSGIR GICD_SGIR 191 192 #define GICv1_ICCICR GICC_CTLR 193 #define GICv1_ICCPMR GICC_PMR 194 #define GICv1_ICCBPR GICC_BPR 195 #define GICv1_ICCIAR GICC_IAR 196 #define GICv1_ICCEOIR GICC_EOIR 197 #define GICv1_ICCRPR GICC_RPR 198 #define GICv1_ICCABPR GICC_ABPR 199 #define GICv1_ICCHPIR GICC_HPPIR 200 #define GICv1_ICCIIDR GICC_IIDR 201 202 #endif /* !_ARM_CORTEX_GICREG_H_ */ 203