1 /* $NetBSD: gic.c,v 1.20 2015/07/29 04:59:48 matt Exp $ */ 2 /*- 3 * Copyright (c) 2012 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas of 3am Software Foundry. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "opt_ddb.h" 32 #include "opt_multiprocessor.h" 33 34 #define _INTR_PRIVATE 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.20 2015/07/29 04:59:48 matt Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/bus.h> 41 #include <sys/device.h> 42 #include <sys/evcnt.h> 43 #include <sys/intr.h> 44 #include <sys/cpu.h> 45 #include <sys/proc.h> 46 47 #include <arm/armreg.h> 48 #include <arm/cpufunc.h> 49 #include <arm/atomic.h> 50 51 #include <arm/cortex/gic_reg.h> 52 #include <arm/cortex/mpcore_var.h> 53 54 #define ARMGIC_SGI_IPIBASE (16 - NIPI) 55 56 static int armgic_match(device_t, cfdata_t, void *); 57 static void armgic_attach(device_t, device_t, void *); 58 59 static void armgic_set_priority(struct pic_softc *, int); 60 static void armgic_unblock_irqs(struct pic_softc *, size_t, uint32_t); 61 static void armgic_block_irqs(struct pic_softc *, size_t, uint32_t); 62 static void armgic_establish_irq(struct pic_softc *, struct intrsource *); 63 #if 0 64 static void armgic_source_name(struct pic_softc *, int, char *, size_t); 65 #endif 66 67 #ifdef MULTIPROCESSOR 68 static void armgic_cpu_init(struct pic_softc *, struct cpu_info *); 69 static void armgic_ipi_send(struct pic_softc *, const kcpuset_t *, u_long); 70 #endif 71 72 static const struct pic_ops armgic_picops = { 73 .pic_unblock_irqs = armgic_unblock_irqs, 74 .pic_block_irqs = armgic_block_irqs, 75 .pic_establish_irq = armgic_establish_irq, 76 #if 0 77 .pic_source_name = armgic_source_name, 78 #endif 79 .pic_set_priority = armgic_set_priority, 80 #ifdef MULTIPROCESSOR 81 .pic_cpu_init = armgic_cpu_init, 82 .pic_ipi_send = armgic_ipi_send, 83 #endif 84 }; 85 86 #define PICTOSOFTC(pic) ((struct armgic_softc *)(pic)) 87 88 static struct armgic_softc { 89 struct pic_softc sc_pic; 90 device_t sc_dev; 91 bus_space_tag_t sc_memt; 92 bus_space_handle_t sc_gicch; 93 bus_space_handle_t sc_gicdh; 94 size_t sc_gic_lines; 95 uint32_t sc_gic_type; 96 uint32_t sc_gic_valid_lines[1024/32]; 97 uint32_t sc_enabled_local; 98 #ifdef MULTIPROCESSOR 99 uint32_t sc_mptargets; 100 #endif 101 } armgic_softc = { 102 .sc_pic = { 103 .pic_ops = &armgic_picops, 104 .pic_name = "armgic", 105 }, 106 }; 107 108 static struct intrsource armgic_dummy_source; 109 110 __CTASSERT(NIPL == 8); 111 112 /* 113 * GIC register are always in little-endian. It is assumed the bus_space 114 * will do any endian conversion required. 115 */ 116 static inline uint32_t 117 gicc_read(struct armgic_softc *sc, bus_size_t o) 118 { 119 return bus_space_read_4(sc->sc_memt, sc->sc_gicch, o); 120 } 121 122 static inline void 123 gicc_write(struct armgic_softc *sc, bus_size_t o, uint32_t v) 124 { 125 bus_space_write_4(sc->sc_memt, sc->sc_gicch, o, v); 126 } 127 128 static inline uint32_t 129 gicd_read(struct armgic_softc *sc, bus_size_t o) 130 { 131 return bus_space_read_4(sc->sc_memt, sc->sc_gicdh, o); 132 } 133 134 static inline void 135 gicd_write(struct armgic_softc *sc, bus_size_t o, uint32_t v) 136 { 137 bus_space_write_4(sc->sc_memt, sc->sc_gicdh, o, v); 138 } 139 140 /* 141 * In the GIC prioritization scheme, lower numbers have higher priority. 142 * Only write priorities that could be non-secure. 143 */ 144 static inline uint32_t 145 armgic_ipl_to_priority(int ipl) 146 { 147 return GICC_PMR_NONSECURE 148 | ((IPL_HIGH - ipl) * GICC_PMR_NS_PRIORITIES / NIPL); 149 } 150 151 #if 0 152 static inline int 153 armgic_priority_to_ipl(uint32_t priority) 154 { 155 return IPL_HIGH 156 - (priority & ~GICC_PMR_NONSECURE) * NIPL / GICC_PMR_NS_PRIORITIES; 157 } 158 #endif 159 160 static void 161 armgic_unblock_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask) 162 { 163 struct armgic_softc * const sc = PICTOSOFTC(pic); 164 const size_t group = irq_base / 32; 165 166 if (group == 0) 167 sc->sc_enabled_local |= irq_mask; 168 169 gicd_write(sc, GICD_ISENABLERn(group), irq_mask); 170 } 171 172 static void 173 armgic_block_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask) 174 { 175 struct armgic_softc * const sc = PICTOSOFTC(pic); 176 const size_t group = irq_base / 32; 177 178 if (group == 0) 179 sc->sc_enabled_local &= ~irq_mask; 180 181 gicd_write(sc, GICD_ICENABLERn(group), irq_mask); 182 } 183 184 static void 185 armgic_set_priority(struct pic_softc *pic, int ipl) 186 { 187 struct armgic_softc * const sc = PICTOSOFTC(pic); 188 189 const uint32_t priority = armgic_ipl_to_priority(ipl); 190 gicc_write(sc, GICC_PMR, priority); 191 } 192 193 #ifdef __HAVE_PIC_FAST_SOFTINTS 194 void 195 softint_init_md(lwp_t *l, u_int level, uintptr_t *machdep_p) 196 { 197 lwp_t **lp = &l->l_cpu->ci_softlwps[level]; 198 KASSERT(*lp == NULL || *lp == l); 199 *lp = l; 200 /* 201 * Really easy. Just tell it to trigger the local CPU. 202 */ 203 *machdep_p = GICD_SGIR_TargetListFilter_Me 204 | __SHIFTIN(level, GICD_SGIR_SGIINTID); 205 } 206 207 void 208 softint_trigger(uintptr_t machdep) 209 { 210 211 gicd_write(&armgic_softc, GICD_SGIR, machdep); 212 } 213 #endif 214 215 void 216 armgic_irq_handler(void *tf) 217 { 218 struct cpu_info * const ci = curcpu(); 219 struct armgic_softc * const sc = &armgic_softc; 220 const int old_ipl = ci->ci_cpl; 221 #ifdef DIAGNOSTIC 222 const int old_mtx_count = ci->ci_mtx_count; 223 const int old_l_biglocks = ci->ci_curlwp->l_biglocks; 224 #endif 225 #ifdef DEBUG 226 size_t n = 0; 227 #endif 228 229 ci->ci_data.cpu_nintr++; 230 231 KASSERTMSG(old_ipl != IPL_HIGH, "old_ipl %d pmr %#x hppir %#x", 232 old_ipl, gicc_read(sc, GICC_PMR), gicc_read(sc, GICC_HPPIR)); 233 #if 0 234 printf("%s(enter): %s: pmr=%u hppir=%u\n", 235 __func__, ci->ci_data.cpu_name, 236 gicc_read(sc, GICC_PMR), 237 gicc_read(sc, GICC_HPPIR)); 238 #elif 0 239 printf("(%u:%d", ci->ci_index, old_ipl); 240 #endif 241 242 for (;;) { 243 uint32_t iar = gicc_read(sc, GICC_IAR); 244 uint32_t irq = __SHIFTOUT(iar, GICC_IAR_IRQ); 245 //printf(".%u", irq); 246 if (irq == GICC_IAR_IRQ_SPURIOUS) { 247 iar = gicc_read(sc, GICC_IAR); 248 irq = __SHIFTOUT(iar, GICC_IAR_IRQ); 249 if (irq == GICC_IAR_IRQ_SPURIOUS) 250 break; 251 //printf(".%u", irq); 252 } 253 254 //const uint32_t cpuid = __SHIFTOUT(iar, GICC_IAR_CPUID_MASK); 255 struct intrsource * const is = sc->sc_pic.pic_sources[irq]; 256 KASSERT(is != &armgic_dummy_source); 257 258 /* 259 * GIC has asserted IPL for us so we can just update ci_cpl. 260 * 261 * But it's not that simple. We may have already bumped ci_cpl 262 * due to a high priority interrupt and now we are about to 263 * dispatch one lower than the previous. It's possible for 264 * that previous interrupt to have deferred some interrupts 265 * so we need deal with those when lowering to the current 266 * interrupt's ipl. 267 * 268 * However, if are just raising ipl, we can just update ci_cpl. 269 */ 270 #if 0 271 const int ipl = armgic_priority_to_ipl(gicc_read(sc, GICC_RPR)); 272 KASSERTMSG(panicstr != NULL || ipl == is->is_ipl, 273 "%s: irq %d: running ipl %d != source ipl %u", 274 ci->ci_data.cpu_name, irq, ipl, is->is_ipl); 275 #else 276 const int ipl = is->is_ipl; 277 #endif 278 if (__predict_false(ipl < ci->ci_cpl)) { 279 //printf("<"); 280 pic_do_pending_ints(I32_bit, ipl, tf); 281 KASSERT(ci->ci_cpl == ipl); 282 } else { 283 KASSERTMSG(ipl > ci->ci_cpl, "ipl %d cpl %d hw-ipl %#x", 284 ipl, ci->ci_cpl, 285 gicc_read(sc, GICC_PMR)); 286 //printf(">"); 287 gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ipl)); 288 ci->ci_cpl = ipl; 289 } 290 //printf("$"); 291 cpsie(I32_bit); 292 pic_dispatch(is, tf); 293 cpsid(I32_bit); 294 gicc_write(sc, GICC_EOIR, iar); 295 #ifdef DEBUG 296 n++; 297 KDASSERTMSG(n < 5, "%s: processed too many (%zu)", 298 ci->ci_data.cpu_name, n); 299 #endif 300 } 301 302 // printf("%s(%p): exit (%zu dispatched)\n", __func__, tf, n); 303 /* 304 * Now handle any pending ints. 305 */ 306 //printf("!"); 307 KASSERT(old_ipl != IPL_HIGH); 308 pic_do_pending_ints(I32_bit, old_ipl, tf); 309 KASSERTMSG(ci->ci_cpl == old_ipl, "ci_cpl %d old_ipl %d", ci->ci_cpl, old_ipl); 310 KASSERT(old_mtx_count == ci->ci_mtx_count); 311 KASSERT(old_l_biglocks == ci->ci_curlwp->l_biglocks); 312 #if 0 313 printf("%s(exit): %s(%d): pmr=%u hppir=%u\n", 314 __func__, ci->ci_data.cpu_name, ci->ci_cpl, 315 gicc_read(sc, GICC_PMR), 316 gicc_read(sc, GICC_HPPIR)); 317 #elif 0 318 printf("->%#x)", ((struct trapframe *)tf)->tf_pc); 319 #endif 320 } 321 322 void 323 armgic_establish_irq(struct pic_softc *pic, struct intrsource *is) 324 { 325 struct armgic_softc * const sc = PICTOSOFTC(pic); 326 const size_t group = is->is_irq / 32; 327 const u_int irq = is->is_irq & 31; 328 const u_int byte_shift = 8 * (irq & 3); 329 const u_int twopair_shift = 2 * (irq & 15); 330 331 KASSERTMSG(sc->sc_gic_valid_lines[group] & __BIT(irq), 332 "irq %u: not valid (group[%zu]=0x%08x [0x%08x])", 333 is->is_irq, group, sc->sc_gic_valid_lines[group], 334 (uint32_t)__BIT(irq)); 335 336 KASSERTMSG(is->is_type == IST_LEVEL || is->is_type == IST_EDGE, 337 "irq %u: type %u unsupported", is->is_irq, is->is_type); 338 339 const bus_size_t targets_reg = GICD_ITARGETSRn(is->is_irq / 4); 340 const bus_size_t cfg_reg = GICD_ICFGRn(is->is_irq / 16); 341 uint32_t targets = gicd_read(sc, targets_reg); 342 uint32_t cfg = gicd_read(sc, cfg_reg); 343 344 if (group > 0) { 345 /* 346 * There are 4 irqs per TARGETS register. For now bind 347 * to the primary cpu. 348 */ 349 targets &= ~(0xff << byte_shift); 350 #if 0 351 #ifdef MULTIPROCESSOR 352 if (is->is_mpsafe) { 353 targets |= sc->sc_mptargets << byte_shift; 354 } else 355 #endif 356 #endif 357 targets |= 1 << byte_shift; 358 gicd_write(sc, targets_reg, targets); 359 360 /* 361 * There are 16 irqs per CFG register. 10=EDGE 00=LEVEL 362 */ 363 uint32_t new_cfg = cfg; 364 uint32_t old_cfg = (cfg >> twopair_shift) & 3; 365 if (is->is_type == IST_LEVEL && (old_cfg & 2) != 0) { 366 new_cfg &= ~(3 << twopair_shift); 367 } else if (is->is_type == IST_EDGE && (old_cfg & 2) == 0) { 368 new_cfg |= 2 << twopair_shift; 369 } 370 if (new_cfg != cfg) { 371 gicd_write(sc, cfg_reg, new_cfg); 372 #if 0 373 printf("%s: irq %u: cfg changed from %#x to %#x\n", 374 pic->pic_name, is->is_irq, cfg, new_cfg); 375 #endif 376 } 377 #ifdef MULTIPROCESSOR 378 } else { 379 /* 380 * All group 0 interrupts are per processor and MPSAFE by 381 * default. 382 */ 383 is->is_mpsafe = true; 384 #endif 385 } 386 387 /* 388 * There are 4 irqs per PRIORITY register. Map the IPL 389 * to GIC priority. 390 */ 391 const bus_size_t priority_reg = GICD_IPRIORITYRn(is->is_irq / 4); 392 uint32_t priority = gicd_read(sc, priority_reg); 393 priority &= ~(0xff << byte_shift); 394 priority |= armgic_ipl_to_priority(is->is_ipl) << byte_shift; 395 gicd_write(sc, priority_reg, priority); 396 397 #if 0 398 printf("%s: irq %u: target %#x cfg %u priority %#x (%u)\n", 399 pic->pic_name, is->is_irq, (targets >> byte_shift) & 0xff, 400 (cfg >> twopair_shift) & 3, (priority >> byte_shift) & 0xff, 401 is->is_ipl); 402 #endif 403 } 404 405 #ifdef MULTIPROCESSOR 406 static void 407 armgic_cpu_init_priorities(struct armgic_softc *sc) 408 { 409 uint32_t enabled = sc->sc_enabled_local; 410 for (size_t i = 0; i < 32; i += 4, enabled >>= 4) { 411 /* 412 * If there are no enabled interrupts for the priority register, 413 * don't bother changing it. 414 */ 415 if ((enabled & 0x0f) == 0) 416 continue; 417 /* 418 * Since priorities are in 3210 order, it' 419 */ 420 const bus_size_t priority_reg = GICD_IPRIORITYRn(i / 4); 421 uint32_t priority = gicd_read(sc, priority_reg); 422 uint32_t byte_mask = 0xff; 423 size_t byte_shift = 0; 424 for (size_t j = 0; j < 4; j++, byte_mask <<= 8, byte_shift += 8) { 425 struct intrsource * const is = sc->sc_pic.pic_sources[i+j]; 426 if (is == NULL || is == &armgic_dummy_source) 427 continue; 428 priority &= ~byte_mask; 429 priority |= armgic_ipl_to_priority(is->is_ipl) << byte_shift; 430 } 431 gicd_write(sc, priority_reg, priority); 432 } 433 } 434 435 static void 436 armgic_cpu_init_targets(struct armgic_softc *sc) 437 { 438 /* 439 * Update the mpsafe targets 440 */ 441 for (size_t irq = 32; irq < sc->sc_pic.pic_maxsources; irq++) { 442 struct intrsource * const is = sc->sc_pic.pic_sources[irq]; 443 const bus_size_t targets_reg = GICD_ITARGETSRn(irq / 4); 444 if (is != NULL && is->is_mpsafe) { 445 const u_int byte_shift = 8 * (irq & 3); 446 uint32_t targets = gicd_read(sc, targets_reg); 447 targets |= sc->sc_mptargets << byte_shift; 448 gicd_write(sc, targets_reg, targets); 449 } 450 } 451 } 452 453 void 454 armgic_cpu_init(struct pic_softc *pic, struct cpu_info *ci) 455 { 456 struct armgic_softc * const sc = PICTOSOFTC(pic); 457 sc->sc_mptargets |= 1 << cpu_index(ci); 458 KASSERTMSG(ci->ci_cpl == IPL_HIGH, "ipl %d not IPL_HIGH", ci->ci_cpl); 459 if (!CPU_IS_PRIMARY(ci)) { 460 if (sc->sc_mptargets != 1) { 461 armgic_cpu_init_targets(sc); 462 } 463 if (sc->sc_enabled_local) { 464 armgic_cpu_init_priorities(sc); 465 gicd_write(sc, GICD_ISENABLERn(0), 466 sc->sc_enabled_local); 467 } 468 } 469 gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ci->ci_cpl)); // set PMR 470 gicc_write(sc, GICC_CTRL, GICC_CTRL_V1_Enable); // enable interrupt 471 cpsie(I32_bit); // allow IRQ exceptions 472 } 473 474 void 475 armgic_ipi_send(struct pic_softc *pic, const kcpuset_t *kcp, u_long ipi) 476 { 477 struct armgic_softc * const sc = PICTOSOFTC(pic); 478 479 #if 0 480 if (ipi == IPI_NOP) { 481 __asm __volatile("sev"); 482 return; 483 } 484 #endif 485 486 uint32_t sgir = __SHIFTIN(ARMGIC_SGI_IPIBASE + ipi, GICD_SGIR_SGIINTID); 487 if (kcp != NULL) { 488 uint32_t targets; 489 kcpuset_export_u32(kcp, &targets, sizeof(targets)); 490 sgir |= __SHIFTIN(targets, GICD_SGIR_TargetList); 491 sgir |= GICD_SGIR_TargetListFilter_List; 492 } else { 493 if (ncpu == 1) 494 return; 495 sgir |= GICD_SGIR_TargetListFilter_NotMe; 496 } 497 498 //printf("%s: %s: %#x", __func__, curcpu()->ci_data.cpu_name, sgir); 499 gicd_write(sc, GICD_SGIR, sgir); 500 //printf("\n"); 501 } 502 #endif 503 504 int 505 armgic_match(device_t parent, cfdata_t cf, void *aux) 506 { 507 struct mpcore_attach_args * const mpcaa = aux; 508 509 if (strcmp(cf->cf_name, mpcaa->mpcaa_name) != 0) 510 return 0; 511 if (!CPU_ID_CORTEX_P(cputype) || CPU_ID_CORTEX_A8_P(cputype)) 512 return 0; 513 514 return 1; 515 } 516 517 void 518 armgic_attach(device_t parent, device_t self, void *aux) 519 { 520 struct armgic_softc * const sc = &armgic_softc; 521 struct mpcore_attach_args * const mpcaa = aux; 522 523 sc->sc_dev = self; 524 self->dv_private = sc; 525 526 sc->sc_memt = mpcaa->mpcaa_memt; /* provided for us */ 527 bus_space_subregion(sc->sc_memt, mpcaa->mpcaa_memh, mpcaa->mpcaa_off1, 528 4096, &sc->sc_gicdh); 529 bus_space_subregion(sc->sc_memt, mpcaa->mpcaa_memh, mpcaa->mpcaa_off2, 530 4096, &sc->sc_gicch); 531 532 sc->sc_gic_type = gicd_read(sc, GICD_TYPER); 533 sc->sc_pic.pic_maxsources = GICD_TYPER_LINES(sc->sc_gic_type); 534 535 gicc_write(sc, GICC_CTRL, 0); /* disable all interrupts */ 536 gicd_write(sc, GICD_CTRL, 0); /* disable all interrupts */ 537 538 gicc_write(sc, GICC_PMR, 0xff); 539 uint32_t pmr = gicc_read(sc, GICC_PMR); 540 u_int priorities = 1 << popcount32(pmr); 541 542 /* 543 * Let's find out how many real sources we have. 544 */ 545 for (size_t i = 0, group = 0; 546 i < sc->sc_pic.pic_maxsources; 547 i += 32, group++) { 548 /* 549 * To figure what sources are real, one enables all interrupts 550 * and then reads back the enable mask so which ones really 551 * got enabled. 552 */ 553 gicd_write(sc, GICD_ISENABLERn(group), 0xffffffff); 554 uint32_t valid = gicd_read(sc, GICD_ISENABLERn(group)); 555 556 /* 557 * Now disable (clear enable) them again. 558 */ 559 gicd_write(sc, GICD_ICENABLERn(group), valid); 560 561 /* 562 * Count how many are valid. 563 */ 564 sc->sc_gic_lines += popcount32(valid); 565 sc->sc_gic_valid_lines[group] = valid; 566 } 567 568 aprint_normal(": Generic Interrupt Controller, " 569 "%zu sources (%zu valid)\n", 570 sc->sc_pic.pic_maxsources, sc->sc_gic_lines); 571 572 #ifdef MULTIPROCESSOR 573 sc->sc_pic.pic_cpus = kcpuset_running; 574 #endif 575 pic_add(&sc->sc_pic, 0); 576 577 /* 578 * Force the GICD to IPL_HIGH and then enable interrupts. 579 */ 580 struct cpu_info * const ci = curcpu(); 581 KASSERTMSG(ci->ci_cpl == IPL_HIGH, "ipl %d not IPL_HIGH", ci->ci_cpl); 582 armgic_set_priority(&sc->sc_pic, ci->ci_cpl); // set PMR 583 gicd_write(sc, GICD_CTRL, GICD_CTRL_Enable); // enable Distributer 584 gicc_write(sc, GICC_CTRL, GICC_CTRL_V1_Enable); // enable CPU interrupts 585 cpsie(I32_bit); // allow interrupt exceptions 586 587 /* 588 * For each line that isn't valid, we set the intrsource for it to 589 * point at a dummy source so that pic_intr_establish will fail for it. 590 */ 591 for (size_t i = 0, group = 0; 592 i < sc->sc_pic.pic_maxsources; 593 i += 32, group++) { 594 uint32_t invalid = ~sc->sc_gic_valid_lines[group]; 595 for (size_t j = 0; invalid && j < 32; j++, invalid >>= 1) { 596 if (invalid & 1) { 597 sc->sc_pic.pic_sources[i + j] = 598 &armgic_dummy_source; 599 } 600 } 601 } 602 #ifdef __HAVE_PIC_FAST_SOFTINTS 603 intr_establish(SOFTINT_BIO, IPL_SOFTBIO, IST_MPSAFE | IST_EDGE, 604 pic_handle_softint, (void *)SOFTINT_BIO); 605 intr_establish(SOFTINT_CLOCK, IPL_SOFTCLOCK, IST_MPSAFE | IST_EDGE, 606 pic_handle_softint, (void *)SOFTINT_CLOCK); 607 intr_establish(SOFTINT_NET, IPL_SOFTNET, IST_MPSAFE | IST_EDGE, 608 pic_handle_softint, (void *)SOFTINT_NET); 609 intr_establish(SOFTINT_SERIAL, IPL_SOFTSERIAL, IST_MPSAFE | IST_EDGE, 610 pic_handle_softint, (void *)SOFTINT_SERIAL); 611 #endif 612 #ifdef MULTIPROCESSOR 613 intr_establish(ARMGIC_SGI_IPIBASE + IPI_AST, IPL_VM, 614 IST_MPSAFE | IST_EDGE, pic_ipi_ast, (void *)-1); 615 intr_establish(ARMGIC_SGI_IPIBASE + IPI_XCALL, IPL_HIGH, 616 IST_MPSAFE | IST_EDGE, pic_ipi_xcall, (void *)-1); 617 intr_establish(ARMGIC_SGI_IPIBASE + IPI_GENERIC, IPL_HIGH, 618 IST_MPSAFE | IST_EDGE, pic_ipi_generic, (void *)-1); 619 intr_establish(ARMGIC_SGI_IPIBASE + IPI_NOP, IPL_VM, 620 IST_MPSAFE | IST_EDGE, pic_ipi_nop, (void *)-1); 621 intr_establish(ARMGIC_SGI_IPIBASE + IPI_SHOOTDOWN, IPL_SCHED, 622 IST_MPSAFE | IST_EDGE, pic_ipi_shootdown, (void *)-1); 623 #ifdef DDB 624 intr_establish(ARMGIC_SGI_IPIBASE + IPI_DDB, IPL_HIGH, 625 IST_MPSAFE | IST_EDGE, pic_ipi_ddb, NULL); 626 #endif 627 #ifdef __HAVE_PREEMPTION 628 intr_establish(ARMGIC_SGI_IPIBASE + IPI_KPREEMPT, IPL_VM, 629 IST_MPSAFE | IST_EDGE, pic_ipi_kpreempt, (void *)-1); 630 #endif 631 armgic_cpu_init(&sc->sc_pic, curcpu()); 632 #endif 633 634 const u_int ppis = popcount32(sc->sc_gic_valid_lines[0] >> 16); 635 const u_int sgis = popcount32(sc->sc_gic_valid_lines[0] & 0xffff); 636 aprint_normal_dev(sc->sc_dev, "%u Priorities, %zu SPIs, %u PPIs, %u SGIs\n", 637 priorities, sc->sc_gic_lines - ppis - sgis, ppis, sgis); 638 } 639 640 CFATTACH_DECL_NEW(armgic, 0, 641 armgic_match, armgic_attach, NULL, NULL); 642