1 /* $NetBSD: gic.c,v 1.31 2017/07/14 06:33:26 skrll Exp $ */ 2 /*- 3 * Copyright (c) 2012 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas of 3am Software Foundry. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "opt_ddb.h" 32 #include "opt_multiprocessor.h" 33 34 #define _INTR_PRIVATE 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.31 2017/07/14 06:33:26 skrll Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/bus.h> 41 #include <sys/cpu.h> 42 #include <sys/device.h> 43 #include <sys/evcnt.h> 44 #include <sys/intr.h> 45 #include <sys/proc.h> 46 47 #include <arm/armreg.h> 48 #include <arm/cpufunc.h> 49 #include <arm/atomic.h> 50 51 #include <arm/cortex/gic_reg.h> 52 #include <arm/cortex/mpcore_var.h> 53 54 void armgic_irq_handler(void *); 55 56 #define ARMGIC_SGI_IPIBASE 0 57 58 /* 59 * SGIs 8-16 are reserved for use by ARM Trusted Firmware. 60 */ 61 __CTASSERT(ARMGIC_SGI_IPIBASE + NIPI <= 8); 62 63 static int armgic_match(device_t, cfdata_t, void *); 64 static void armgic_attach(device_t, device_t, void *); 65 66 static void armgic_set_priority(struct pic_softc *, int); 67 static void armgic_unblock_irqs(struct pic_softc *, size_t, uint32_t); 68 static void armgic_block_irqs(struct pic_softc *, size_t, uint32_t); 69 static void armgic_establish_irq(struct pic_softc *, struct intrsource *); 70 #if 0 71 static void armgic_source_name(struct pic_softc *, int, char *, size_t); 72 #endif 73 74 #ifdef MULTIPROCESSOR 75 static void armgic_cpu_init(struct pic_softc *, struct cpu_info *); 76 static void armgic_ipi_send(struct pic_softc *, const kcpuset_t *, u_long); 77 #endif 78 79 static const struct pic_ops armgic_picops = { 80 .pic_unblock_irqs = armgic_unblock_irqs, 81 .pic_block_irqs = armgic_block_irqs, 82 .pic_establish_irq = armgic_establish_irq, 83 #if 0 84 .pic_source_name = armgic_source_name, 85 #endif 86 .pic_set_priority = armgic_set_priority, 87 #ifdef MULTIPROCESSOR 88 .pic_cpu_init = armgic_cpu_init, 89 .pic_ipi_send = armgic_ipi_send, 90 #endif 91 }; 92 93 #define PICTOSOFTC(pic) ((struct armgic_softc *)(pic)) 94 95 static struct armgic_softc { 96 struct pic_softc sc_pic; 97 device_t sc_dev; 98 bus_space_tag_t sc_memt; 99 bus_space_handle_t sc_gicch; 100 bus_space_handle_t sc_gicdh; 101 size_t sc_gic_lines; 102 uint32_t sc_gic_type; 103 uint32_t sc_gic_valid_lines[1024/32]; 104 uint32_t sc_enabled_local; 105 #ifdef MULTIPROCESSOR 106 uint32_t sc_mptargets; 107 #endif 108 uint32_t sc_bptargets; 109 } armgic_softc = { 110 .sc_pic = { 111 .pic_ops = &armgic_picops, 112 .pic_name = "armgic", 113 }, 114 }; 115 116 static struct intrsource armgic_dummy_source; 117 118 __CTASSERT(NIPL == 8); 119 120 /* 121 * GIC register are always in little-endian. It is assumed the bus_space 122 * will do any endian conversion required. 123 */ 124 static inline uint32_t 125 gicc_read(struct armgic_softc *sc, bus_size_t o) 126 { 127 return bus_space_read_4(sc->sc_memt, sc->sc_gicch, o); 128 } 129 130 static inline void 131 gicc_write(struct armgic_softc *sc, bus_size_t o, uint32_t v) 132 { 133 bus_space_write_4(sc->sc_memt, sc->sc_gicch, o, v); 134 } 135 136 static inline uint32_t 137 gicd_read(struct armgic_softc *sc, bus_size_t o) 138 { 139 return bus_space_read_4(sc->sc_memt, sc->sc_gicdh, o); 140 } 141 142 static inline void 143 gicd_write(struct armgic_softc *sc, bus_size_t o, uint32_t v) 144 { 145 bus_space_write_4(sc->sc_memt, sc->sc_gicdh, o, v); 146 } 147 148 static uint32_t 149 gicd_find_targets(struct armgic_softc *sc) 150 { 151 uint32_t targets = 0; 152 153 /* 154 * GICD_ITARGETSR0 through 7 are read-only, and each field returns 155 * a value that corresponds only to the processor reading the 156 * register. Use this to determine the current processor's 157 * CPU interface number. 158 */ 159 for (int i = 0; i < 8; i++) { 160 targets = gicd_read(sc, GICD_ITARGETSRn(i)); 161 if (targets != 0) 162 break; 163 } 164 targets |= (targets >> 16); 165 targets |= (targets >> 8); 166 targets &= 0xff; 167 168 return targets ? targets : 1; 169 } 170 171 /* 172 * In the GIC prioritization scheme, lower numbers have higher priority. 173 * Only write priorities that could be non-secure. 174 */ 175 static inline uint32_t 176 armgic_ipl_to_priority(int ipl) 177 { 178 return GICC_PMR_NONSECURE 179 | ((IPL_HIGH - ipl) * GICC_PMR_NS_PRIORITIES / NIPL); 180 } 181 182 #if 0 183 static inline int 184 armgic_priority_to_ipl(uint32_t priority) 185 { 186 return IPL_HIGH 187 - (priority & ~GICC_PMR_NONSECURE) * NIPL / GICC_PMR_NS_PRIORITIES; 188 } 189 #endif 190 191 static void 192 armgic_unblock_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask) 193 { 194 struct armgic_softc * const sc = PICTOSOFTC(pic); 195 const size_t group = irq_base / 32; 196 197 if (group == 0) 198 sc->sc_enabled_local |= irq_mask; 199 200 gicd_write(sc, GICD_ISENABLERn(group), irq_mask); 201 } 202 203 static void 204 armgic_block_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask) 205 { 206 struct armgic_softc * const sc = PICTOSOFTC(pic); 207 const size_t group = irq_base / 32; 208 209 if (group == 0) 210 sc->sc_enabled_local &= ~irq_mask; 211 212 gicd_write(sc, GICD_ICENABLERn(group), irq_mask); 213 } 214 215 static void 216 armgic_set_priority(struct pic_softc *pic, int ipl) 217 { 218 struct armgic_softc * const sc = PICTOSOFTC(pic); 219 220 const uint32_t priority = armgic_ipl_to_priority(ipl); 221 gicc_write(sc, GICC_PMR, priority); 222 } 223 224 #ifdef __HAVE_PIC_FAST_SOFTINTS 225 void 226 softint_init_md(lwp_t *l, u_int level, uintptr_t *machdep_p) 227 { 228 lwp_t **lp = &l->l_cpu->ci_softlwps[level]; 229 KASSERT(*lp == NULL || *lp == l); 230 *lp = l; 231 /* 232 * Really easy. Just tell it to trigger the local CPU. 233 */ 234 *machdep_p = GICD_SGIR_TargetListFilter_Me 235 | __SHIFTIN(level, GICD_SGIR_SGIINTID); 236 } 237 238 void 239 softint_trigger(uintptr_t machdep) 240 { 241 242 gicd_write(&armgic_softc, GICD_SGIR, machdep); 243 } 244 #endif 245 246 void 247 armgic_irq_handler(void *tf) 248 { 249 struct cpu_info * const ci = curcpu(); 250 struct armgic_softc * const sc = &armgic_softc; 251 const int old_ipl = ci->ci_cpl; 252 #ifdef DIAGNOSTIC 253 const int old_mtx_count = ci->ci_mtx_count; 254 const int old_l_biglocks = ci->ci_curlwp->l_biglocks; 255 #endif 256 #ifdef DEBUG 257 size_t n = 0; 258 #endif 259 260 ci->ci_data.cpu_nintr++; 261 262 KASSERTMSG(old_ipl != IPL_HIGH, "old_ipl %d pmr %#x hppir %#x", 263 old_ipl, gicc_read(sc, GICC_PMR), gicc_read(sc, GICC_HPPIR)); 264 265 for (;;) { 266 uint32_t iar = gicc_read(sc, GICC_IAR); 267 uint32_t irq = __SHIFTOUT(iar, GICC_IAR_IRQ); 268 269 if (irq == GICC_IAR_IRQ_SPURIOUS || 270 irq == GICC_IAR_IRQ_SSPURIOUS) { 271 iar = gicc_read(sc, GICC_IAR); 272 irq = __SHIFTOUT(iar, GICC_IAR_IRQ); 273 if (irq == GICC_IAR_IRQ_SPURIOUS) 274 break; 275 if (irq == GICC_IAR_IRQ_SSPURIOUS) { 276 break; 277 } 278 } 279 280 //const uint32_t cpuid = __SHIFTOUT(iar, GICC_IAR_CPUID_MASK); 281 struct intrsource * const is = sc->sc_pic.pic_sources[irq]; 282 KASSERT(is != &armgic_dummy_source); 283 284 /* 285 * GIC has asserted IPL for us so we can just update ci_cpl. 286 * 287 * But it's not that simple. We may have already bumped ci_cpl 288 * due to a high priority interrupt and now we are about to 289 * dispatch one lower than the previous. It's possible for 290 * that previous interrupt to have deferred some interrupts 291 * so we need deal with those when lowering to the current 292 * interrupt's ipl. 293 * 294 * However, if are just raising ipl, we can just update ci_cpl. 295 */ 296 const int ipl = is->is_ipl; 297 if (__predict_false(ipl < ci->ci_cpl)) { 298 pic_do_pending_ints(I32_bit, ipl, tf); 299 KASSERT(ci->ci_cpl == ipl); 300 } else { 301 KASSERTMSG(ipl > ci->ci_cpl, "ipl %d cpl %d hw-ipl %#x", 302 ipl, ci->ci_cpl, 303 gicc_read(sc, GICC_PMR)); 304 gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ipl)); 305 ci->ci_cpl = ipl; 306 } 307 cpsie(I32_bit); 308 pic_dispatch(is, tf); 309 cpsid(I32_bit); 310 gicc_write(sc, GICC_EOIR, iar); 311 #ifdef DEBUG 312 n++; 313 KDASSERTMSG(n < 5, "%s: processed too many (%zu)", 314 ci->ci_data.cpu_name, n); 315 #endif 316 } 317 318 /* 319 * Now handle any pending ints. 320 */ 321 KASSERT(old_ipl != IPL_HIGH); 322 pic_do_pending_ints(I32_bit, old_ipl, tf); 323 KASSERTMSG(ci->ci_cpl == old_ipl, "ci_cpl %d old_ipl %d", ci->ci_cpl, old_ipl); 324 KASSERT(old_mtx_count == ci->ci_mtx_count); 325 KASSERT(old_l_biglocks == ci->ci_curlwp->l_biglocks); 326 } 327 328 void 329 armgic_establish_irq(struct pic_softc *pic, struct intrsource *is) 330 { 331 struct armgic_softc * const sc = PICTOSOFTC(pic); 332 const size_t group = is->is_irq / 32; 333 const u_int irq = is->is_irq & 31; 334 const u_int byte_shift = 8 * (irq & 3); 335 const u_int twopair_shift = 2 * (irq & 15); 336 337 KASSERTMSG(sc->sc_gic_valid_lines[group] & __BIT(irq), 338 "irq %u: not valid (group[%zu]=0x%08x [0x%08x])", 339 is->is_irq, group, sc->sc_gic_valid_lines[group], 340 (uint32_t)__BIT(irq)); 341 342 KASSERTMSG(is->is_type == IST_LEVEL || is->is_type == IST_EDGE, 343 "irq %u: type %u unsupported", is->is_irq, is->is_type); 344 345 const bus_size_t targets_reg = GICD_ITARGETSRn(is->is_irq / 4); 346 const bus_size_t cfg_reg = GICD_ICFGRn(is->is_irq / 16); 347 uint32_t targets = gicd_read(sc, targets_reg); 348 uint32_t cfg = gicd_read(sc, cfg_reg); 349 350 if (group > 0) { 351 /* 352 * There are 4 irqs per TARGETS register. For now bind 353 * to the primary cpu. 354 */ 355 targets &= ~(0xff << byte_shift); 356 #if 0 357 #ifdef MULTIPROCESSOR 358 if (is->is_mpsafe) { 359 targets |= sc->sc_mptargets << byte_shift; 360 } else 361 #endif 362 #endif 363 targets |= sc->sc_bptargets << byte_shift; 364 gicd_write(sc, targets_reg, targets); 365 366 /* 367 * There are 16 irqs per CFG register. 10=EDGE 00=LEVEL 368 */ 369 uint32_t new_cfg = cfg; 370 uint32_t old_cfg = (cfg >> twopair_shift) & 3; 371 if (is->is_type == IST_LEVEL && (old_cfg & 2) != 0) { 372 new_cfg &= ~(3 << twopair_shift); 373 } else if (is->is_type == IST_EDGE && (old_cfg & 2) == 0) { 374 new_cfg |= 2 << twopair_shift; 375 } 376 if (new_cfg != cfg) { 377 gicd_write(sc, cfg_reg, new_cfg); 378 } 379 #ifdef MULTIPROCESSOR 380 } else { 381 /* 382 * All group 0 interrupts are per processor and MPSAFE by 383 * default. 384 */ 385 is->is_mpsafe = true; 386 #endif 387 } 388 389 /* 390 * There are 4 irqs per PRIORITY register. Map the IPL 391 * to GIC priority. 392 */ 393 const bus_size_t priority_reg = GICD_IPRIORITYRn(is->is_irq / 4); 394 uint32_t priority = gicd_read(sc, priority_reg); 395 priority &= ~(0xff << byte_shift); 396 priority |= armgic_ipl_to_priority(is->is_ipl) << byte_shift; 397 gicd_write(sc, priority_reg, priority); 398 } 399 400 #ifdef MULTIPROCESSOR 401 static void 402 armgic_cpu_init_priorities(struct armgic_softc *sc) 403 { 404 /* Set lowest priority, i.e. disable interrupts */ 405 for (size_t i = 0; i < 32; i += 4) { 406 const bus_size_t priority_reg = GICD_IPRIORITYRn(i / 4); 407 gicd_write(sc, priority_reg, ~0); 408 } 409 } 410 411 static void 412 armgic_cpu_update_priorities(struct armgic_softc *sc) 413 { 414 uint32_t enabled = sc->sc_enabled_local; 415 for (size_t i = 0; i < 32; i += 4, enabled >>= 4) { 416 const bus_size_t priority_reg = GICD_IPRIORITYRn(i / 4); 417 uint32_t priority = gicd_read(sc, priority_reg); 418 uint32_t byte_mask = 0xff; 419 size_t byte_shift = 0; 420 for (size_t j = 0; j < 4; j++, byte_mask <<= 8, byte_shift += 8) { 421 struct intrsource * const is = sc->sc_pic.pic_sources[i+j]; 422 priority |= byte_mask; 423 if (is == NULL || is == &armgic_dummy_source) 424 continue; 425 priority &= ~byte_mask; 426 priority |= armgic_ipl_to_priority(is->is_ipl) << byte_shift; 427 } 428 gicd_write(sc, priority_reg, priority); 429 } 430 } 431 432 static void 433 armgic_cpu_init_targets(struct armgic_softc *sc) 434 { 435 /* 436 * Update the mpsafe targets 437 */ 438 for (size_t irq = 32; irq < sc->sc_pic.pic_maxsources; irq++) { 439 struct intrsource * const is = sc->sc_pic.pic_sources[irq]; 440 const bus_size_t targets_reg = GICD_ITARGETSRn(irq / 4); 441 if (is != NULL && is->is_mpsafe) { 442 const u_int byte_shift = 8 * (irq & 3); 443 uint32_t targets = gicd_read(sc, targets_reg); 444 targets |= sc->sc_mptargets << byte_shift; 445 gicd_write(sc, targets_reg, targets); 446 } 447 } 448 } 449 450 void 451 armgic_cpu_init(struct pic_softc *pic, struct cpu_info *ci) 452 { 453 struct armgic_softc * const sc = PICTOSOFTC(pic); 454 sc->sc_mptargets |= gicd_find_targets(sc); 455 KASSERTMSG(ci->ci_cpl == IPL_HIGH, "ipl %d not IPL_HIGH", ci->ci_cpl); 456 armgic_cpu_init_priorities(sc); 457 if (!CPU_IS_PRIMARY(ci)) { 458 if (popcount(sc->sc_mptargets) != 1) { 459 armgic_cpu_init_targets(sc); 460 } 461 if (sc->sc_enabled_local) { 462 armgic_cpu_update_priorities(sc); 463 gicd_write(sc, GICD_ISENABLERn(0), 464 sc->sc_enabled_local); 465 } 466 } 467 gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ci->ci_cpl)); // set PMR 468 gicc_write(sc, GICC_CTRL, GICC_CTRL_V1_Enable); // enable interrupt 469 cpsie(I32_bit); // allow IRQ exceptions 470 } 471 472 void 473 armgic_ipi_send(struct pic_softc *pic, const kcpuset_t *kcp, u_long ipi) 474 { 475 struct armgic_softc * const sc = PICTOSOFTC(pic); 476 477 #if 0 478 if (ipi == IPI_NOP) { 479 __asm __volatile("sev"); 480 return; 481 } 482 #endif 483 484 uint32_t sgir = __SHIFTIN(ARMGIC_SGI_IPIBASE + ipi, GICD_SGIR_SGIINTID); 485 if (kcp != NULL) { 486 uint32_t targets; 487 kcpuset_export_u32(kcp, &targets, sizeof(targets)); 488 sgir |= __SHIFTIN(targets, GICD_SGIR_TargetList); 489 sgir |= GICD_SGIR_TargetListFilter_List; 490 } else { 491 if (ncpu == 1) 492 return; 493 sgir |= GICD_SGIR_TargetListFilter_NotMe; 494 } 495 496 gicd_write(sc, GICD_SGIR, sgir); 497 } 498 #endif 499 500 int 501 armgic_match(device_t parent, cfdata_t cf, void *aux) 502 { 503 struct mpcore_attach_args * const mpcaa = aux; 504 505 if (strcmp(cf->cf_name, mpcaa->mpcaa_name) != 0) 506 return 0; 507 if (!CPU_ID_CORTEX_P(cputype) || CPU_ID_CORTEX_A8_P(cputype)) 508 return 0; 509 510 return 1; 511 } 512 513 void 514 armgic_attach(device_t parent, device_t self, void *aux) 515 { 516 struct armgic_softc * const sc = &armgic_softc; 517 struct mpcore_attach_args * const mpcaa = aux; 518 519 sc->sc_dev = self; 520 self->dv_private = sc; 521 522 sc->sc_memt = mpcaa->mpcaa_memt; /* provided for us */ 523 bus_space_subregion(sc->sc_memt, mpcaa->mpcaa_memh, mpcaa->mpcaa_off1, 524 4096, &sc->sc_gicdh); 525 bus_space_subregion(sc->sc_memt, mpcaa->mpcaa_memh, mpcaa->mpcaa_off2, 526 4096, &sc->sc_gicch); 527 528 sc->sc_gic_type = gicd_read(sc, GICD_TYPER); 529 sc->sc_pic.pic_maxsources = GICD_TYPER_LINES(sc->sc_gic_type); 530 531 gicc_write(sc, GICC_CTRL, 0); /* disable all interrupts */ 532 gicd_write(sc, GICD_CTRL, 0); /* disable all interrupts */ 533 534 gicc_write(sc, GICC_PMR, 0xff); 535 uint32_t pmr = gicc_read(sc, GICC_PMR); 536 u_int priorities = 1 << popcount32(pmr); 537 538 const uint32_t iidr = gicc_read(sc, GICC_IIDR); 539 const int iidr_prod = __SHIFTOUT(iidr, GICC_IIDR_ProductID); 540 const int iidr_arch = __SHIFTOUT(iidr, GICC_IIDR_ArchVersion); 541 const int iidr_rev = __SHIFTOUT(iidr, GICC_IIDR_Revision); 542 const int iidr_imp = __SHIFTOUT(iidr, GICC_IIDR_Implementer); 543 544 /* 545 * Find the boot processor's CPU interface number. 546 */ 547 sc->sc_bptargets = gicd_find_targets(sc); 548 549 /* 550 * Let's find out how many real sources we have. 551 */ 552 for (size_t i = 0, group = 0; 553 i < sc->sc_pic.pic_maxsources; 554 i += 32, group++) { 555 /* 556 * To figure what sources are real, one enables all interrupts 557 * and then reads back the enable mask so which ones really 558 * got enabled. 559 */ 560 gicd_write(sc, GICD_ISENABLERn(group), 0xffffffff); 561 uint32_t valid = gicd_read(sc, GICD_ISENABLERn(group)); 562 563 /* 564 * Now disable (clear enable) them again. 565 */ 566 gicd_write(sc, GICD_ICENABLERn(group), valid); 567 568 /* 569 * Count how many are valid. 570 */ 571 sc->sc_gic_lines += popcount32(valid); 572 sc->sc_gic_valid_lines[group] = valid; 573 } 574 575 aprint_normal(": Generic Interrupt Controller, " 576 "%zu sources (%zu valid)\n", 577 sc->sc_pic.pic_maxsources, sc->sc_gic_lines); 578 aprint_debug_dev(sc->sc_dev, "Architecture version %d" 579 " (0x%x:%d rev %d)\n", iidr_arch, iidr_imp, iidr_prod, 580 iidr_rev); 581 582 #ifdef MULTIPROCESSOR 583 sc->sc_pic.pic_cpus = kcpuset_running; 584 #endif 585 pic_add(&sc->sc_pic, 0); 586 587 /* 588 * Force the GICD to IPL_HIGH and then enable interrupts. 589 */ 590 struct cpu_info * const ci = curcpu(); 591 KASSERTMSG(ci->ci_cpl == IPL_HIGH, "ipl %d not IPL_HIGH", ci->ci_cpl); 592 armgic_set_priority(&sc->sc_pic, ci->ci_cpl); // set PMR 593 gicd_write(sc, GICD_CTRL, GICD_CTRL_Enable); // enable Distributer 594 gicc_write(sc, GICC_CTRL, GICC_CTRL_V1_Enable); // enable CPU interrupts 595 cpsie(I32_bit); // allow interrupt exceptions 596 597 /* 598 * For each line that isn't valid, we set the intrsource for it to 599 * point at a dummy source so that pic_intr_establish will fail for it. 600 */ 601 for (size_t i = 0, group = 0; 602 i < sc->sc_pic.pic_maxsources; 603 i += 32, group++) { 604 uint32_t invalid = ~sc->sc_gic_valid_lines[group]; 605 for (size_t j = 0; invalid && j < 32; j++, invalid >>= 1) { 606 if (invalid & 1) { 607 sc->sc_pic.pic_sources[i + j] = 608 &armgic_dummy_source; 609 } 610 } 611 } 612 #ifdef __HAVE_PIC_FAST_SOFTINTS 613 intr_establish(SOFTINT_BIO, IPL_SOFTBIO, IST_MPSAFE | IST_EDGE, 614 pic_handle_softint, (void *)SOFTINT_BIO); 615 intr_establish(SOFTINT_CLOCK, IPL_SOFTCLOCK, IST_MPSAFE | IST_EDGE, 616 pic_handle_softint, (void *)SOFTINT_CLOCK); 617 intr_establish(SOFTINT_NET, IPL_SOFTNET, IST_MPSAFE | IST_EDGE, 618 pic_handle_softint, (void *)SOFTINT_NET); 619 intr_establish(SOFTINT_SERIAL, IPL_SOFTSERIAL, IST_MPSAFE | IST_EDGE, 620 pic_handle_softint, (void *)SOFTINT_SERIAL); 621 #endif 622 #ifdef MULTIPROCESSOR 623 armgic_cpu_init(&sc->sc_pic, curcpu()); 624 625 intr_establish(ARMGIC_SGI_IPIBASE + IPI_AST, IPL_VM, 626 IST_MPSAFE | IST_EDGE, pic_ipi_ast, (void *)-1); 627 intr_establish(ARMGIC_SGI_IPIBASE + IPI_XCALL, IPL_HIGH, 628 IST_MPSAFE | IST_EDGE, pic_ipi_xcall, (void *)-1); 629 intr_establish(ARMGIC_SGI_IPIBASE + IPI_GENERIC, IPL_HIGH, 630 IST_MPSAFE | IST_EDGE, pic_ipi_generic, (void *)-1); 631 intr_establish(ARMGIC_SGI_IPIBASE + IPI_NOP, IPL_VM, 632 IST_MPSAFE | IST_EDGE, pic_ipi_nop, (void *)-1); 633 intr_establish(ARMGIC_SGI_IPIBASE + IPI_SHOOTDOWN, IPL_SCHED, 634 IST_MPSAFE | IST_EDGE, pic_ipi_shootdown, (void *)-1); 635 #ifdef DDB 636 intr_establish(ARMGIC_SGI_IPIBASE + IPI_DDB, IPL_HIGH, 637 IST_MPSAFE | IST_EDGE, pic_ipi_ddb, NULL); 638 #endif 639 #ifdef __HAVE_PREEMPTION 640 intr_establish(ARMGIC_SGI_IPIBASE + IPI_KPREEMPT, IPL_VM, 641 IST_MPSAFE | IST_EDGE, pic_ipi_kpreempt, (void *)-1); 642 #endif 643 #endif 644 645 const u_int ppis = popcount32(sc->sc_gic_valid_lines[0] >> 16); 646 const u_int sgis = popcount32(sc->sc_gic_valid_lines[0] & 0xffff); 647 aprint_normal_dev(sc->sc_dev, "%u Priorities, %zu SPIs, %u PPIs, " 648 "%u SGIs\n", priorities, sc->sc_gic_lines - ppis - sgis, ppis, 649 sgis); 650 } 651 652 CFATTACH_DECL_NEW(armgic, 0, 653 armgic_match, armgic_attach, NULL, NULL); 654