1 /* $NetBSD: gic.c,v 1.9 2014/04/27 16:22:13 matt Exp $ */ 2 /*- 3 * Copyright (c) 2012 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas of 3am Software Foundry. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "opt_ddb.h" 32 33 #define _INTR_PRIVATE 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.9 2014/04/27 16:22:13 matt Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/device.h> 41 #include <sys/evcnt.h> 42 #include <sys/intr.h> 43 #include <sys/cpu.h> 44 #include <sys/proc.h> 45 #include <sys/xcall.h> /* for xc_ipi_handler */ 46 47 #include <arm/armreg.h> 48 #include <arm/cpufunc.h> 49 #include <arm/atomic.h> 50 51 #include <arm/cortex/gic_reg.h> 52 #include <arm/cortex/mpcore_var.h> 53 54 #define ARMGIC_SGI_IPIBASE (16 - NIPI) 55 56 static int armgic_match(device_t, cfdata_t, void *); 57 static void armgic_attach(device_t, device_t, void *); 58 59 static void armgic_set_priority(struct pic_softc *, int); 60 static void armgic_unblock_irqs(struct pic_softc *, size_t, uint32_t); 61 static void armgic_block_irqs(struct pic_softc *, size_t, uint32_t); 62 static void armgic_establish_irq(struct pic_softc *, struct intrsource *); 63 #if 0 64 static void armgic_source_name(struct pic_softc *, int, char *, size_t); 65 #endif 66 67 #ifdef MULTIPROCESSOR 68 static void armgic_cpu_init(struct pic_softc *, struct cpu_info *); 69 static void armgic_ipi_send(struct pic_softc *, const kcpuset_t *, u_long); 70 #endif 71 72 static const struct pic_ops armgic_picops = { 73 .pic_unblock_irqs = armgic_unblock_irqs, 74 .pic_block_irqs = armgic_block_irqs, 75 .pic_establish_irq = armgic_establish_irq, 76 #if 0 77 .pic_source_name = armgic_source_name, 78 #endif 79 .pic_set_priority = armgic_set_priority, 80 #ifdef MULTIPROCESSOR 81 .pic_cpu_init = armgic_cpu_init, 82 .pic_ipi_send = armgic_ipi_send, 83 #endif 84 }; 85 86 #define PICTOSOFTC(pic) ((struct armgic_softc *)(pic)) 87 88 static struct armgic_softc { 89 struct pic_softc sc_pic; 90 device_t sc_dev; 91 bus_space_tag_t sc_memt; 92 bus_space_handle_t sc_gicch; 93 bus_space_handle_t sc_gicdh; 94 size_t sc_gic_lines; 95 uint32_t sc_gic_type; 96 uint32_t sc_gic_valid_lines[1024/32]; 97 uint32_t sc_enabled_local; 98 #ifdef MULTIPROCESSOR 99 uint32_t sc_mptargets; 100 #endif 101 } armgic_softc = { 102 .sc_pic = { 103 .pic_ops = &armgic_picops, 104 .pic_name = "armgic", 105 }, 106 }; 107 108 static struct intrsource armgic_dummy_source; 109 110 __CTASSERT(NIPL == 8); 111 112 /* 113 * GIC register are always in little-endian. It is assumed the bus_space 114 * will do any endian conversion required. 115 */ 116 static inline uint32_t 117 gicc_read(struct armgic_softc *sc, bus_size_t o) 118 { 119 return bus_space_read_4(sc->sc_memt, sc->sc_gicch, o); 120 } 121 122 static inline void 123 gicc_write(struct armgic_softc *sc, bus_size_t o, uint32_t v) 124 { 125 bus_space_write_4(sc->sc_memt, sc->sc_gicch, o, v); 126 } 127 128 static inline uint32_t 129 gicd_read(struct armgic_softc *sc, bus_size_t o) 130 { 131 return bus_space_read_4(sc->sc_memt, sc->sc_gicdh, o); 132 } 133 134 static inline void 135 gicd_write(struct armgic_softc *sc, bus_size_t o, uint32_t v) 136 { 137 bus_space_write_4(sc->sc_memt, sc->sc_gicdh, o, v); 138 } 139 140 /* 141 * In the GIC prioritization scheme, lower numbers have higher priority. 142 * Only write priorities that could be non-secure. 143 */ 144 static inline uint32_t 145 armgic_ipl_to_priority(int ipl) 146 { 147 return GICC_PMR_NONSECURE 148 | ((IPL_HIGH - ipl) * GICC_PMR_NS_PRIORITIES / NIPL); 149 } 150 151 #if 0 152 static inline int 153 armgic_priority_to_ipl(uint32_t priority) 154 { 155 return IPL_HIGH 156 - (priority & ~GICC_PMR_NONSECURE) * NIPL / GICC_PMR_NS_PRIORITIES; 157 } 158 #endif 159 160 static void 161 armgic_unblock_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask) 162 { 163 struct armgic_softc * const sc = PICTOSOFTC(pic); 164 const size_t group = irq_base / 32; 165 166 if (group == 0) 167 sc->sc_enabled_local |= irq_mask; 168 169 gicd_write(sc, GICD_ISENABLERn(group), irq_mask); 170 } 171 172 static void 173 armgic_block_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask) 174 { 175 struct armgic_softc * const sc = PICTOSOFTC(pic); 176 const size_t group = irq_base / 32; 177 178 if (group == 0) 179 sc->sc_enabled_local &= ~irq_mask; 180 181 gicd_write(sc, GICD_ICENABLERn(group), irq_mask); 182 } 183 184 static uint32_t armgic_last_priority; 185 186 static void 187 armgic_set_priority(struct pic_softc *pic, int ipl) 188 { 189 struct armgic_softc * const sc = PICTOSOFTC(pic); 190 191 const uint32_t priority = armgic_ipl_to_priority(ipl); 192 gicc_write(sc, GICC_PMR, priority); 193 armgic_last_priority = priority; 194 } 195 196 #ifdef __HAVE_PIC_FAST_SOFTINTS 197 void 198 softint_init_md(lwp_t *l, u_int level, uintptr_t *machdep_p) 199 { 200 lwp_t **lp = &l->l_cpu->ci_softlwps[level]; 201 KASSERT(*lp == NULL || *lp == l); 202 *lp = l; 203 /* 204 * Really easy. Just tell it to trigger the local CPU. 205 */ 206 *machdep_p = GICD_SGIR_TargetListFilter_Me 207 | __SHIFTIN(level, GICD_SGIR_SGIINTID); 208 } 209 210 void 211 softint_trigger(uintptr_t machdep) 212 { 213 214 gicd_write(&armgic_softc, GICD_SGIR, machdep); 215 } 216 #endif 217 218 void 219 armgic_irq_handler(void *tf) 220 { 221 struct cpu_info * const ci = curcpu(); 222 struct armgic_softc * const sc = &armgic_softc; 223 const int old_ipl = ci->ci_cpl; 224 #ifdef DIAGNOSTIC 225 const int old_mtx_count = ci->ci_mtx_count; 226 const int old_l_biglocks = ci->ci_curlwp->l_biglocks; 227 #endif 228 #ifdef DEBUG 229 size_t n = 0; 230 #endif 231 232 ci->ci_data.cpu_nintr++; 233 234 KASSERTMSG(old_ipl != IPL_HIGH, "old_ipl %d pmr %#x hppir %#x", 235 old_ipl, gicc_read(sc, GICC_PMR), gicc_read(sc, GICC_HPPIR)); 236 #if 0 237 printf("%s(enter): %s: pmr=%u hppir=%u\n", 238 __func__, ci->ci_data.cpu_name, 239 gicc_read(sc, GICC_PMR), 240 gicc_read(sc, GICC_HPPIR)); 241 #elif 0 242 printf("(%u:%d", ci->ci_index, old_ipl); 243 #endif 244 245 for (;;) { 246 uint32_t iar = gicc_read(sc, GICC_IAR); 247 uint32_t irq = __SHIFTOUT(iar, GICC_IAR_IRQ); 248 //printf(".%u", irq); 249 if (irq == GICC_IAR_IRQ_SPURIOUS) { 250 iar = gicc_read(sc, GICC_IAR); 251 irq = __SHIFTOUT(iar, GICC_IAR_IRQ); 252 if (irq == GICC_IAR_IRQ_SPURIOUS) 253 break; 254 //printf(".%u", irq); 255 } 256 257 //const uint32_t cpuid = __SHIFTOUT(iar, GICC_IAR_CPUID_MASK); 258 struct intrsource * const is = sc->sc_pic.pic_sources[irq]; 259 KASSERT(is != &armgic_dummy_source); 260 261 /* 262 * GIC has asserted IPL for us so we can just update ci_cpl. 263 * 264 * But it's not that simple. We may have already bumped ci_cpl 265 * due to a high priority interrupt and now we are about to 266 * dispatch one lower than the previous. It's possible for 267 * that previous interrupt to have deferred some interrupts 268 * so we need deal with those when lowering to the current 269 * interrupt's ipl. 270 * 271 * However, if are just raising ipl, we can just update ci_cpl. 272 */ 273 #if 0 274 const int ipl = armgic_priority_to_ipl(gicc_read(sc, GICC_RPR)); 275 KASSERTMSG(panicstr != NULL || ipl == is->is_ipl, 276 "%s: irq %d: running ipl %d != source ipl %u", 277 ci->ci_data.cpu_name, irq, ipl, is->is_ipl); 278 #else 279 const int ipl = is->is_ipl; 280 #endif 281 if (__predict_false(ipl < ci->ci_cpl)) { 282 //printf("<"); 283 pic_do_pending_ints(I32_bit, ipl, tf); 284 KASSERT(ci->ci_cpl == ipl); 285 } else { 286 KASSERTMSG(ipl > ci->ci_cpl, "ipl %d cpl %d hw-ipl %#x", 287 ipl, ci->ci_cpl, 288 gicc_read(sc, GICC_PMR)); 289 //printf(">"); 290 gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ipl)); 291 ci->ci_cpl = ipl; 292 } 293 //printf("$"); 294 cpsie(I32_bit); 295 pic_dispatch(is, tf); 296 cpsid(I32_bit); 297 gicc_write(sc, GICC_EOIR, iar); 298 #ifdef DEBUG 299 n++; 300 KDASSERTMSG(n < 5, "%s: processed too many (%zu)", 301 ci->ci_data.cpu_name, n); 302 #endif 303 } 304 305 // printf("%s(%p): exit (%zu dispatched)\n", __func__, tf, n); 306 /* 307 * Now handle any pending ints. 308 */ 309 //printf("!"); 310 KASSERT(old_ipl != IPL_HIGH); 311 pic_do_pending_ints(I32_bit, old_ipl, tf); 312 KASSERTMSG(ci->ci_cpl == old_ipl, "ci_cpl %d old_ipl %d", ci->ci_cpl, old_ipl); 313 KASSERT(old_mtx_count == ci->ci_mtx_count); 314 KASSERT(old_l_biglocks == ci->ci_curlwp->l_biglocks); 315 #if 0 316 printf("%s(exit): %s(%d): pmr=%u hppir=%u\n", 317 __func__, ci->ci_data.cpu_name, ci->ci_cpl, 318 gicc_read(sc, GICC_PMR), 319 gicc_read(sc, GICC_HPPIR)); 320 #elif 0 321 printf("->%#x)", ((struct trapframe *)tf)->tf_pc); 322 #endif 323 } 324 325 void 326 armgic_establish_irq(struct pic_softc *pic, struct intrsource *is) 327 { 328 struct armgic_softc * const sc = PICTOSOFTC(pic); 329 const size_t group = is->is_irq / 32; 330 const u_int irq = is->is_irq & 31; 331 const u_int byte_shift = 8 * (irq & 3); 332 const u_int twopair_shift = 2 * (irq & 15); 333 334 KASSERTMSG(sc->sc_gic_valid_lines[group] & __BIT(irq), 335 "irq %u: not valid (group[%zu]=0x%08x [0x%08x])", 336 is->is_irq, group, sc->sc_gic_valid_lines[group], 337 (uint32_t)__BIT(irq)); 338 339 KASSERTMSG(is->is_type == IST_LEVEL || is->is_type == IST_EDGE, 340 "irq %u: type %u unsupported", is->is_irq, is->is_type); 341 342 const bus_size_t targets_reg = GICD_ITARGETSRn(is->is_irq / 4); 343 const bus_size_t cfg_reg = GICD_ICFGRn(is->is_irq / 16); 344 uint32_t targets = gicd_read(sc, targets_reg); 345 uint32_t cfg = gicd_read(sc, cfg_reg); 346 347 if (group > 0) { 348 /* 349 * There are 4 irqs per TARGETS register. For now bind 350 * to the primary cpu. 351 */ 352 targets &= ~(0xff << byte_shift); 353 #ifdef MULTIPROCESSOR 354 if (is->is_mpsafe) { 355 targets |= sc->sc_mptargets; 356 } else 357 #endif 358 targets |= 1 << byte_shift; 359 gicd_write(sc, targets_reg, targets); 360 361 /* 362 * There are 16 irqs per CFG register. 10=EDGE 00=LEVEL 363 */ 364 uint32_t new_cfg = cfg; 365 uint32_t old_cfg = (cfg >> twopair_shift) & 3; 366 if (is->is_type == IST_LEVEL && (old_cfg & 2) != 0) { 367 new_cfg &= ~(3 << twopair_shift); 368 } else if (is->is_type == IST_EDGE && (old_cfg & 2) == 0) { 369 new_cfg |= 2 << twopair_shift; 370 } 371 if (new_cfg != cfg) { 372 gicd_write(sc, cfg_reg, cfg); 373 #if 0 374 printf("%s: irq %u: cfg changed from %#x to %#x\n", 375 pic->pic_name, is->is_irq, cfg, new_cfg); 376 #endif 377 } 378 #ifdef MULTIPROCESSOR 379 } else { 380 /* 381 * All group 0 interrupts are per processor and MPSAFE by 382 * default. 383 */ 384 is->is_mpsafe = true; 385 #endif 386 } 387 388 /* 389 * There are 4 irqs per PRIORITY register. Map the IPL 390 * to GIC priority. 391 */ 392 const bus_size_t priority_reg = GICD_IPRIORITYRn(is->is_irq / 4); 393 uint32_t priority = gicd_read(sc, priority_reg); 394 priority &= ~(0xff << byte_shift); 395 priority |= armgic_ipl_to_priority(is->is_ipl) << byte_shift; 396 gicd_write(sc, priority_reg, priority); 397 398 #if 0 399 printf("%s: irq %u: target %#x cfg %u priority %#x (%u)\n", 400 pic->pic_name, is->is_irq, (targets >> byte_shift) & 0xff, 401 (cfg >> twopair_shift) & 3, (priority >> byte_shift) & 0xff, 402 is->is_ipl); 403 #endif 404 } 405 406 #ifdef MULTIPROCESSOR 407 static void 408 armgic_cpu_init_priorities(struct armgic_softc *sc) 409 { 410 uint32_t enabled = sc->sc_enabled_local; 411 for (size_t i = 0; i < 32; i += 4, enabled >>= 4) { 412 /* 413 * If there are no enabled interrupts for the priority register, 414 * don't bother changing it. 415 */ 416 if ((enabled & 0x0f) == 0) 417 continue; 418 /* 419 * Since priorities are in 3210 order, it' 420 */ 421 const bus_size_t priority_reg = GICD_IPRIORITYRn(i / 4); 422 uint32_t priority = gicd_read(sc, priority_reg); 423 uint32_t byte_mask = 0xff; 424 size_t byte_shift = 0; 425 for (size_t j = 0; j < 4; j++, byte_mask <<= 8, byte_shift += 8) { 426 struct intrsource * const is = sc->sc_pic.pic_sources[i+j]; 427 if (is == NULL || is == &armgic_dummy_source) 428 continue; 429 priority &= ~byte_mask; 430 priority |= armgic_ipl_to_priority(is->is_ipl) << byte_shift; 431 } 432 gicd_write(sc, priority_reg, priority); 433 } 434 } 435 436 static void 437 armgic_cpu_init_targets(struct armgic_softc *sc) 438 { 439 /* 440 * Update the mpsafe targets 441 */ 442 for (size_t irq = 32; irq < sc->sc_gic_lines; irq++) { 443 struct intrsource * const is = sc->sc_pic.pic_sources[irq]; 444 const bus_size_t targets_reg = GICD_ITARGETSRn(irq / 4); 445 if (is != NULL && is->is_mpsafe) { 446 const u_int byte_shift = 0xff << (8 * (irq & 3)); 447 uint32_t targets = gicd_read(sc, targets_reg); 448 targets |= sc->sc_mptargets << byte_shift; 449 gicd_write(sc, targets_reg, targets); 450 } 451 } 452 } 453 454 void 455 armgic_cpu_init(struct pic_softc *pic, struct cpu_info *ci) 456 { 457 struct armgic_softc * const sc = PICTOSOFTC(pic); 458 sc->sc_mptargets |= 1 << cpu_index(ci); 459 KASSERTMSG(ci->ci_cpl == IPL_HIGH, "ipl %d not IPL_HIGH", ci->ci_cpl); 460 if (!CPU_IS_PRIMARY(ci)) { 461 if (sc->sc_mptargets != 1) { 462 armgic_cpu_init_targets(sc); 463 } 464 if (sc->sc_enabled_local) { 465 armgic_cpu_init_priorities(sc); 466 gicd_write(sc, GICD_ISENABLERn(0), 467 sc->sc_enabled_local); 468 } 469 } 470 gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ci->ci_cpl)); // set PMR 471 gicc_write(sc, GICC_CTRL, GICC_CTRL_V1_Enable); // enable interrupt 472 cpsie(I32_bit); // allow IRQ exceptions 473 } 474 475 void 476 armgic_ipi_send(struct pic_softc *pic, const kcpuset_t *kcp, u_long ipi) 477 { 478 struct armgic_softc * const sc = PICTOSOFTC(pic); 479 480 #if 0 481 if (ipi == IPI_NOP) { 482 __asm __volatile("sev"); 483 return; 484 } 485 #endif 486 487 uint32_t sgir = __SHIFTIN(ARMGIC_SGI_IPIBASE + ipi, GICD_SGIR_SGIINTID); 488 if (kcp != NULL) { 489 uint32_t targets; 490 kcpuset_export_u32(kcp, &targets, sizeof(targets)); 491 sgir |= __SHIFTIN(targets, GICD_SGIR_TargetList); 492 sgir |= GICD_SGIR_TargetListFilter_List; 493 } else { 494 if (ncpu == 1) 495 return; 496 sgir |= GICD_SGIR_TargetListFilter_NotMe; 497 } 498 499 //printf("%s: %s: %#x", __func__, curcpu()->ci_data.cpu_name, sgir); 500 gicd_write(sc, GICD_SGIR, sgir); 501 //printf("\n"); 502 } 503 #endif 504 505 int 506 armgic_match(device_t parent, cfdata_t cf, void *aux) 507 { 508 struct mpcore_attach_args * const mpcaa = aux; 509 510 if (strcmp(cf->cf_name, mpcaa->mpcaa_name) != 0) 511 return 0; 512 if (!CPU_ID_CORTEX_P(cputype) || CPU_ID_CORTEX_A8_P(cputype)) 513 return 0; 514 515 return 1; 516 } 517 518 void 519 armgic_attach(device_t parent, device_t self, void *aux) 520 { 521 struct armgic_softc * const sc = &armgic_softc; 522 struct mpcore_attach_args * const mpcaa = aux; 523 524 sc->sc_dev = self; 525 self->dv_private = sc; 526 527 sc->sc_memt = mpcaa->mpcaa_memt; /* provided for us */ 528 bus_space_subregion(sc->sc_memt, mpcaa->mpcaa_memh, mpcaa->mpcaa_off1, 529 4096, &sc->sc_gicdh); 530 bus_space_subregion(sc->sc_memt, mpcaa->mpcaa_memh, mpcaa->mpcaa_off2, 531 4096, &sc->sc_gicch); 532 533 sc->sc_gic_type = gicd_read(sc, GICD_TYPER); 534 sc->sc_pic.pic_maxsources = GICD_TYPER_LINES(sc->sc_gic_type); 535 536 gicc_write(sc, GICC_CTRL, 0); /* disable all interrupts */ 537 gicd_write(sc, GICD_CTRL, 0); /* disable all interrupts */ 538 539 gicc_write(sc, GICC_PMR, 0xff); 540 uint32_t pmr = gicc_read(sc, GICC_PMR); 541 u_int priorities = 1 << popcount32(pmr); 542 543 /* 544 * Let's find out how many real sources we have. 545 */ 546 for (size_t i = 0, group = 0; 547 i < sc->sc_pic.pic_maxsources; 548 i += 32, group++) { 549 /* 550 * To figure what sources are real, one enables all interrupts 551 * and then reads back the enable mask so which ones really 552 * got enabled. 553 */ 554 gicd_write(sc, GICD_ISENABLERn(group), 0xffffffff); 555 uint32_t valid = gicd_read(sc, GICD_ISENABLERn(group)); 556 557 /* 558 * Now disable (clear enable) them again. 559 */ 560 gicd_write(sc, GICD_ICENABLERn(group), valid); 561 562 /* 563 * Count how many are valid. 564 */ 565 sc->sc_gic_lines += popcount32(valid); 566 sc->sc_gic_valid_lines[group] = valid; 567 } 568 569 aprint_normal(": Generic Interrupt Controller, " 570 "%zu sources (%zu valid)\n", 571 sc->sc_pic.pic_maxsources, sc->sc_gic_lines); 572 573 pic_add(&sc->sc_pic, 0); 574 575 /* 576 * Force the GICD to IPL_HIGH and then enable interrupts. 577 */ 578 struct cpu_info * const ci = curcpu(); 579 KASSERTMSG(ci->ci_cpl == IPL_HIGH, "ipl %d not IPL_HIGH", ci->ci_cpl); 580 armgic_set_priority(&sc->sc_pic, ci->ci_cpl); // set PMR 581 gicd_write(sc, GICD_CTRL, GICD_CTRL_Enable); // enable Distributer 582 gicc_write(sc, GICC_CTRL, GICC_CTRL_V1_Enable); // enable CPU interrupts 583 cpsie(I32_bit); // allow interrupt exceptions 584 585 /* 586 * For each line that isn't valid, we set the intrsource for it to 587 * point at a dummy source so that pic_intr_establish will fail for it. 588 */ 589 for (size_t i = 0, group = 0; 590 i < sc->sc_pic.pic_maxsources; 591 i += 32, group++) { 592 uint32_t invalid = ~sc->sc_gic_valid_lines[group]; 593 for (size_t j = 0; invalid && j < 32; j++, invalid >>= 1) { 594 if (invalid & 1) { 595 sc->sc_pic.pic_sources[i + j] = 596 &armgic_dummy_source; 597 } 598 } 599 } 600 #ifdef __HAVE_PIC_FAST_SOFTINTS 601 intr_establish(SOFTINT_BIO, IPL_SOFTBIO, IST_EDGE, 602 pic_handle_softint, (void *)SOFTINT_BIO); 603 intr_establish(SOFTINT_CLOCK, IPL_SOFTCLOCK, IST_EDGE, 604 pic_handle_softint, (void *)SOFTINT_CLOCK); 605 intr_establish(SOFTINT_NET, IPL_SOFTNET, IST_EDGE, 606 pic_handle_softint, (void *)SOFTINT_NET); 607 intr_establish(SOFTINT_SERIAL, IPL_SOFTSERIAL, IST_EDGE, 608 pic_handle_softint, (void *)SOFTINT_SERIAL); 609 #endif 610 #ifdef MULTIPROCESSOR 611 intr_establish(ARMGIC_SGI_IPIBASE + IPI_AST, IPL_VM, IST_EDGE, 612 pic_ipi_nop, (void *)-1); 613 intr_establish(ARMGIC_SGI_IPIBASE + IPI_XCALL, IPL_VM, IST_EDGE, 614 pic_ipi_xcall, (void *)-1); 615 intr_establish(ARMGIC_SGI_IPIBASE + IPI_NOP, IPL_VM, IST_EDGE, 616 pic_ipi_nop, (void *)-1); 617 intr_establish(ARMGIC_SGI_IPIBASE + IPI_SHOOTDOWN, IPL_VM, IST_EDGE, 618 pic_ipi_shootdown, (void *)-1); 619 #ifdef DDB 620 intr_establish(ARMGIC_SGI_IPIBASE + IPI_DDB, IPL_HIGH, IST_EDGE, 621 pic_ipi_ddb, NULL); 622 #endif 623 #ifdef __HAVE_PREEMPTION 624 intr_establish(ARMGIC_SGI_IPIBASE + IPI_KPREEMPT, IPL_VM, IST_EDGE, 625 pic_ipi_nop, (void *)-1); 626 #endif 627 armgic_cpu_init(&sc->sc_pic, curcpu()); 628 #endif 629 630 const u_int ppis = popcount32(sc->sc_gic_valid_lines[0] >> 16); 631 const u_int sgis = popcount32(sc->sc_gic_valid_lines[0] & 0xffff); 632 aprint_normal_dev(sc->sc_dev, "%u Priorities, %zu SPIs, %u PPIs, %u SGIs\n", 633 priorities, sc->sc_gic_lines - ppis - sgis, ppis, sgis); 634 } 635 636 CFATTACH_DECL_NEW(armgic, 0, 637 armgic_match, armgic_attach, NULL, NULL); 638