1 /*- 2 * Copyright (c) 2012 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas of 3am Software Foundry. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include "locators.h" 31 32 #include <sys/cdefs.h> 33 34 __KERNEL_RCSID(1, "$NetBSD: armperiph.c,v 1.10 2015/04/02 06:15:40 matt Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/device.h> 38 #include <sys/lwp.h> 39 40 #include "ioconf.h" 41 42 #include <arm/mainbus/mainbus.h> 43 #include <arm/cortex/mpcore_var.h> 44 #include <arm/cortex/gtmr_intr.h> 45 46 static int armperiph_match(device_t, cfdata_t, void *); 47 static void armperiph_attach(device_t, device_t, void *); 48 49 static bool attached; 50 51 struct armperiph_softc { 52 device_t sc_dev; 53 bus_space_tag_t sc_memt; 54 bus_space_handle_t sc_memh; 55 }; 56 57 struct armperiph_info { 58 const char pi_name[12]; 59 bus_size_t pi_off1; 60 bus_size_t pi_off2; 61 }; 62 63 #ifdef CPU_CORTEXA5 64 static const struct armperiph_info a5_devices[] = { 65 { "armscu", 0x0000, 0 }, 66 { "armgic", 0x1000, 0x0100 }, 67 { "a9tmr", 0x0200, 0 }, 68 { "a9wdt", 0x0600, 0 }, 69 { "arml2cc", 0, 0 }, /* external; needs "offset" property */ 70 { "", 0, 0 }, 71 }; 72 #endif 73 74 #ifdef CPU_CORTEXA7 75 static const struct armperiph_info a7_devices[] = { 76 { "armgic", 0x1000, 0x2000 }, 77 { "armgtmr", 0, 0 }, 78 { "", 0, 0 }, 79 }; 80 #endif 81 82 #ifdef CPU_CORTEXA9 83 static const struct armperiph_info a9_devices[] = { 84 { "armscu", 0x0000, 0 }, 85 { "arml2cc", 0x2000, 0 }, 86 { "armgic", 0x1000, 0x0100 }, 87 { "a9tmr", 0x0200, 0 }, 88 { "a9wdt", 0x0600, 0 }, 89 { "", 0, 0 }, 90 }; 91 #endif 92 93 #ifdef CPU_CORTEXA15 94 static const struct armperiph_info a15_devices[] = { 95 { "armgic", 0x1000, 0x2000 }, 96 { "armgtmr", 0, 0 }, 97 { "", 0, 0 }, 98 }; 99 #endif 100 101 #ifdef CPU_CORTEXA17 102 static const struct armperiph_info a17_devices[] = { 103 { "armgic", 0x1000, 0x2000 }, 104 { "armgtmr", 0, 0 }, 105 { "", 0, 0 }, 106 }; 107 #endif 108 109 110 static const struct mpcore_config { 111 const struct armperiph_info *cfg_devices; 112 uint32_t cfg_cpuid; 113 uint32_t cfg_cbar_size; 114 } configs[] = { 115 #ifdef CPU_CORTEXA5 116 { a5_devices, 0x410fc050, 2*4096 }, 117 #endif 118 #ifdef CPU_CORTEXA7 119 { a7_devices, 0x410fc070, 8*4096 }, 120 #endif 121 #ifdef CPU_CORTEXA9 122 { a9_devices, 0x410fc090, 3*4096 }, 123 #endif 124 #ifdef CPU_CORTEXA15 125 { a15_devices, 0x410fc0f0, 8*4096 }, 126 #endif 127 #ifdef CPU_CORTEXA17 128 { a17_devices, 0x410fc0e0, 8*4096 }, 129 #endif 130 }; 131 132 static const struct mpcore_config * 133 armperiph_find_config(void) 134 { 135 const uint32_t arm_cpuid = curcpu()->ci_arm_cpuid & 0xff0ff0f0; 136 for (size_t i = 0; i < __arraycount(configs); i++) { 137 if (arm_cpuid == configs[i].cfg_cpuid) { 138 return configs + i; 139 } 140 } 141 142 return NULL; 143 } 144 145 CFATTACH_DECL_NEW(armperiph, sizeof(struct armperiph_softc), 146 armperiph_match, armperiph_attach, NULL, NULL); 147 148 static int 149 armperiph_match(device_t parent, cfdata_t cf, void *aux) 150 { 151 struct mainbus_attach_args * const mb = aux; 152 const int base = cf->cf_loc[MAINBUSCF_BASE]; 153 const int size = cf->cf_loc[MAINBUSCF_SIZE]; 154 const int dack = cf->cf_loc[MAINBUSCF_DACK]; 155 const int irq = cf->cf_loc[MAINBUSCF_IRQ]; 156 const int intrbase = cf->cf_loc[MAINBUSCF_INTRBASE]; 157 158 if (attached) 159 return 0; 160 161 if (base != MAINBUSCF_BASE_DEFAULT || base != mb->mb_iobase 162 || size != MAINBUSCF_SIZE_DEFAULT || size != mb->mb_iosize 163 || dack != MAINBUSCF_DACK_DEFAULT || dack != mb->mb_drq 164 || irq != MAINBUSCF_IRQ_DEFAULT || irq != mb->mb_irq 165 || intrbase != MAINBUSCF_INTRBASE_DEFAULT 166 || intrbase != mb->mb_intrbase) 167 return 0; 168 169 if (!CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid)) 170 return 0; 171 172 if (armreg_cbar_read() == 0) 173 return 0; 174 175 if (armperiph_find_config() == NULL) 176 return 0; 177 178 return 1; 179 } 180 181 static void 182 armperiph_attach(device_t parent, device_t self, void *aux) 183 { 184 struct armperiph_softc * const sc = device_private(self); 185 struct mainbus_attach_args * const mb = aux; 186 bus_addr_t cbar = armreg_cbar_read(); 187 const struct mpcore_config * const cfg = armperiph_find_config(); 188 prop_dictionary_t prop = device_properties(self); 189 uint32_t cbar_override; 190 191 if (prop_dictionary_get_uint32(prop, "cbar", &cbar_override)) 192 cbar = (bus_addr_t)cbar_override; 193 194 /* 195 * The normal mainbus bus space will not work for us so the port's 196 * device_register must have replaced it with one that will work. 197 */ 198 sc->sc_dev = self; 199 sc->sc_memt = mb->mb_iot; 200 201 int error = bus_space_map(sc->sc_memt, cbar, cfg->cfg_cbar_size, 0, 202 &sc->sc_memh); 203 if (error) { 204 aprint_normal(": error mapping registers at %#lx: %d\n", 205 cbar, error); 206 return; 207 } 208 aprint_normal("\n"); 209 210 /* 211 * Let's try to attach any children we may have. 212 */ 213 for (size_t i = 0; cfg->cfg_devices[i].pi_name[0] != 0; i++) { 214 struct mpcore_attach_args mpcaa = { 215 .mpcaa_name = cfg->cfg_devices[i].pi_name, 216 .mpcaa_memt = sc->sc_memt, 217 .mpcaa_memh = sc->sc_memh, 218 .mpcaa_off1 = cfg->cfg_devices[i].pi_off1, 219 .mpcaa_off2 = cfg->cfg_devices[i].pi_off2, 220 }; 221 #if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15) 222 if (strcmp(mpcaa.mpcaa_name, "armgtmr") == 0) { 223 mpcaa.mpcaa_irq = IRQ_GTMR_PPI_VTIMER; 224 } 225 #endif 226 227 config_found(self, &mpcaa, NULL); 228 } 229 } 230