1 /*- 2 * Copyright (c) 2012 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas of 3am Software Foundry. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include "locators.h" 31 32 #include <sys/cdefs.h> 33 34 __KERNEL_RCSID(1, "$NetBSD: armperiph.c,v 1.4 2013/06/20 05:30:21 matt Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/device.h> 38 39 #include "ioconf.h" 40 41 #include <arm/mainbus/mainbus.h> 42 #include <arm/cortex/mpcore_var.h> 43 44 static int armperiph_match(device_t, cfdata_t, void *); 45 static void armperiph_attach(device_t, device_t, void *); 46 47 static bool attached; 48 49 struct armperiph_softc { 50 device_t sc_dev; 51 bus_space_tag_t sc_memt; 52 bus_space_handle_t sc_memh; 53 }; 54 55 struct armperiph_info { 56 const char pi_name[12]; 57 bus_size_t pi_off1; 58 bus_size_t pi_off2; 59 }; 60 61 #ifdef CPU_CORTEXA5 62 static const struct armperiph_info a5_devices[] = { 63 { "armscu", 0x0000, 0 }, 64 { "armgic", 0x1000, 0x0100 }, 65 { "a9tmr", 0x0200, 0 }, 66 { "", 0, 0 }, 67 }; 68 #endif 69 70 #ifdef CPU_CORTEXA7 71 static const struct armperiph_info a7_devices[] = { 72 { "armgic", 0x1000, 0x2000 }, 73 { "armgtmr", 0, 0 }, 74 { "", 0, 0 }, 75 }; 76 #endif 77 78 #ifdef CPU_CORTEXA9 79 static const struct armperiph_info a9_devices[] = { 80 { "armscu", 0x0000, 0 }, 81 { "arml2cc", 0x2000, 0 }, 82 { "armgic", 0x1000, 0x0100 }, 83 { "a9tmr", 0x0200, 0 }, 84 { "a9wdt", 0x0600, 0 }, 85 { "", 0, 0 }, 86 }; 87 #endif 88 89 #ifdef CPU_CORTEXA15 90 static const struct armperiph_info a15_devices[] = { 91 { "armgic", 0x1000, 0x2000 }, 92 { "armgtmr", 0, 0 }, 93 { "", 0, 0 }, 94 }; 95 #endif 96 97 98 static const struct mpcore_config { 99 const struct armperiph_info *cfg_devices; 100 uint32_t cfg_cpuid; 101 uint32_t cfg_cbar_size; 102 } configs[] = { 103 #ifdef CPU_CORTEXA5 104 { a5_devices, 0x410fc050, 2*4096 }, 105 #endif 106 #ifdef CPU_CORTEXA7 107 { a7_devices, 0x410fc070, 8*4096 }, 108 #endif 109 #ifdef CPU_CORTEXA9 110 { a9_devices, 0x410fc090, 3*4096 }, 111 #endif 112 #ifdef CPU_CORTEXA15 113 { a15_devices, 0x410fc0f0, 8*4096 }, 114 #endif 115 }; 116 117 static const struct mpcore_config * 118 armperiph_find_config(void) 119 { 120 const uint32_t arm_cpuid = curcpu()->ci_arm_cpuid & 0xff0ff0f0; 121 for (size_t i = 0; i < __arraycount(configs); i++) { 122 if (arm_cpuid == configs[i].cfg_cpuid) { 123 return configs + i; 124 } 125 } 126 127 return NULL; 128 } 129 130 CFATTACH_DECL_NEW(armperiph, sizeof(struct armperiph_softc), 131 armperiph_match, armperiph_attach, NULL, NULL); 132 133 static int 134 armperiph_match(device_t parent, cfdata_t cf, void *aux) 135 { 136 struct mainbus_attach_args * const mb = aux; 137 const int base = cf->cf_loc[MAINBUSCF_BASE]; 138 const int size = cf->cf_loc[MAINBUSCF_SIZE]; 139 const int dack = cf->cf_loc[MAINBUSCF_DACK]; 140 const int irq = cf->cf_loc[MAINBUSCF_IRQ]; 141 const int intrbase = cf->cf_loc[MAINBUSCF_INTRBASE]; 142 143 if (attached) 144 return 0; 145 146 if (base != MAINBUSCF_BASE_DEFAULT || base != mb->mb_iobase 147 || size != MAINBUSCF_SIZE_DEFAULT || size != mb->mb_iosize 148 || dack != MAINBUSCF_DACK_DEFAULT || dack != mb->mb_drq 149 || irq != MAINBUSCF_IRQ_DEFAULT || irq != mb->mb_irq 150 || intrbase != MAINBUSCF_INTRBASE_DEFAULT 151 || intrbase != mb->mb_intrbase) 152 return 0; 153 154 if (!CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid)) 155 return 0; 156 157 if (armreg_cbar_read() == 0) 158 return 0; 159 160 if (armperiph_find_config() == NULL) 161 return 0; 162 163 return 1; 164 } 165 166 static void 167 armperiph_attach(device_t parent, device_t self, void *aux) 168 { 169 struct armperiph_softc * const sc = device_private(self); 170 struct mainbus_attach_args * const mb = aux; 171 bus_addr_t cbar = armreg_cbar_read(); 172 const struct mpcore_config * const cfg = armperiph_find_config(); 173 174 /* 175 * The normal mainbus bus space will not work for us so the port's 176 * device_register must have replaced it with one that will work. 177 */ 178 sc->sc_dev = self; 179 sc->sc_memt = mb->mb_iot; 180 181 int error = bus_space_map(sc->sc_memt, cbar, cfg->cfg_cbar_size, 0, 182 &sc->sc_memh); 183 if (error) { 184 aprint_normal(": error mapping registers at %#lx: %d\n", 185 cbar, error); 186 return; 187 } 188 aprint_normal("\n"); 189 190 /* 191 * Let's try to attach any children we may have. 192 */ 193 for (size_t i = 0; cfg->cfg_devices[i].pi_name[0] != 0; i++) { 194 struct mpcore_attach_args mpcaa = { 195 .mpcaa_name = cfg->cfg_devices[i].pi_name, 196 .mpcaa_memt = sc->sc_memt, 197 .mpcaa_memh = sc->sc_memh, 198 .mpcaa_off1 = cfg->cfg_devices[i].pi_off1, 199 .mpcaa_off2 = cfg->cfg_devices[i].pi_off2, 200 }; 201 202 config_found(self, &mpcaa, NULL); 203 } 204 } 205