1 /*- 2 * Copyright (c) 2012 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas of 3am Software Foundry. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include "locators.h" 31 #include "opt_cputypes.h" 32 33 #include <sys/cdefs.h> 34 35 __KERNEL_RCSID(1, "$NetBSD: armperiph.c,v 1.19 2021/08/07 16:18:43 thorpej Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/device.h> 39 #include <sys/lwp.h> 40 41 #include "ioconf.h" 42 43 #include <arm/mainbus/mainbus.h> 44 #include <arm/cortex/mpcore_var.h> 45 #include <arm/cortex/gtmr_intr.h> 46 #include <arm/cortex/a9tmr_intr.h> 47 48 static int armperiph_match(device_t, cfdata_t, void *); 49 static void armperiph_attach(device_t, device_t, void *); 50 51 static bool attached; 52 53 struct armperiph_softc { 54 device_t sc_dev; 55 bus_space_tag_t sc_memt; 56 bus_space_handle_t sc_memh; 57 }; 58 59 struct armperiph_info { 60 const char pi_name[12]; 61 bus_size_t pi_off1; 62 bus_size_t pi_off2; 63 }; 64 65 static const struct armperiph_info a5_devices[] = { 66 { "armscu", 0x0000, 0 }, 67 { "armgic", 0x1000, 0x0100 }, 68 { "arma9tmr", 0x0200, 0 }, 69 { "a9wdt", 0x0600, 0 }, 70 { "arml2cc", 0, 0 }, /* external; needs "offset" property */ 71 { "", 0, 0 }, 72 }; 73 74 static const struct armperiph_info a7_devices[] = { 75 { "armgic", 0x1000, 0x2000 }, 76 { "armgtmr", 0, 0 }, 77 { "", 0, 0 }, 78 }; 79 80 static const struct armperiph_info a9_devices[] = { 81 { "armscu", 0x0000, 0 }, 82 { "arml2cc", 0x2000, 0 }, 83 { "armgic", 0x1000, 0x0100 }, 84 { "arma9tmr", 0x0200, 0 }, 85 { "a9wdt", 0x0600, 0 }, 86 { "", 0, 0 }, 87 }; 88 89 static const struct armperiph_info a15_devices[] = { 90 { "armgic", 0x1000, 0x2000 }, 91 { "armgtmr", 0, 0 }, 92 { "", 0, 0 }, 93 }; 94 95 static const struct armperiph_info a17_devices[] = { 96 { "armgic", 0x1000, 0x2000 }, 97 { "armgtmr", 0, 0 }, 98 { "", 0, 0 }, 99 }; 100 101 static const struct armperiph_info a57_devices[] = { 102 { "armgic", 0x1000, 0x2000 }, 103 { "armgtmr", 0, 0 }, 104 { "", 0, 0 }, 105 }; 106 107 108 static const struct mpcore_config { 109 const struct armperiph_info *cfg_devices; 110 uint32_t cfg_cpuid; 111 uint32_t cfg_cbar_size; 112 } configs[] = { 113 { a5_devices, 0x410fc050, 2*4096 }, 114 { a7_devices, 0x410fc070, 8*4096 }, 115 { a9_devices, 0x410fc090, 3*4096 }, 116 { a15_devices, 0x410fc0f0, 8*4096 }, 117 { a17_devices, 0x410fc0e0, 8*4096 }, 118 { a57_devices, 0x410fd070, 8*4096 }, 119 }; 120 121 static const struct mpcore_config * 122 armperiph_find_config(void) 123 { 124 const uint32_t arm_cpuid = curcpu()->ci_arm_cpuid & 0xff0ff0f0; 125 for (size_t i = 0; i < __arraycount(configs); i++) { 126 if (arm_cpuid == configs[i].cfg_cpuid) { 127 return configs + i; 128 } 129 } 130 131 return NULL; 132 } 133 134 CFATTACH_DECL_NEW(armperiph, sizeof(struct armperiph_softc), 135 armperiph_match, armperiph_attach, NULL, NULL); 136 137 static int 138 armperiph_match(device_t parent, cfdata_t cf, void *aux) 139 { 140 struct mainbus_attach_args * const mb = aux; 141 const int base = cf->cf_loc[MAINBUSCF_BASE]; 142 const int size = cf->cf_loc[MAINBUSCF_SIZE]; 143 const int dack = cf->cf_loc[MAINBUSCF_DACK]; 144 const int irq = cf->cf_loc[MAINBUSCF_IRQ]; 145 const int intrbase = cf->cf_loc[MAINBUSCF_INTRBASE]; 146 147 if (attached) 148 return 0; 149 150 if (base != MAINBUSCF_BASE_DEFAULT || base != mb->mb_iobase 151 || size != MAINBUSCF_SIZE_DEFAULT || size != mb->mb_iosize 152 || dack != MAINBUSCF_DACK_DEFAULT || dack != mb->mb_drq 153 || irq != MAINBUSCF_IRQ_DEFAULT || irq != mb->mb_irq 154 || intrbase != MAINBUSCF_INTRBASE_DEFAULT 155 || intrbase != mb->mb_intrbase) 156 return 0; 157 158 if (!CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid)) 159 return 0; 160 161 if (armreg_cbar_read() == 0) 162 return 0; 163 164 if (armperiph_find_config() == NULL) 165 return 0; 166 167 return 1; 168 } 169 170 static void 171 armperiph_attach(device_t parent, device_t self, void *aux) 172 { 173 struct armperiph_softc * const sc = device_private(self); 174 struct mainbus_attach_args * const mb = aux; 175 bus_addr_t cbar = armreg_cbar_read(); 176 const struct mpcore_config * const cfg = armperiph_find_config(); 177 prop_dictionary_t prop = device_properties(self); 178 uint32_t cbar_override; 179 180 if (prop_dictionary_get_uint32(prop, "cbar", &cbar_override)) 181 cbar = (bus_addr_t)cbar_override; 182 183 /* 184 * The normal mainbus bus space will not work for us so the port's 185 * device_register must have replaced it with one that will work. 186 */ 187 sc->sc_dev = self; 188 sc->sc_memt = mb->mb_iot; 189 190 int error = bus_space_map(sc->sc_memt, cbar, cfg->cfg_cbar_size, 0, 191 &sc->sc_memh); 192 if (error) { 193 aprint_normal(": error mapping registers at %#lx: %d\n", 194 cbar, error); 195 return; 196 } 197 aprint_normal("\n"); 198 199 /* 200 * Let's try to attach any children we may have. 201 */ 202 for (size_t i = 0; cfg->cfg_devices[i].pi_name[0] != 0; i++) { 203 struct mpcore_attach_args mpcaa = { 204 .mpcaa_name = cfg->cfg_devices[i].pi_name, 205 .mpcaa_memt = sc->sc_memt, 206 .mpcaa_memh = sc->sc_memh, 207 .mpcaa_off1 = cfg->cfg_devices[i].pi_off1, 208 .mpcaa_off2 = cfg->cfg_devices[i].pi_off2, 209 }; 210 if (strcmp(mpcaa.mpcaa_name, "arma9tmr") == 0) { 211 mpcaa.mpcaa_irq = IRQ_A9TMR_PPI_GTIMER; 212 } 213 if (strcmp(mpcaa.mpcaa_name, "armgtmr") == 0) { 214 mpcaa.mpcaa_irq = IRQ_GTMR_PPI_VTIMER; 215 } 216 217 config_found(self, &mpcaa, NULL, CFARGS_NONE); 218 } 219 attached = true; 220 } 221