1 /* $NetBSD: a9tmr.c,v 1.16 2018/06/20 05:01:39 hkenken Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: a9tmr.c,v 1.16 2018/06/20 05:01:39 hkenken Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/kernel.h> 40 #include <sys/proc.h> 41 #include <sys/systm.h> 42 #include <sys/timetc.h> 43 #include <sys/xcall.h> 44 45 #include <prop/proplib.h> 46 47 #include <arm/cortex/a9tmr_reg.h> 48 #include <arm/cortex/a9tmr_var.h> 49 50 #include <arm/cortex/mpcore_var.h> 51 52 static int a9tmr_match(device_t, cfdata_t, void *); 53 static void a9tmr_attach(device_t, device_t, void *); 54 55 static u_int a9tmr_get_timecount(struct timecounter *); 56 57 static struct a9tmr_softc a9tmr_sc; 58 59 static struct timecounter a9tmr_timecounter = { 60 .tc_get_timecount = a9tmr_get_timecount, 61 .tc_poll_pps = 0, 62 .tc_counter_mask = ~0u, 63 .tc_frequency = 0, /* set by cpu_initclocks() */ 64 .tc_name = NULL, /* set by attach */ 65 .tc_quality = 500, 66 .tc_priv = &a9tmr_sc, 67 .tc_next = NULL, 68 }; 69 70 CFATTACH_DECL_NEW(arma9tmr, 0, a9tmr_match, a9tmr_attach, NULL, NULL); 71 72 static inline uint32_t 73 a9tmr_global_read(struct a9tmr_softc *sc, bus_size_t o) 74 { 75 return bus_space_read_4(sc->sc_memt, sc->sc_global_memh, o); 76 } 77 78 static inline void 79 a9tmr_global_write(struct a9tmr_softc *sc, bus_size_t o, uint32_t v) 80 { 81 bus_space_write_4(sc->sc_memt, sc->sc_global_memh, o, v); 82 } 83 84 85 /* ARGSUSED */ 86 static int 87 a9tmr_match(device_t parent, cfdata_t cf, void *aux) 88 { 89 struct mpcore_attach_args * const mpcaa = aux; 90 91 if (a9tmr_sc.sc_dev != NULL) 92 return 0; 93 94 if ((armreg_pfr1_read() & ARM_PFR1_GTIMER_MASK) != 0) 95 return 0; 96 97 if (!CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid) && 98 !CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid)) 99 return 0; 100 101 if (strcmp(mpcaa->mpcaa_name, cf->cf_name) != 0) 102 return 0; 103 104 /* 105 * This isn't present on UP A9s (since CBAR isn't present). 106 */ 107 uint32_t mpidr = armreg_mpidr_read(); 108 if (mpidr == 0 || (mpidr & MPIDR_U)) 109 return 0; 110 111 return 1; 112 } 113 114 static void 115 a9tmr_attach(device_t parent, device_t self, void *aux) 116 { 117 struct a9tmr_softc *sc = &a9tmr_sc; 118 struct mpcore_attach_args * const mpcaa = aux; 119 prop_dictionary_t dict = device_properties(self); 120 char freqbuf[sizeof("XXX SHz")]; 121 const char *cpu_type; 122 123 /* 124 * This runs at the ARM PERIPHCLOCK which should be 1/2 of the CPU clock. 125 * The MD code should have setup our frequency for us. 126 */ 127 if (!prop_dictionary_get_uint32(dict, "frequency", &sc->sc_freq)) { 128 dict = device_properties(parent); 129 prop_dictionary_get_uint32(dict, "frequency", &sc->sc_freq); 130 } 131 132 humanize_number(freqbuf, sizeof(freqbuf), sc->sc_freq, "Hz", 1000); 133 134 aprint_naive("\n"); 135 if (CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid)) { 136 cpu_type = "A5"; 137 } else { 138 cpu_type = "A9"; 139 } 140 aprint_normal(": %s Global 64-bit Timer (%s)\n", cpu_type, freqbuf); 141 142 self->dv_private = sc; 143 sc->sc_dev = self; 144 sc->sc_memt = mpcaa->mpcaa_memt; 145 sc->sc_memh = mpcaa->mpcaa_memh; 146 147 evcnt_attach_dynamic(&sc->sc_ev_missing_ticks, EVCNT_TYPE_MISC, NULL, 148 device_xname(self), "missing interrupts"); 149 150 bus_space_subregion(sc->sc_memt, sc->sc_memh, 151 mpcaa->mpcaa_off1, TMR_GLOBAL_SIZE, &sc->sc_global_memh); 152 153 if (mpcaa->mpcaa_irq != -1) { 154 sc->sc_global_ih = intr_establish(mpcaa->mpcaa_irq, IPL_CLOCK, 155 IST_EDGE | IST_MPSAFE, a9tmr_intr, NULL); 156 if (sc->sc_global_ih == NULL) 157 panic("%s: unable to register timer interrupt", __func__); 158 aprint_normal_dev(sc->sc_dev, "interrupting on irq %d\n", 159 mpcaa->mpcaa_irq); 160 } 161 } 162 163 static inline uint64_t 164 a9tmr_gettime(struct a9tmr_softc *sc) 165 { 166 uint32_t lo, hi; 167 168 do { 169 hi = a9tmr_global_read(sc, TMR_GBL_CTR_U); 170 lo = a9tmr_global_read(sc, TMR_GBL_CTR_L); 171 } while (hi != a9tmr_global_read(sc, TMR_GBL_CTR_U)); 172 173 return ((uint64_t)hi << 32) | lo; 174 } 175 176 void 177 a9tmr_init_cpu_clock(struct cpu_info *ci) 178 { 179 struct a9tmr_softc * const sc = &a9tmr_sc; 180 uint64_t now = a9tmr_gettime(sc); 181 182 KASSERT(ci == curcpu()); 183 184 ci->ci_lastintr = now; 185 186 a9tmr_global_write(sc, TMR_GBL_AUTOINC, sc->sc_autoinc); 187 188 /* 189 * To update the compare register we have to disable comparisions first. 190 */ 191 uint32_t ctl = a9tmr_global_read(sc, TMR_GBL_CTL); 192 if (ctl & TMR_GBL_CTL_CMP_ENABLE) { 193 a9tmr_global_write(sc, TMR_GBL_CTL, 194 ctl & ~TMR_GBL_CTL_CMP_ENABLE); 195 } 196 197 /* 198 * Schedule the next interrupt. 199 */ 200 now += sc->sc_autoinc; 201 a9tmr_global_write(sc, TMR_GBL_CMP_L, (uint32_t) now); 202 a9tmr_global_write(sc, TMR_GBL_CMP_H, (uint32_t) (now >> 32)); 203 204 /* 205 * Re-enable the comparator and now enable interrupts. 206 */ 207 a9tmr_global_write(sc, TMR_GBL_INT, 1); /* clear interrupt pending */ 208 ctl |= TMR_GBL_CTL_CMP_ENABLE | TMR_GBL_CTL_INT_ENABLE | 209 TMR_GBL_CTL_AUTO_INC | TMR_CTL_ENABLE; 210 a9tmr_global_write(sc, TMR_GBL_CTL, ctl); 211 #if 0 212 printf("%s: %s: ctl %#x autoinc %u cmp %#x%08x now %#"PRIx64"\n", 213 __func__, ci->ci_data.cpu_name, 214 a9tmr_global_read(sc, TMR_GBL_CTL), 215 a9tmr_global_read(sc, TMR_GBL_AUTOINC), 216 a9tmr_global_read(sc, TMR_GBL_CMP_H), 217 a9tmr_global_read(sc, TMR_GBL_CMP_L), 218 a9tmr_gettime(sc)); 219 220 int s = splsched(); 221 uint64_t when = now; 222 u_int n = 0; 223 while ((now = a9tmr_gettime(sc)) < when) { 224 /* spin */ 225 n++; 226 KASSERTMSG(n <= sc->sc_autoinc, 227 "spun %u times but only %"PRIu64" has passed", 228 n, when - now); 229 } 230 printf("%s: %s: status %#x cmp %#x%08x now %#"PRIx64"\n", 231 __func__, ci->ci_data.cpu_name, 232 a9tmr_global_read(sc, TMR_GBL_INT), 233 a9tmr_global_read(sc, TMR_GBL_CMP_H), 234 a9tmr_global_read(sc, TMR_GBL_CMP_L), 235 a9tmr_gettime(sc)); 236 splx(s); 237 #elif 0 238 delay(1000000 / hz + 1000); 239 #endif 240 } 241 242 void 243 a9tmr_cpu_initclocks(void) 244 { 245 struct a9tmr_softc * const sc = &a9tmr_sc; 246 247 KASSERT(sc->sc_dev != NULL); 248 KASSERT(sc->sc_freq != 0); 249 250 sc->sc_autoinc = sc->sc_freq / hz; 251 252 a9tmr_init_cpu_clock(curcpu()); 253 254 a9tmr_timecounter.tc_name = device_xname(sc->sc_dev); 255 a9tmr_timecounter.tc_frequency = sc->sc_freq; 256 257 tc_init(&a9tmr_timecounter); 258 } 259 260 static void 261 a9tmr_update_freq_cb(void *arg1, void *arg2) 262 { 263 a9tmr_init_cpu_clock(curcpu()); 264 } 265 266 void 267 a9tmr_update_freq(uint32_t freq) 268 { 269 struct a9tmr_softc * const sc = &a9tmr_sc; 270 uint64_t xc; 271 272 KASSERT(sc->sc_dev != NULL); 273 KASSERT(freq != 0); 274 275 tc_detach(&a9tmr_timecounter); 276 277 sc->sc_freq = freq; 278 sc->sc_autoinc = sc->sc_freq / hz; 279 280 xc = xc_broadcast(0, a9tmr_update_freq_cb, NULL, NULL); 281 xc_wait(xc); 282 283 a9tmr_timecounter.tc_frequency = sc->sc_freq; 284 tc_init(&a9tmr_timecounter); 285 } 286 287 void 288 a9tmr_delay(unsigned int n) 289 { 290 struct a9tmr_softc * const sc = &a9tmr_sc; 291 292 KASSERT(sc != NULL); 293 294 uint32_t freq = sc->sc_freq ? sc->sc_freq : 295 curcpu()->ci_data.cpu_cc_freq / 2; 296 KASSERT(freq != 0); 297 298 /* 299 * not quite divide by 1000000 but close enough 300 * (higher by 1.3% which means we wait 1.3% longer). 301 */ 302 const uint64_t incr_per_us = (freq >> 20) + (freq >> 24); 303 304 const uint64_t delta = n * incr_per_us; 305 const uint64_t base = a9tmr_gettime(sc); 306 const uint64_t finish = base + delta; 307 308 while (a9tmr_gettime(sc) < finish) { 309 /* spin */ 310 } 311 } 312 313 /* 314 * a9tmr_intr: 315 * 316 * Handle the hardclock interrupt. 317 */ 318 int 319 a9tmr_intr(void *arg) 320 { 321 struct clockframe * const cf = arg; 322 struct a9tmr_softc * const sc = &a9tmr_sc; 323 struct cpu_info * const ci = curcpu(); 324 325 const uint64_t now = a9tmr_gettime(sc); 326 uint64_t delta = now - ci->ci_lastintr; 327 328 a9tmr_global_write(sc, TMR_GBL_INT, 1); /* Ack the interrupt */ 329 330 #if 0 331 printf("%s(%p): %s: now %#"PRIx64" delta %"PRIu64"\n", 332 __func__, cf, ci->ci_data.cpu_name, now, delta); 333 #endif 334 KASSERTMSG(delta > sc->sc_autoinc / 64, 335 "%s: interrupting too quickly (delta=%"PRIu64")", 336 ci->ci_data.cpu_name, delta); 337 338 ci->ci_lastintr = now; 339 340 hardclock(cf); 341 342 if (delta > sc->sc_autoinc) { 343 u_int ticks = hz; 344 for (delta -= sc->sc_autoinc; 345 delta >= sc->sc_autoinc && ticks > 0; 346 delta -= sc->sc_autoinc, ticks--) { 347 #if 0 348 /* 349 * Try to make up up to a seconds amount of 350 * missed clock interrupts 351 */ 352 hardclock(cf); 353 #else 354 sc->sc_ev_missing_ticks.ev_count++; 355 #endif 356 } 357 } 358 359 return 1; 360 } 361 362 void 363 setstatclockrate(int newhz) 364 { 365 } 366 367 static u_int 368 a9tmr_get_timecount(struct timecounter *tc) 369 { 370 struct a9tmr_softc * const sc = tc->tc_priv; 371 372 return (u_int) (a9tmr_gettime(sc)); 373 } 374