1 /* $NetBSD: a9tmr.c,v 1.14 2015/07/24 05:20:01 ryo Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: a9tmr.c,v 1.14 2015/07/24 05:20:01 ryo Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/kernel.h> 40 #include <sys/proc.h> 41 #include <sys/systm.h> 42 #include <sys/timetc.h> 43 #include <sys/xcall.h> 44 45 #include <prop/proplib.h> 46 47 #include <arm/cortex/a9tmr_reg.h> 48 #include <arm/cortex/a9tmr_var.h> 49 50 #include <arm/cortex/mpcore_var.h> 51 52 static int a9tmr_match(device_t, cfdata_t, void *); 53 static void a9tmr_attach(device_t, device_t, void *); 54 55 static int clockhandler(void *); 56 57 static u_int a9tmr_get_timecount(struct timecounter *); 58 59 static struct a9tmr_softc a9tmr_sc; 60 61 static struct timecounter a9tmr_timecounter = { 62 .tc_get_timecount = a9tmr_get_timecount, 63 .tc_poll_pps = 0, 64 .tc_counter_mask = ~0u, 65 .tc_frequency = 0, /* set by cpu_initclocks() */ 66 .tc_name = NULL, /* set by attach */ 67 .tc_quality = 500, 68 .tc_priv = &a9tmr_sc, 69 .tc_next = NULL, 70 }; 71 72 CFATTACH_DECL_NEW(a9tmr, 0, a9tmr_match, a9tmr_attach, NULL, NULL); 73 74 static inline uint32_t 75 a9tmr_global_read(struct a9tmr_softc *sc, bus_size_t o) 76 { 77 return bus_space_read_4(sc->sc_memt, sc->sc_global_memh, o); 78 } 79 80 static inline void 81 a9tmr_global_write(struct a9tmr_softc *sc, bus_size_t o, uint32_t v) 82 { 83 bus_space_write_4(sc->sc_memt, sc->sc_global_memh, o, v); 84 } 85 86 87 /* ARGSUSED */ 88 static int 89 a9tmr_match(device_t parent, cfdata_t cf, void *aux) 90 { 91 struct mpcore_attach_args * const mpcaa = aux; 92 93 if (a9tmr_sc.sc_dev != NULL) 94 return 0; 95 96 if ((armreg_pfr1_read() & ARM_PFR1_GTIMER_MASK) != 0) 97 return 0; 98 99 if (!CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid) && 100 !CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid)) 101 return 0; 102 103 if (strcmp(mpcaa->mpcaa_name, cf->cf_name) != 0) 104 return 0; 105 106 /* 107 * This isn't present on UP A9s (since CBAR isn't present). 108 */ 109 uint32_t mpidr = armreg_mpidr_read(); 110 if (mpidr == 0 || (mpidr & MPIDR_U)) 111 return 0; 112 113 return 1; 114 } 115 116 static void 117 a9tmr_attach(device_t parent, device_t self, void *aux) 118 { 119 struct a9tmr_softc *sc = &a9tmr_sc; 120 struct mpcore_attach_args * const mpcaa = aux; 121 prop_dictionary_t dict = device_properties(self); 122 char freqbuf[sizeof("XXX SHz")]; 123 const char *cpu_type; 124 125 /* 126 * This runs at the ARM PERIPHCLOCK which should be 1/2 of the CPU clock. 127 * The MD code should have setup our frequency for us. 128 */ 129 prop_dictionary_get_uint32(dict, "frequency", &sc->sc_freq); 130 131 humanize_number(freqbuf, sizeof(freqbuf), sc->sc_freq, "Hz", 1000); 132 133 aprint_naive("\n"); 134 if (CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid)) { 135 cpu_type = "A5"; 136 } else { 137 cpu_type = "A9"; 138 } 139 aprint_normal(": %s Global 64-bit Timer (%s)\n", cpu_type, freqbuf); 140 141 self->dv_private = sc; 142 sc->sc_dev = self; 143 sc->sc_memt = mpcaa->mpcaa_memt; 144 sc->sc_memh = mpcaa->mpcaa_memh; 145 146 evcnt_attach_dynamic(&sc->sc_ev_missing_ticks, EVCNT_TYPE_MISC, NULL, 147 device_xname(self), "missing interrupts"); 148 149 bus_space_subregion(sc->sc_memt, sc->sc_memh, 150 TMR_GLOBAL_BASE, TMR_GLOBAL_SIZE, &sc->sc_global_memh); 151 bus_space_subregion(sc->sc_memt, sc->sc_memh, 152 TMR_PRIVATE_BASE, TMR_PRIVATE_SIZE, &sc->sc_private_memh); 153 bus_space_subregion(sc->sc_memt, sc->sc_memh, 154 TMR_WDOG_BASE, TMR_WDOG_SIZE, &sc->sc_wdog_memh); 155 156 sc->sc_global_ih = intr_establish(IRQ_A9TMR_PPI_GTIMER, IPL_CLOCK, 157 IST_EDGE | IST_MPSAFE, clockhandler, NULL); 158 if (sc->sc_global_ih == NULL) 159 panic("%s: unable to register timer interrupt", __func__); 160 aprint_normal_dev(sc->sc_dev, "interrupting on irq %d\n", 161 IRQ_A9TMR_PPI_GTIMER); 162 } 163 164 static inline uint64_t 165 a9tmr_gettime(struct a9tmr_softc *sc) 166 { 167 uint32_t lo, hi; 168 169 do { 170 hi = a9tmr_global_read(sc, TMR_GBL_CTR_U); 171 lo = a9tmr_global_read(sc, TMR_GBL_CTR_L); 172 } while (hi != a9tmr_global_read(sc, TMR_GBL_CTR_U)); 173 174 return ((uint64_t)hi << 32) | lo; 175 } 176 177 void 178 a9tmr_init_cpu_clock(struct cpu_info *ci) 179 { 180 struct a9tmr_softc * const sc = &a9tmr_sc; 181 uint64_t now = a9tmr_gettime(sc); 182 183 KASSERT(ci == curcpu()); 184 185 ci->ci_lastintr = now; 186 187 a9tmr_global_write(sc, TMR_GBL_AUTOINC, sc->sc_autoinc); 188 189 /* 190 * To update the compare register we have to disable comparisions first. 191 */ 192 uint32_t ctl = a9tmr_global_read(sc, TMR_GBL_CTL); 193 if (ctl & TMR_GBL_CTL_CMP_ENABLE) { 194 a9tmr_global_write(sc, TMR_GBL_CTL, 195 ctl & ~TMR_GBL_CTL_CMP_ENABLE); 196 } 197 198 /* 199 * Schedule the next interrupt. 200 */ 201 now += sc->sc_autoinc; 202 a9tmr_global_write(sc, TMR_GBL_CMP_L, (uint32_t) now); 203 a9tmr_global_write(sc, TMR_GBL_CMP_H, (uint32_t) (now >> 32)); 204 205 /* 206 * Re-enable the comparator and now enable interrupts. 207 */ 208 a9tmr_global_write(sc, TMR_GBL_INT, 1); /* clear interrupt pending */ 209 ctl |= TMR_GBL_CTL_CMP_ENABLE | TMR_GBL_CTL_INT_ENABLE | 210 TMR_GBL_CTL_AUTO_INC | TMR_CTL_ENABLE; 211 a9tmr_global_write(sc, TMR_GBL_CTL, ctl); 212 #if 0 213 printf("%s: %s: ctl %#x autoinc %u cmp %#x%08x now %#"PRIx64"\n", 214 __func__, ci->ci_data.cpu_name, 215 a9tmr_global_read(sc, TMR_GBL_CTL), 216 a9tmr_global_read(sc, TMR_GBL_AUTOINC), 217 a9tmr_global_read(sc, TMR_GBL_CMP_H), 218 a9tmr_global_read(sc, TMR_GBL_CMP_L), 219 a9tmr_gettime(sc)); 220 221 int s = splsched(); 222 uint64_t when = now; 223 u_int n = 0; 224 while ((now = a9tmr_gettime(sc)) < when) { 225 /* spin */ 226 n++; 227 KASSERTMSG(n <= sc->sc_autoinc, 228 "spun %u times but only %"PRIu64" has passed", 229 n, when - now); 230 } 231 printf("%s: %s: status %#x cmp %#x%08x now %#"PRIx64"\n", 232 __func__, ci->ci_data.cpu_name, 233 a9tmr_global_read(sc, TMR_GBL_INT), 234 a9tmr_global_read(sc, TMR_GBL_CMP_H), 235 a9tmr_global_read(sc, TMR_GBL_CMP_L), 236 a9tmr_gettime(sc)); 237 splx(s); 238 #elif 0 239 delay(1000000 / hz + 1000); 240 #endif 241 } 242 243 void 244 cpu_initclocks(void) 245 { 246 struct a9tmr_softc * const sc = &a9tmr_sc; 247 248 KASSERT(sc->sc_dev != NULL); 249 KASSERT(sc->sc_freq != 0); 250 251 sc->sc_autoinc = sc->sc_freq / hz; 252 253 a9tmr_init_cpu_clock(curcpu()); 254 255 a9tmr_timecounter.tc_name = device_xname(sc->sc_dev); 256 a9tmr_timecounter.tc_frequency = sc->sc_freq; 257 258 tc_init(&a9tmr_timecounter); 259 } 260 261 static void 262 a9tmr_update_freq_cb(void *arg1, void *arg2) 263 { 264 a9tmr_init_cpu_clock(curcpu()); 265 } 266 267 void 268 a9tmr_update_freq(uint32_t freq) 269 { 270 struct a9tmr_softc * const sc = &a9tmr_sc; 271 uint64_t xc; 272 273 KASSERT(sc->sc_dev != NULL); 274 KASSERT(freq != 0); 275 276 tc_detach(&a9tmr_timecounter); 277 278 sc->sc_freq = freq; 279 sc->sc_autoinc = sc->sc_freq / hz; 280 281 xc = xc_broadcast(0, a9tmr_update_freq_cb, NULL, NULL); 282 xc_wait(xc); 283 284 a9tmr_timecounter.tc_frequency = sc->sc_freq; 285 tc_init(&a9tmr_timecounter); 286 } 287 288 void 289 a9tmr_delay(unsigned int n) 290 { 291 struct a9tmr_softc * const sc = &a9tmr_sc; 292 293 KASSERT(sc != NULL); 294 295 uint32_t freq = sc->sc_freq ? sc->sc_freq : 296 curcpu()->ci_data.cpu_cc_freq / 2; 297 KASSERT(freq != 0); 298 299 /* 300 * not quite divide by 1000000 but close enough 301 * (higher by 1.3% which means we wait 1.3% longer). 302 */ 303 const uint64_t incr_per_us = (freq >> 20) + (freq >> 24); 304 305 const uint64_t delta = n * incr_per_us; 306 const uint64_t base = a9tmr_gettime(sc); 307 const uint64_t finish = base + delta; 308 309 while (a9tmr_gettime(sc) < finish) { 310 /* spin */ 311 } 312 } 313 314 /* 315 * clockhandler: 316 * 317 * Handle the hardclock interrupt. 318 */ 319 static int 320 clockhandler(void *arg) 321 { 322 struct clockframe * const cf = arg; 323 struct a9tmr_softc * const sc = &a9tmr_sc; 324 struct cpu_info * const ci = curcpu(); 325 326 const uint64_t now = a9tmr_gettime(sc); 327 uint64_t delta = now - ci->ci_lastintr; 328 329 a9tmr_global_write(sc, TMR_GBL_INT, 1); /* Ack the interrupt */ 330 331 #if 0 332 printf("%s(%p): %s: now %#"PRIx64" delta %"PRIu64"\n", 333 __func__, cf, ci->ci_data.cpu_name, now, delta); 334 #endif 335 KASSERTMSG(delta > sc->sc_autoinc / 64, 336 "%s: interrupting too quickly (delta=%"PRIu64")", 337 ci->ci_data.cpu_name, delta); 338 339 ci->ci_lastintr = now; 340 341 hardclock(cf); 342 343 if (delta > sc->sc_autoinc) { 344 u_int ticks = hz; 345 for (delta -= sc->sc_autoinc; 346 delta >= sc->sc_autoinc && ticks > 0; 347 delta -= sc->sc_autoinc, ticks--) { 348 #if 0 349 /* 350 * Try to make up up to a seconds amount of 351 * missed clock interrupts 352 */ 353 hardclock(cf); 354 #else 355 sc->sc_ev_missing_ticks.ev_count++; 356 #endif 357 } 358 } 359 360 return 1; 361 } 362 363 void 364 setstatclockrate(int newhz) 365 { 366 } 367 368 static u_int 369 a9tmr_get_timecount(struct timecounter *tc) 370 { 371 struct a9tmr_softc * const sc = tc->tc_priv; 372 373 return (u_int) (a9tmr_gettime(sc)); 374 } 375