1 /*- 2 * Copyright (c) 2012 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas of 3am Software Foundry. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #ifndef _ARM_BROADCOM_BCM53XX_REG_H_ 31 #define _ARM_BROADCOM_BCM53XX_REG_H_ 32 33 /* 34 * 0x0000_0000..0x07ff_ffff 128MB DDR2/3 DRAM Memory Region (dual map) 35 * 0x0800_0000..0x0fff_ffff 128MB PCIe 0 Address Match Region 36 * 0x1800_0000..0x180f_ffff 1MB Core Register Region 37 * 0x1810_0000..0x181f_ffff 1MB IDM Register Region 38 * 0x1900_0000..0x190f_ffff 1MB ARMcore (CORTEX-A9) Register Region 39 * 0x1c00_0000..0x1dff_ffff 1MB NAND Flash Region 40 * 0x1e00_0000..0x1dff_ffff 1MB Serial Flash Region 41 * 0x4000_0000..0x47ff_ffff 128MB PCIe 1 Address Match Region 42 * 0x4800_0000..0x4fff_ffff 128MB PCIe 2 Address Match Region 43 * 0x8000_0000..0xbfff_ffff 1024MB DDR2/3 DRAM Memory Region 44 * 0xfffd_0000..0xfffe_ffff 128KB Internal Boot ROM Region 45 * 0xffff_0000..0xffff_043f 1088B Internal SKU ROM Region 46 * 0xffff_1000..0xffff_1fff 4KB Enumeration ROM Register Region 47 */ 48 #define BCM53XX_PCIE0_OWIN_PBASE 0x08000000 49 #define BCM53XX_PCIE0_OWIN_SIZE 0x04000000 50 #define BCM53XX_PCIE0_OWIN_MAX 0x08000000 51 52 #define BCM53XX_IOREG_PBASE 0x18000000 53 #define BCM53XX_IOREG_SIZE 0x00200000 54 55 #define BCM53XX_ARMCORE_PBASE 0x19000000 56 #define BCM53XX_ARMCORE_SIZE 0x00100000 57 58 #define BCM53XX_NAND_PBASE 0x1c000000 59 #define BCM53XX_NAND_SIZE 0x01000000 60 61 #define BCM53XX_SPIFLASH_PBASE 0x1d000000 62 #define BCM53XX_SPIFLASH_SIZE 0x01000000 63 64 #define BCM53XX_PCIE1_OWIN_PBASE 0x40000000 65 #define BCM53XX_PCIE1_OWIN_SIZE 0x04000000 66 #define BCM53XX_PCIE1_OWIN_MAX 0x08000000 67 68 #define BCM53XX_PCIE2_OWIN_PBASE 0x48000000 69 #define BCM53XX_PCIE2_OWIN_SIZE 0x04000000 70 #define BCM53XX_PCIE2_OWIN_MAX 0x08000000 71 72 #define BCM53XX_IO_SIZE (BCM53XX_IOREG_SIZE \ 73 + BCM53XX_ARMCORE_SIZE \ 74 + BCM53XX_PCIE0_OWIN_SIZE \ 75 + BCM53XX_PCIE1_OWIN_SIZE \ 76 + BCM53XX_PCIE2_OWIN_SIZE) 77 78 #define BCM53XX_REF_CLK (25*1000*1000) 79 80 #define CCA_UART_FREQ BCM53XX_REF_CLK 81 82 /* Chip Common A */ 83 #define CCA_MISC_BASE 0x000000 84 #define CCA_MISC_SIZE 0x001000 85 #define CCA_UART0_BASE 0x000300 86 #define CCA_UART1_BASE 0x000400 87 88 /* Chip Common B */ 89 #define CCB_BASE 0x000000 90 #ifdef BCM5301X 91 #define CCB_SIZE 0x030000 92 #define PWM_BASE 0x002000 93 #define MII_BASE 0x003000 94 #define RNG_BASE 0x004000 95 #define TIMER0_BASE 0x005000 96 #define TIMER1_BASE 0x006000 97 #define SRAB_BASE 0x007000 98 #define UART2_BASE 0x008000 99 #define SMBUS1_BASE 0x009000 100 101 #define CRU_BASE 0x00b000 102 #define DMU_BASE 0x00c000 103 #elif defined(BCM563XX) 104 #define CCB_SIZE 0x040000 105 #define GPIO_BASE 0x030000 106 #define PWM_BASE 0x031000 107 #define MII_BASE 0x032000 108 #define RNG_BASE 0x033000 109 #define TIMER0_BASE 0x034000 110 #define TIMER1_BASE 0x035000 111 #define UART2_BASE 0x037000 112 #define SMBUS0_BASE 0x038000 113 #define WDT_BASE 0x039000 114 #define PKA_BASE 0x03a000 115 #define SMBUS1_BASE 0x03b000 116 117 #define CRU_BASE 0x03e000 118 #define DMU_BASE 0x03f000 119 #endif 120 121 #define DDR_BASE 0x010000 122 123 #define PCIE0_BASE 0x012000 124 #define PCIE1_BASE 0x013000 125 126 #ifdef BCM5301X 127 #define PCIE2_BASE 0x014000 128 #define SDIO_BASE 0x020000 129 #define EHCI_BASE 0x021000 130 #define OHCI_BASE 0x022000 131 #define GMAC0_BASE 0x024000 132 #define GMAC1_BASE 0x025000 133 #define GMAC2_BASE 0x026000 134 #define GMAC3_BASE 0x027000 135 #define NAND_BASE 0x028000 136 #define QSPI_BASE 0x029000 137 #define I2S_BASE 0x02A000 138 #define DMAC_BASE 0x02C000 139 #endif 140 141 #ifdef BCM563XX 142 #define DMAC_BASE 0x020000 143 #define GMAC0_BASE 0x022000 144 #define GMAC1_BASE 0x023000 145 #define NAND_BASE 0x026000 146 #define QSPI_BASE 0x027000 147 #define EHCI_BASE 0x02A000 148 #define OHCI_BASE 0x02B000 149 #endif 150 151 #define IDM_BASE 0x100000 152 #define IDM_SIZE 0x100000 153 154 /* Chip Common A */ 155 156 #ifdef CCA_PRIVATE 157 158 #define MISC_CHIPID 0x000 159 #define CHIPID_REV __BITS(19,16) 160 #define CHIPID_ID __BITS(15,0) 161 #define ID_BCM53010 0xcf12 // 53010 162 #define ID_BCM53011 0xcf13 // 53011 163 #define ID_BCM53012 0xcf14 // 53012 164 #define ID_BCM53013 0xcf15 // 53013 165 #define ID_BCM56340 0xdc14 // 56340 166 167 #define MISC_CAPABILITY 0x004 168 #define CAPABILITY_JTAG_PRESENT __BIT(22) 169 #define CAPABILITY_UART_CLKSEL __BITS(4,3) 170 #define UART_CLKSEL_REFCLK 0 171 #define UART_CLKSEL_INTCLK 1 172 /* 2 & 3 are reserved */ 173 #define CAPABILITY_BIG_ENDIAN __BIT(2) 174 #define CAPABILITY_UART_COUNT __BITS(1,0) 175 176 #define MISC_CORECTL 0x008 177 #define CORECTL_UART_CLK_EN __BIT(3) 178 #define CORECTL_GPIO_ASYNC_INT_EN __BIT(2) 179 #define CORECTL_UART_CLK_OVERRIDE __BIT(0) 180 181 #define MISC_INTSTATUS 0x020 182 #define INTSTATUS_WDRESET __BIT(31) // WO2C 183 #define INTSTATUS_UARTINT __BIT(6) // RO 184 #define INTSTATUS_GPIOINT __BIT(0) // RO 185 186 #define MISC_INTMASK 0x024 187 #define INTMASK_UARTINT __BIT(6) // 1 = enabled 188 #define INTMASK_GPIOINT __BIT(0) // 1 = enabled 189 190 /* Only bits [23:0] are used in the GPIO registers */ 191 #define GPIO_INPUT 0x060 // RO 192 #define GPIO_OUT 0x064 193 #define GPIO_OUTEN 0x068 194 #define GPIO_INTPOLARITY 0x070 // 1 = active low 195 #define GPIO_INTMASK 0x074 // 1 = enabled (level) 196 #define GPIO_EVENT 0x078 // W1C, 1 = edge seen 197 #define GPIO_EVENT_INTMASK 0x07c // 1 = enabled (edge) 198 #define GPIO_EVENT_INTPOLARITY 0x084 // 1 = falling 199 #define GPIO_TIMER_VAL 0x088 200 #define TIMERVAL_ONCOUNT __BITS(31,16) 201 #define TIMERVAL_OFFCOUNT __BITS(15,0) 202 #define GPIO_TIMER_OUTMASK 0x08c 203 #define GPIO_DEBUG_SEL 0x0a8 204 205 #define MISC_WATCHDOG 0x080 // 0 disables, 1 resets 206 207 #define MISC_CLKDIV 0x0a4 208 #define CLKDIV_JTAG_MASTER_CLKDIV __BITS(13,9) 209 #define CLKDIV_UART_CLKDIV __BITS(7,1) 210 211 #define MISC_CAPABILITY2 0x0ac 212 #define CAPABILITY2_GSIO_PRESENT __BIT(1) // SPI exists 213 214 #define MISC_GSIOCTL 0x0e4 215 #define GSIOCTL_STARTBUSY __BIT(31) 216 #define GSIOCTL_GSIOMODE __BIT(30) // 0 = SPI 217 #define GSIOCTL_ERROR __BIT(23) 218 #define GSIOCTL_BIGENDIAN __BIT(22) 219 #define GSIOCTL_GSIOGO __BIT(21) 220 #define GSIOCTL_NUM_DATABYTES __BITS(17,16) // actual is + 1 221 #define GSIOCTL_NUM_WAITCYCLES __BITS(15,14) // actual is + 1 222 #define GSIOCTL_NUM_ADDRESSBYTES __BITS(13,12) // actual is + 1 223 #define GSIOCTL_GSIOCODE __BITS(10,8) 224 #define GSIOCODE_OP_RD1DATA 0 225 #define GSIOCODE_OP_WRADDR_RDADDR 1 226 #define GSIOCODE_OP_WRADDR_XFRDATA 2 227 #define GSIOCODE_OP_WRADDR_WAIT_XFRDATA 3 228 #define GSIOCODE_XFRDATA 4 229 #define GSIOCTL_GSIOOP __BITS(7,0) 230 231 #define MISC_GSIOADDRESS 0x0e8 232 #define MISC_GSIODATA 0x0ec 233 234 #define MISC_CLKDIV2 0x0f0 235 #define CLKDIV2_GSIODIV __BITS(20,5) 236 237 #define MISC_EROM_PTR_OFFSET 0x0fc 238 239 #endif /* CCA_PRIVATE */ 240 241 /* 242 * UART0 & 1 use the standard 16550 register layout (normal 1 byte stride) 243 * and have 64-byte FIFOs 244 */ 245 246 /* TIMER0 & 1 are implemented by the dtimer driver */ 247 248 #define TIMER_FREQ BCM53XX_REF_CLK 249 250 #ifdef SRAB_PRIVATE 251 #define SRAB_CMDSTAT 0x002c 252 #define SRA_PAGE __BITS(31,24) 253 #define SRA_OFFSET __BITS(23,16) 254 #define SRA_PAGEOFFSET __BITS(31,16) 255 #define SRA_RST __BIT(2) 256 #define SRA_WRITE __BIT(1) 257 #define SRA_GORDYN __BIT(0) 258 #define SRAB_WDH 0x0030 259 #define SRAB_WDL 0x0034 260 #define SRAB_RDH 0x0038 261 #define SRAB_RDL 0x003c 262 #endif 263 264 #ifdef MII_PRIVATE 265 #define MII_INTERNAL 0x0038003 /* internal phy bitmask */ 266 #define MIIMGT 0x000 267 #define MIIMGT_BYP __BIT(10) 268 #define MIIMGT_EXT __BIT(9) 269 #define MIIMGT_BSY __BIT(8) 270 #define MIIMGT_PRE __BIT(7) 271 #define MIIMGT_MDCDIV __BITS(6,0) 272 #define MIICMD 0x004 273 #define MIICMD_SB __BITS(31,30) 274 #define MIICMD_SB_DEF __SHIFTIN(1, MIICMD_SB) 275 #define MIICMD_OP __BITS(29,28) 276 #define MIICMD_OP_RD __SHIFTIN(2, MIICMD_OP) 277 #define MIICMD_OP_WR __SHIFTIN(1, MIICMD_OP) 278 #define MIICMD_PHY __BITS(27,23) 279 #define MIICMD_REG __BITS(22,18) 280 #define MIICMD_TA __BITS(17,16) 281 #define MIICMD_TA_DEF __SHIFTIN(2, MIICMD_TA) 282 #define MIICMD_DATA __BITS(15,0) 283 284 #define MIICMD_RD_DEF (MIICMD_SB_DEF|MIICMD_OP_RD|MIICMD_TA_DEF) 285 #define MIICMD_WR_DEF (MIICMD_SB_DEF|MIICMD_OP_WR|MIICMD_TA_DEF) 286 #define MIICMD__PHYREG(p,r) (__SHIFTIN(p,MIICMD_PHY)|__SHIFTIN(r,MIICMD_REG)) 287 #define MIICMD_RD(p,r) (MIICMD_RD_DEF|MIICMD__PHYREG((p),(r))) 288 #define MIICMD_WR(p,r,v) (MIICMD_WR_DEF|MIICMD__PHYREG((p),(r))|(v)) 289 #endif /* MII_PRIVATE */ 290 291 #ifdef RNG_PRIVATE 292 #define RNG_CTRL 0x000 293 #define RNG_COMBLK2_OSC_DIS __BITS(27,22) 294 #define RNG_COMBLK1_OSC_DIS __BITS(21,16) 295 #define RNG_ICLK_BYP_DIV_CNT __BITS(15,8) 296 #define RNG_JCLK_BYP_SRC __BIT(5) 297 #define RNG_JCLK_BYP_SEL __BIT(4) 298 #define RNG_RBG2X __BIT(1) 299 #define RNG_RBGEN __BIT(0) 300 #define RNG_STATUS 0x004 301 #define RNG_VAL __BITS(31,24) 302 #define RNG_WARM_CNT __BITS(19,0) 303 304 #define RNG_DATA 0x008 305 #define RNG_FF_THRESHOLD 0x00c 306 #define RNG_INT_MASK 0x010 307 #define RNG_INT_OFF __BIT(0) 308 #endif /* RNG_PRIVATE */ 309 310 #ifdef UART2_PRIVATE 311 /* 312 * UART2 (ChipCommonB) uses a 4-byte stride and 16-byte FIFO. 313 * Its frequency is the APB clock. 314 */ 315 #define UART2_LPDLL 0x020 316 #define UART2_LPDLH 0x024 317 #endif 318 319 #ifdef CRU_PRIVATE 320 321 #define CRU_CONTROL 0x000 322 #define CRUCTL_QSPI_CLK_SEL __BITS(2,1) 323 #define QSPI_CLK_25MHZ 0 // iproc_ref_clk 324 #define QSPI_CLK_50MHZ 1 // iproc_sdio_clk / 4 325 #define QSPI_CLK_31dot25MHZ 2 // iproc_clk250 / 8 326 #define QSPI_CLK_62dot5MHZ 3 // iproc_clk250 / 4 327 #define CRUCTL_SW_RESET __BIT(0) 328 329 #define CRU_GENPLL_CONTROL5 0x1154 330 #define GENPLL_CONTROL5_NDIV_INT __BITS(29,20) // = (n ? n : 1024) 331 #define GENPLL_CONTROL5_NDIV_FRAC __BITS(19,0) // = 1 / n 332 #define CRU_GENPLL_CONTROL6 0x1158 333 #define GENPLL_CONTROL6_PDIV __BITS(26,24) // = (n ? n : 8) 334 #define GENPLL_CONTROL6_CH0_MDIV __BITS(23,16) // = (n ? n : 256), clk_mac 335 #define GENPLL_CONTROL6_CH1_MDIV __BITS(15,8) // = (n ? n : 256), clk_robo 336 #define GENPLL_CONTROL6_CH2_MDIV __BITS(7,0) // = (n ? n : 256), clf_usb2 337 #define CRU_GENPLL_CONTROL7 0x115c 338 #define GENPLL_CONTROL7_CH3_MDIV __BITS(23,16) // = (n ? n : 256), clk_iproc 339 340 #define USB2_REF_CLK (1920*1000*1000) 341 #define CRU_USB2_CONTROL 0x1164 342 #define USB2_CONTROL_KA __BITS(24,22) 343 #define USB2_CONTROL_KI __BITS(31,19) 344 #define USB2_CONTROL_KP __BITS(18,15) 345 #define USB2_CONTROL_PDIV __BITS(14,12) // = (n ? n : 8) 346 #define USB2_CONTROL_NDIV_INT __BITS(11,2) // = (n ? n : 1024) 347 #define USB2_CONTROL_PLL_PCIEUSB3_RESET __BIT(1) // inverted 1=normal 348 #define USB2_CONTROL_PLL_USB2_RESET __BIT(0) // inverted 1=normal 349 350 #define CRU_CLKSET_KEY 0x1180 351 #define CRU_CLKSET_KEY_MAGIC 0xea68 352 353 #define CRU_GPIO_SELECT 0x11c0 // CRU GPIO Select 354 #define CRU_GPIO_DRIVE_SEL2 0x11c4 355 #define CRU_GPIO_DRIVE_SEL1 0x11c8 356 #define CRU_GPIO_DRIVE_SEL0 0x11cc 357 #define CRU_GPIO_INPUT_DISABLE 0x11d0 358 #define CRU_GPIO_HYSTERESIS 0x11d4 359 #define CRU_GPIO_SLEW_RATE 0x11d8 360 #define CRU_GPIO_PULL_UP 0x11dc 361 #define CRU_GPIO_PULL_DOWN 0x11e0 362 363 #define CRU_STRAPS_CONTROL 0x12a0 364 #define STRAP_BOOT_DEV __BITS(17,16) 365 #define STRAP_NAND_TYPE __BITS(15,12) 366 #define STRAP_NAND_PAGE __BITS(11,10) 367 #define STRAP_DDR3 __BIT(9) 368 #define STRAP_P5_VOLT_15 __BIT(8) 369 #define STRAP_P5_MODE __BITS(7,6) 370 #define STRAP_PCIE0_MODE __BIT(5) 371 #define STRAP_USB3_SEL __BIT(4) 372 #define STRAP_EX_EXTCLK __BIT(3) 373 #define STRAP_HW_FWDG_EN __BIT(2) 374 #define STRAP_LED_SERIAL_MODE __BIT(1) 375 #define STRAP_BISR_BYPASS_AUTOLOAD __BIT(0) 376 377 #endif /* CRU_PRIVATE */ 378 379 #ifdef DMU_PRIVATE 380 381 #define DMU_LCPLL_CONTROL0 0x100 382 #define DMU_LCPLL_CONTROL1 0x104 383 #define LCPLL_CONTROL1_PDIV __BITS(30,28) // = (n ? n : 8) 384 #define LCPLL_CONTROL1_NDIV_INT __BITS(27,20) // = (n ? n : 256) 385 #define LCPLL_CONTROL1_NDIV_FRAC __BITS(19,0) // = 1 / n 386 /* 387 * SYS_CLK = (1 / pdiv) * (ndiv_int + (ndiv_frac / 0x40000000)) x F(ref) 388 */ 389 #define DMU_LCPLL_CONTROL2 0x108 390 #define LCPLL_CONTROL2_CH0_MDIV __BITS(31,24) // = (n ? n : 256), clk_pcie_ref 391 #define LCPLL_CONTROL2_CH1_MDIV __BITS(23,16) // = (n ? n : 256), clk_sdio 392 #define LCPLL_CONTROL2_CH2_MDIV __BITS(15,8) // = (n ? n : 256), clk_ddr 393 #define LCPLL_CONTROL2_CH3_MDIV __BITS(7,0) // = (n ? n : 256), clf_dft 394 395 #define DMU_CRU_RESET 0x200 396 #define DMU_CRU_RESET_IPROC __BIT(1) 397 #define DMU_CRU_RESET_CMICD __BIT(0) 398 399 #endif /* DMU_PRIVATE */ 400 401 #ifdef DDR_PRIVATE 402 /* 403 * DDR CTL register has such inspired names. 404 */ 405 #define DDR_CTL_01 0x004 406 #define CTL_01_MAX_CHIP_SEL __BITS(18,16) // not documented as such 407 #define CTL_01_MAX_COL __BITS(11,8) 408 #define CTL_01_MAX_ROW __BITS(4,0) 409 410 #define DDR_CTL_82 0x148 411 #define CTL_82_COL_DIFF __BITS(26,24) 412 #define CTL_82_ROW_DIFF __BITS(18,16) 413 #define CTL_82_BANK_DIFF __BITS(9,8) 414 #define CTL_82_ZQCS_ROTATE __BIT(0) 415 416 #define DDR_CTL_86 0x158 417 #define CTL_86_CS_MAP __BITS(27,24) 418 #define CTL_86_INHIBIT_DRAM_CMD __BIT(16) 419 #define CTL_86_DIS_RD_INTRLV __BIT(8) 420 #define CTL_86_NUM_QENT_ACT_DIS __BITS(2,0) 421 422 #define DDR_CTL_87 0x15c 423 #define CTL_87_IN_ORDER_ACCEPT __BIT(24) 424 #define CTL_87_Q_FULLNESS __BITS(18,16) 425 #define CTL_87_REDUC __BIT(8) 426 #define CTL_87_BURST_ON_FLY_BIT __BITS(3,0) 427 428 #define DDR_PHY_CTL_PLL_STATUS 0x810 429 #define PLL_STATUS_LOCK_LOST __BIT(26) 430 #define PLL_STATUS_MHZ __BITS(25,14) 431 #define PLL_STATUS_CLOCKING_4X __BIT(13) 432 #define PLL_STATUS_STATUS __BITS(12,1) 433 #define PLL_STATUS_LOCK __BIT(0) 434 435 #define DDR_PHY_CTL_PLL_DIVIDERS 0x81c 436 #define PLL_DIVIDERS_POST_DIV __BITS(13,11) 437 #define PLL_DIVIDERS_PDIV __BITS(10,8) // 4x: (n ? n : 8), n = n - 4, 4x 438 #define PLL_DIVIDERS_NDIV __BITS(7,0) 439 440 #endif /* DDR_PRIVATE */ 441 442 #ifdef PCIE_PRIVATE 443 444 #define PCIE_CLK_CONTROL 0x000 445 446 #define PCIE_RC_AXI_CONFIG 0x100 447 #define PCIE_AWCACHE_CONFIG __BITS(17,14) 448 #define PCIE_AWUSER_CONFIG __BITS(13,9) 449 #define PCIE_ARCACHE_CONFIG __BITS(8,5) 450 #define PCIE_ARUSER_CONFIG __BITS(4,0) 451 452 #define PCIE_CFG_IND_ADDR 0x120 453 #define CFG_IND_ADDR_FUNC __BITS(15,13) 454 #define CFG_IND_ADDR_LAYER __BITS(12,11) 455 #define CFG_IND_ADDR_REG __BITS(10,2) 456 #define PCIE_CFG_IND_DATA 0x124 457 #define PCIE_CFG_ADDR 0x1f8 458 #define CFG_ADDR_BUS __BITS(27,20) 459 #define CFG_ADDR_DEV __BITS(19,15) 460 #define CFG_ADDR_FUNC __BITS(14,12) 461 #define CFG_ADDR_REG __BITS(11,2) 462 #define CFG_ADDR_TYPE __BITS(1,0) 463 #define CFG_ADDR_TYPE0 __SHIFTIN(0, CFG_ADDR_TYPE) 464 #define CFG_ADDR_TYPE1 __SHIFTIN(1, CFG_ADDR_TYPE) 465 #define PCIE_CFG_DATA 0x1fc 466 #define PCIE_EQ_PAGE 0x200 467 #define PCIE_MSI_PAGE 0x204 468 #define PCIE_MSI_INTR_EN 0x208 469 #define PCIE_MSI_CTRL_0 0x210 470 #define PCIE_MSI_CTRL_1 0x214 471 #define PCIE_MSI_CTRL_2 0x218 472 #define PCIE_MSI_CTRL_3 0x21c 473 #define PCIE_MSI_CTRL_4 0x220 474 #define PCIE_MSI_CTRL_5 0x224 475 #define PCIE_SYS_EQ_HEAD_0 0x250 476 #define PCIE_SYS_EQ_TAIL_0 0x254 477 #define PCIE_SYS_EQ_HEAD_1 0x258 478 #define PCIE_SYS_EQ_TAIL_1 0x25c 479 #define PCIE_SYS_EQ_HEAD_2 0x260 480 #define PCIE_SYS_EQ_TAIL_2 0x264 481 #define PCIE_SYS_EQ_HEAD_3 0x268 482 #define PCIE_SYS_EQ_TAIL_3 0x26c 483 #define PCIE_SYS_EQ_HEAD_4 0x270 484 #define PCIE_SYS_EQ_TAIL_4 0x274 485 #define PCIE_SYS_EQ_HEAD_5 0x278 486 #define PCIE_SYS_EQ_TAIL_5 0x27c 487 #define PCIE_SYS_RC_INTX_EN 0x330 488 #define PCIE_SYS_RC_INTX_CSR 0x334 489 490 #define PCIE_CFG000_BASE 0x400 491 492 #define PCIE_FUNC0_IMAP0_0 0xc00 493 #define PCIE_FUNC0_IMAP0_1 0xc04 494 #define PCIE_FUNC0_IMAP0_2 0xc08 495 #define PCIE_FUNC0_IMAP0_3 0xc0c 496 #define PCIE_FUNC0_IMAP0_4 0xc10 497 #define PCIE_FUNC0_IMAP0_5 0xc14 498 #define PCIE_FUNC0_IMAP0_6 0xc18 499 #define PCIE_FUNC0_IMAP0_7 0xc1c 500 501 #define PCIE_FUNC0_IMAP1 0xc80 502 #define PCIE_FUNC1_IMAP1 0xc88 503 #define PCIE_FUNC0_IMAP2 0xcc0 504 #define PCIE_FUNC1_IMAP2 0xcc8 505 506 #define PCIE_IARR_0_LOWER 0xd00 507 #define PCIE_IARR_0_UPPER 0xd04 508 #define PCIE_IARR_1_LOWER 0xd08 509 #define PCIE_IARR_1_UPPER 0xd0c 510 #define PCIE_IARR_2_LOWER 0xd10 511 #define PCIE_IARR_2_UPPER 0xd14 512 513 #define PCIE_OARR_0 0xd20 514 #define PCIE_OARR_1 0xd28 515 516 #define PCIE_OARR_ADDR __BITS(31,26) 517 518 #define PCIE_OMAP_0_LOWER 0xd40 519 #define PCIE_OMAP_0_UPPER 0xd44 520 #define PCIE_OMAP_1_LOWER 0xd48 521 #define PCIE_OMAP_1_UPPER 0xd4c 522 523 #define PCIE_OMAP_ADDRL __BITS(31,26) 524 525 #define PCIE_FUNC1_IARR_1_SIZE 0xd58 526 #define PCIE_FUNC1_IARR_2_SIZE 0xd5c 527 528 #define PCIE_MEM_CONTROL 0xf00 529 #define PCIE_MEM_ECC_ERR_LOG_0 0xf04 530 #define PCIE_MEM_ECC_ERR_LOG_1 0xf08 531 532 #define PCIE_LINK_STATUS 0xf0c 533 #define PCIE_PHYLINKUP __BIT(3) 534 #define PCIE_DL_ACTIVE __BIT(2) 535 #define PCIE_RX_LOS_TIMEOUT __BIT(1) 536 #define PCIE_LINK_IN_L1 __BIT(0) 537 #define PCIE_STRAP_STATUS 0xf10 538 #define STRAP_PCIE_REPLAY_BUF_TM __BITS(8,4) 539 #define STRAP_PCIE_USER_FOR_CE_GEN1 __BIT(3) 540 #define STRAP_PCIE_USER_FOR_CE_1LANE __BIT(2) 541 #define STRAP_PCIE_IF_ENABLE __BIT(1) 542 #define STRAP_PCIE_USER_RC_MODE __BIT(0) 543 #define PCIE_RESET_STATUS 0xf14 544 545 #define PCIE_RESET_ENABLE_IN_PCIE_LINK_DOWN 0xf18 546 547 #define PCIE_MISC_INTR_EN 0xf1c 548 #define PCIE_TX_DEBUG_CFG 0xf20 549 #define PCIE_ERROR_INTR_EN 0xf30 550 #define PCIE_ERROR_INTR_CLR 0xf34 551 #define PCIE_ERROR_INTR_STS 0xf38 552 553 554 // PCIE_SYS_MSI_INTR_EN 555 #define MSI_INTR_EN_EQ_5 __BIT(5) 556 #define MSI_INTR_EN_EQ_4 __BIT(4) 557 #define MSI_INTR_EN_EQ_3 __BIT(3) 558 #define MSI_INTR_EN_EQ_2 __BIT(2) 559 #define MSI_INTR_EN_EQ_1 __BIT(1) 560 #define MSI_INTR_EN_EQ_0 __BIT(0) 561 562 // PCIE_SYS_MSI_CTRL<n> 563 #define INT_N_DELAY __BITS(9,6) 564 #define INT_N_EVENT __BITS(1,1) 565 #define EQ_ENABLE __BIT(0) 566 567 // PCIE_SYS_EQ_HEAD<n> 568 #define HEAD_PTR __BITS(5,0) 569 570 // PCIE_SYS_EQ_TAIL<n> 571 #define EQ_OVERFLOW __BIT(6) 572 #define TAIL_PTR __BITS(5,0) 573 574 // PCIE_SYS_RC_INTRX_EN 575 #define RC_EN_INTD __BIT(3) 576 #define RC_EN_INTC __BIT(2) 577 #define RC_EN_INTB __BIT(1) 578 #define RC_EN_INTA __BIT(0) 579 580 // PCIE_SYS_RC_INTRX_CSR 581 #define RC_INTD __BIT(3) 582 #define RC_INTC __BIT(2) 583 #define RC_INTB __BIT(1) 584 #define RC_INTA __BIT(0) 585 586 // PCIE_IARR_0_LOWER / UPPER 587 #define IARR0_ADDR __BIT(31,15) 588 #define IARR0_VALID __BIT(0) 589 590 // PCIE_IARR_1_LOWER / UPPER 591 #define IARR1_ADDR __BIT(31,20) 592 #define IARR1_SIZE __BIT(7,0) 593 594 // PCIE_IARR_2_LOWER / UPPER 595 #define IARR2_ADDR __BIT(31,20) 596 #define IARR2_SIZE __BIT(7,0) 597 598 // PCIE_MISC_INTR_EN 599 #define INTR_EN_PCIE_ERR_ATTN __BIT(2) 600 #define INTR_EN_PAXB_ECC_2B_ATTN __BIT(1) 601 #define INTR_EN_PCIE_IN_WAKE_B __BIT(0) 602 603 // PCIE_ERR_INTR_{EN,CLR,STS} 604 #define PCIE_OVERFLOW_UNDERFLOW_INTR __BIT(10) 605 #define PCIE_AXI_MASTER_RRESP_SLV_ERR_INTR __BIT(9) 606 #define PCIE_AXI_MASTER_RRESP_DECERR_INTR __BIT(8) 607 #define PCIE_ECRC_ERR_INTR __BIT(7) 608 #define PCIE_CMPL_TIMEROUT_INTR __BIT(6) 609 #define PCIE_ERR_ATTN_INTR __BIT(5) 610 #define PCIE_IN_WAKE_B_INTR __BIT(4) 611 #define PCIE_REPLAY_BUF_2B_ECC_ERR_INTR __BIT(3) 612 #define PCIE_RD_CMPL_BUF_1_2B_ECC_ERR_INTR __BIT(2) 613 #define PCIE_RD_CMPL_BUF_0_2B_ECC_ERR_INTR __BIT(1) 614 #define PCIE_WR_DATA_BUF_2B_ECC_ERR_INTR __BIT(0) 615 616 #define REGS_DEVICE_CAPACITY 0x04d4 617 #define REGS_LINK_CAPACITY 0x03dc 618 #define REGS_TL_CONTROL_0 0x0800 619 #define REGS_DL_STATUS 0x1048 620 621 #endif /* PCIE_PRIVATE */ 622 623 #define ARMCORE_SCU_BASE 0x20000 /* CBAR is 19020000 */ 624 #define ARMCORE_L2C_BASE 0x22000 625 626 #ifdef ARMCORE_PRIVATE 627 628 #define ARMCORE_CLK_POLICY_FREQ 0x008 629 #define CLK_POLICY_FREQ_PRIVED __BIT(31) 630 #define CLK_POLICY_FREQ_POLICY3 __BITS(26,24) 631 #define CLK_POLICY_FREQ_POLICY2 __BITS(18,16) 632 #define CLK_POLICY_FREQ_POLICY1 __BITS(10,8) 633 #define CLK_POLICY_FREQ_POLICY0 __BITS(2,0) 634 #define CLK_POLICY_REF_CLK 0 // 25 MHZ 635 #define CLK_POLICY_SYS_CLK 1 // sys clk (200MHZ) 636 #define CLK_POLICY_ARM_PLL_CH0 6 // slow clock 637 #define CLK_POLICY_ARM_PLL_CH1 7 // fast clock 638 639 #define ARMCORE_CLK_APB_DIV 0xa10 640 #define CLK_APB_DIV_PRIVED __BIT(31) 641 #define CLK_APB_DIV_VALUE __BITS(1,0) // n = n + 1 642 643 #define ARMCORE_CLK_APB_DIV_TRIGGER 0xa10 644 #define CLK_APB_DIV_TRIGGER_PRIVED __BIT(31) 645 #define CLK_APB_DIV_TRIGGER_OVERRIDE __BIT(0) 646 647 #define ARMCORE_CLK_PLLARMA 0xc00 648 #define CLK_PLLARMA_PDIV __BITS(26,24) // = (n ? n : 16(?)) 649 #define CLK_PLLARMA_NDIV_INT __BITS(17,8) // = (n ? n : 1024) 650 651 #define ARMCORE_CLK_PLLARMB 0xc04 652 #define CLK_PLLARMB_NDIV_FRAC __BITS(19,0) // = 1 / n 653 654 #endif 655 656 #ifdef IDM_PRIVATE 657 658 #define IDM_ARMCORE_M0_BASE 0x00000 659 #define IDM_PCIE_M0_BASE 0x01000 660 #define IDM_PCIE_M1_BASE 0x02000 661 #define IDM_PCIE_M2_BASE 0x03000 662 #define IDM_USB3_BASE 0x05000 663 #define IDM_ARMCORE_S1_BASE 0x06000 664 #define IDM_ARMCORE_S0_BASE 0x07000 665 #define IDM_DDR_S1_BASE 0x08000 666 #define IDM_DDR_S2_BASE 0x09000 667 #define IDM_ROM_S0_BASE 0x0d000 668 #define IDM_AMAC0_BASE 0x10000 669 #define IDM_AMAC1_BASE 0x11000 670 #define IDM_AMAC2_BASE 0x12000 671 #define IDM_AMAC3_BASE 0x13000 672 #define IDM_DMAC_M0_BASE 0x14000 673 #define IDM_USB2_BASE 0x15000 674 #define IDM_SDIO_BASE 0x16000 675 #define IDM_I2S_M0_BASE 0x17000 676 #define IDM_A9JTAG_M0_BASE 0x18000 677 #ifdef BCM5301X 678 #define IDM_NAND_BASE 0x1a000 679 #define IDM_QSPI_BASE 0x1b000 680 #endif 681 #ifdef BCM563XX 682 #define IDM_NAND_BASE 0x1b000 683 #define IDM_QSPI_BASE 0x1c000 684 #endif 685 #define IDM_APBX_BASE 0x21000 686 687 #define IDM_IO_CONTROL_DIRECT 0x0408 688 #define IDM_IO_STATUS 0x0500 689 #define IDM_RESET_CONTROL 0x0800 690 #define IDM_RESET_STATUS 0x0804 691 #define IDM_INTERRUPT_STATUS 0x0a00 692 693 #define IO_CONTROL_DIRECT_ARUSER __BITS(29,25) 694 #define IO_CONTROL_DIRECT_AWUSER __BITS(24,20) 695 #define IO_CONTROL_DIRECT_ARCACHE __BITS(19,16) 696 #define IO_CONTROL_DIRECT_AWCACHE __BITS(10,7) 697 #define AXCACHE_WA __BIT(3) 698 #define AXCACHE_RA __BIT(2) 699 #define AXCACHE_C __BIT(1) 700 #define AXCACHE_B __BIT(0) 701 #define IO_CONTROL_DIRECT_UARTCLKSEL __BIT(17) 702 #define IO_CONTROL_DIRECT_CLK_250_SEL __BIT(6) 703 #define IO_CONTROL_DIRECT_DIRECT_GMII_MODE __BIT(5) 704 #define IO_CONTROL_DIRECT_TX_CLK_OUT_INVERT_EN __BIT(4) 705 #define IO_CONTROL_DIRECT_DEST_SYNC_MODE_EN __BIT(3) 706 #define IO_CONTROL_DIRECT_SOURCE_SYNC_MODE_EN __BIT(2) 707 #define IO_CONTROL_DIRECT_CLK_GATING_EN __BIT(0) 708 709 #define RESET_CONTROL_RESET __BIT(0) 710 711 #endif /* IDM_PRIVATE */ 712 713 #ifdef USBH_PRIVATE 714 #define USBH_PHY_CTRL_P0 0x200 715 #define USBH_PHY_CTRL_P1 0x204 716 717 #define USBH_PHY_CTRL_INIT 0x3ff 718 #endif 719 720 #ifdef GMAC_PRIVATE 721 722 struct gmac_txdb { 723 uint32_t txdb_flags; 724 uint32_t txdb_buflen; 725 uint32_t txdb_addrlo; 726 uint32_t txdb_addrhi; 727 }; 728 #define TXDB_FLAG_SF __BIT(31) // Start oF Frame 729 #define TXDB_FLAG_EF __BIT(30) // End oF Frame 730 #define TXDB_FLAG_IC __BIT(29) // Interupt on Completetion 731 #define TXDB_FLAG_ET __BIT(28) // End Of Table 732 733 struct gmac_rxdb { 734 uint32_t rxdb_flags; 735 uint32_t rxdb_buflen; 736 uint32_t rxdb_addrlo; 737 uint32_t rxdb_addrhi; 738 }; 739 #define RXDB_FLAG_SF __BIT(31) // Start oF Frame (ignored) 740 #define RXDB_FLAG_EF __BIT(30) // End oF Frame (ignored) 741 #define RXDB_FLAG_IC __BIT(29) // Interupt on Completetion 742 #define RXDB_FLAG_ET __BIT(28) // End Of Table 743 744 #define RXSTS_FRAMELEN __BITS(15,0) // # of bytes (including padding) 745 #define RXSTS_PKTTYPE __BITS(17,16) 746 #define RXSTS_PKTTYPE_UC 0 // Unicast 747 #define RXSTS_PKTTYPE_MC 1 // Multicast 748 #define RXSTS_PKTTYPE_BC 2 // Broadcast 749 #define RXSTS_VLAN_PRESENT __BIT(18) 750 #define RXSTS_CRC_ERROR __BIT(19) 751 #define RXSTS_OVERSIZED __BIT(20) 752 #define RXSTS_CTF_HIT __BIT(21) 753 #define RXSTS_CTF_ERROR __BIT(22) 754 #define RXSTS_PKT_OVERFLOW __BIT(23) 755 #define RXSTS_DESC_COUNT __BITS(27,24) // # of descriptors - 1 756 757 #define GMAC_DEVCONTROL 0x000 758 #define ENABLE_DEL_G_TXC __BIT(21) 759 #define ENABLE_DEL_G_RXC __BIT(20) 760 #define TXC_DRNG __BITS(19,18) 761 #define RXC_DRNG __BITS(17,16) 762 #define TXQ_FLUSH __BIT(8) 763 #define NWAY_AUTO_POLL_EN __BIT(7) 764 #define FLOW_CTRL_MODE __BITS(6,5) 765 #define MIB_RD_RESET_EN __BIT(4) 766 #define RGMII_LINK_STATUS_SEL __BIT(3) 767 #define CPU_FLOW_CTRL_ON __BIT(2) 768 #define RXQ_OVERFLOW_CTRL_SEL __BIT(1) 769 #define TXARB_STRICT_MODE __BIT(0) 770 #define GMAC_DEVSTATUS 0x004 771 #define GMAC_BISTSTATUS 0x00c 772 #define GMAC_INTSTATUS 0x020 773 #define GMAC_INTMASK 0x024 774 #define TXQECCUNCORRECTED __BIT(31) 775 #define TXQECCCORRECTED __BIT(30) 776 #define RXQECCUNCORRECTED __BIT(29) 777 #define RXQECCCORRECTED __BIT(28) 778 #define XMTINT_3 __BIT(27) 779 #define XMTINT_2 __BIT(26) 780 #define XMTINT_1 __BIT(25) 781 #define XMTINT_0 __BIT(24) 782 #define RCVINT __BIT(16) 783 #define XMTUF __BIT(15) 784 #define RCVFIFOOF __BIT(14) 785 #define RCVDESCUF __BIT(13) 786 #define DESCPROTOERR __BIT(12) 787 #define DATAERR __BIT(11) 788 #define DESCERR __BIT(10) 789 #define INT_SW_LINK_ST_CHG __BIT(8) 790 #define INT_TIMEOUT __BIT(7) 791 #define MIB_TX_INT __BIT(6) 792 #define MIB_RX_INT __BIT(5) 793 #define MDIOINT __BIT(4) 794 #define NWAYLINKSTATINT __BIT(3) 795 #define TXQ_FLUSH_DONEINT __BIT(2) 796 #define MIB_TX_OVERFLOW __BIT(1) 797 #define MIB_RX_OVERFLOW __BIT(0) 798 #define GMAC_GPTIMER 0x028 799 800 #define GMAC_INTRCVLAZY 0x100 801 #define INTRCVLAZY_FRAMECOUNT __BITS(31,24) 802 #define INTRCVLAZY_TIMEOUT __BITS(23,0) 803 #define GMAC_FLOWCNTL_TH 0x104 804 #define GMAC_TXARB_WRR_TH 0x108 805 #define GMAC_GMACIDLE_CNT_TH 0x10c 806 807 #define GMAC_FIFOACCESSADDR 0x120 808 #define GMAC_FIFOACCESSBYTE 0x124 809 #define GMAC_FIFOACCESSDATA 0x128 810 811 #define GMAC_PHYACCESS 0x180 812 #define GMAC_PHYCONTROL 0x188 813 #define GMAC_TXQCONTROL 0x18c 814 #define GMAC_RXQCONTROL 0x190 815 #define GMAC_GPIOSELECT 0x194 816 #define GMAC_GPIOOUTPUTEN 0x198 817 #define GMAC_TXQRXQMEMORYCONTROL 0x1a0 818 #define GMAC_MEMORYECCSTATUS 0x1a4 819 820 #define GMAC_CLOCKCONTROLSTATUS 0x1e0 821 #define GMAC_POWERCONTROL 0x1e8 822 823 #define GMAC_XMTCONTROL 0x200 824 #define XMTCTL_PREFETCH_THRESH __BITS(25,24) 825 #define XMTCTL_PREFETCH_CTL __BITS(23,21) 826 #define XMTCTL_BURSTLEN __BITS(20,18) 827 #define XMTCTL_ADDREXT __BITS(17,16) 828 #define XMTCTL_DMA_ACT_INDEX __BIT(13) 829 #define XMTCTL_PARITY_DIS __BIT(11) 830 #define XMTCTL_OUTSTANDING_READS __BITS(7,6) 831 #define XMTCTL_BURST_ALIGN_EN __BIT(5) 832 #define XMTCTL_DMA_LOOPBACK __BIT(2) 833 #define XMTCTL_SUSPEND __BIT(1) 834 #define XMTCTL_ENABLE __BIT(0) 835 #define GMAC_XMTPTR 0x204 836 #define XMT_LASTDSCR __BITS(11,4) 837 #define GMAC_XMTADDR_LOW 0x208 838 #define GMAC_XMTADDR_HIGH 0x20c 839 #define GMAC_XMTSTATUS0 0x210 840 #define XMTSTATE __BITS(31,28) 841 #define XMTSTATE_DIS 0 842 #define XMTSTATE_ACTIVE 1 843 #define XMTSTATE_IDLE_WAIT 2 844 #define XMTSTATE_STOPPED 3 845 #define XMTSTATE_SUSP_PENDING 4 846 #define XMT_CURRDSCR __BITS(11,4) 847 #define GMAC_XMTSTATUS1 0x214 848 #define XMTERR __BITS(31,28) 849 #define XMT_ACTIVEDSCR __BITS(11,4) 850 #define GMAC_RCVCONTROL 0x220 851 #define RCVCTL_PREFETCH_THRESH __BITS(25,24) 852 #define RCVCTL_PREFETCH_CTL __BITS(23,21) 853 #define RCVCTL_BURSTLEN __BITS(20,18) 854 #define RCVCTL_ADDREXT __BITS(17,16) 855 #define RCVCTL_DMA_ACT_INDEX __BIT(13) 856 #define RCVCTL_PARITY_DIS __BIT(11) 857 #define RCVCTL_OFLOW_CONTINUE __BIT(10) 858 #define RCVCTL_SEPRXHDRDESC __BIT(9) 859 #define RCVCTL_RCVOFFSET __BITS(7,1) 860 #define RCVCTL_ENABLE __BIT(0) 861 #define GMAC_RCVPTR 0x224 862 #define RCVPTR __BITS(11,4) 863 #define GMAC_RCVADDR_LOW 0x228 864 #define GMAC_RCVADDR_HIGH 0x22c 865 #define GMAC_RCVSTATUS0 0x230 866 #define RCVSTATE __BITS(31,28) 867 #define RCVSTATE_DIS 0 868 #define RCVSTATE_ACTIVE 1 869 #define RCVSTATE_IDLE_WAIT 2 870 #define RCVSTATE_STOPPED 3 871 #define RCVSTATE_SUSP_PENDING 4 872 #define RCV_CURRDSCR __BITS(11,4) 873 #define GMAC_RCVSTATUS1 0x234 874 #define RCV_ACTIVEDSCR __BITS(11,4) 875 876 #define GMAC_TX_GD_OCTETS_LO 0x300 877 878 879 #define UNIMAC_IPG_HD_BPG_CNTL 0x804 880 #define UNIMAC_COMMAND_CONFIG 0x808 881 #define RUNT_FILTER_DIS __BIT(30) 882 #define OOB_EFC_EN __BIT(29) 883 #define IGNORE_TX_PAUSE __BIT(28) 884 #define PRBL_ENA __BIT(27) 885 #define RX_ERR_DIS __BIT(26) 886 #define LINE_LOOPBACK __BIT(25) 887 #define NO_LENGTH_CHECK __BIT(24) 888 #define CNTRL_FRM_ENA __BIT(23) 889 #define ENA_EXT_CONFIG __BIT(22) 890 #define EN_INTERNAL_TX_CRS __BIT(21) 891 #define SW_OVERRIDE_RX __BIT(18) 892 #define SW_OVERRIDE_TX __BIT(17) 893 #define MAC_LOOP_CON __BIT(16) 894 #define LOOP_ENA __BIT(15) 895 #define RCS_CORRUPT_URUN_EN __BIT(14) 896 #define SW_RESET __BIT(13) 897 #define OVERFLOW_EN __BIT(12) 898 #define RX_LOW_LATENCY_EN __BIT(11) 899 #define HD_ENA __BIT(10) 900 #define TX_ADDR_INS __BIT(9) 901 #define PAUSE_IGNORE __BIT(8) 902 #define PAUSE_FWD __BIT(7) 903 #define CRC_FWD __BIT(6) 904 #define PAD_EN __BIT(5) 905 #define PROMISC_EN __BIT(4) 906 #define ETH_SPEED __BITS(3,2) 907 #define ETH_SPEED_10 0 908 #define ETH_SPEED_100 1 909 #define ETH_SPEED_1000 2 910 #define ETH_SPEED_2500 3 911 #define RX_ENA __BIT(1) 912 #define TX_ENA __BIT(0) 913 #define UNIMAC_MAC_0 0x80c // bits 16:47 of macaddr 914 #define UNIMAC_MAC_1 0x810 // bits 0:15 of macaddr 915 #define UNIMAC_FRAME_LEN 0x814 916 #define UNIMAC_PAUSE_QUANTA 0x818 917 #define UNIMAC_TX_TS_SEQ_ID 0x83c 918 #define UNIMAC_MAC_MODE 0x844 919 #define UNIMAC_TAG_0 0x848 920 #define UNIMAC_TAG_1 0x84c 921 #define UNIMAC_RX_PAUSE_QUANTA_SCALE 0x850 922 #define UNIMAC_TX_PREAMBLE 0x854 923 #define UNIMAC_TX_IPG_LENGTH 0x85c 924 #define UNIMAC_PRF_XOFF_TIMER 0x860 925 #define UNIMAC_UMAC_EEE_CTRL 0x864 926 #define UNIMAC_MII_EEE_DELAY_ENTRY_TIMER 0x868 927 #define UNIMAC_GMII_EEE_DELAY_ENTRY_TIMER 0x86c 928 #define UNIMAC_UMAC_EEE_REF_COUNT 0x870 929 #define UNIMAC_UMAX_RX_PKT_DROP_STATUS 0x878 930 931 #define UNIMAC_UMAC_SYMMETRIC_IDLE_THRESHOLD 0x87c // RX IDLE threshold for LPI prediction 932 #define UNIMAC_MII_EEE_WAKE_TIMER 0x880 // MII_EEE Wake timer 933 #define UNIMAC_GMII_EEE_WAKE_TIMER 0x884 // GMII_EEE Wake timer 934 #define UNIMAC_UMAC_REV_ID 0x888 // UNIMAC_REV_ID 935 #define UNIMAC_MAC_PFC_TYPE 0xb00 // Programmable ethertype (GNAT 13440) 936 #define UNIMAC_MAC_PFC_OPCODE 0xb04 // Programmable opcode (GNAT 13440) 937 #define UNIMAC_MAC_PFC_DA_0 0xb08 // lower 32 bits of programmable DA for PPP (GNAT 13897) 938 #define UNIMAC_MAC_PFC_DA_1 0xb0c // upper 16 bits of programmable DA for PPP (GNAT 13897) 939 #define UNIMAC_MACSEC_CNTRL 0xb14 // Miscellaneous control for MACSEC (GNAT 11599,11600,12078,12198) 940 #define UNIMAC_TS_STATUS_CNTRL 0xb18 // Timestamp control/status 941 #define UNIMAC_TX_TS_DATA 0xb1c // Transmit Timestamp data 942 #define UNIMAC_PAUSE_CONTROL 0xb30 // PAUSE frame timer control register 943 #define UNIMAC_FLUSH_CONTROL 0xb34 // Flush enable control register 944 #define UNIMAC_RXFIFO_STAT 0xb38 // RXFIFO status register 945 #define UNIMAC_TXFIFO_STAT 0xb3c // TXFIFO status register 946 #define UNIMAC_MAC_PFC_CTRL 0xb40 // PPP control register 947 #define UNIMAC_MAC_PFC_REFRESH_CTRL 0xb44 // PPP refresh control register 948 949 #endif /* GMAC_PRIVATE */ 950 951 #ifdef NAND_PRIVATE 952 953 #define NAND_REVISION 0x0000 // NAND Revision 954 #define NAND_CMD_START 0x0004 // Nand Flash Command Start 955 #define NAND_CMD_EXT_ADDR 0x0008 // Nand Flash Command Extended Address 956 #define NAND_CMD_ADDR 0x000c // Nand Flash Command Address 957 #define NAND_CMD_END_ADDR 0x0010 // Nand Flash Command End Address 958 #define NAND_INTFC_STATUS 0x0014 // Nand Flash Interface Status 959 #define NAND_CS_NAND_SELECT 0x0018 // Nand Flash CS 960 #define NAND_CS_NAND_XOR 0x001c // Nand Flash EBI 961 #define NAND_LL_OP 0x0020 // Nand Flash Low Level Operation 962 #define NAND_MPLANE_BASE_EXT_ADDR 0x0024 // Nand Flash Multiplane base address 963 #define NAND_MPLANE_BASE_ADDR 0x0028 // Nand Flash Multiplane base address 964 #define NAND_ACC_CONTROL_CS0 0x0050 // Nand Flash Access Control 965 #define NAND_CONFIG_CS0 0x0054 // Nand Flash Config 966 #define NAND_TIMING_1_CS0 0x0058 // Nand Flash Timing Parameters 1 967 #define NAND_TIMING_2_CS0 0x005c // Nand Flash Timing Parameters 2 968 #define NAND_ACC_CONTROL_CS1 0x0060 // Nand Flash Access Control 969 #define NAND_CONFIG_CS1 0x0064 // Nand Flash 970 #define NAND_TIMING_1_CS1 0x0068 // Nand Flash Timing Parameters 1 971 #define NAND_TIMING_2_CS1 0x006c // Nand Flash Timing Parameters 2 972 #define NAND_CORR_STAT_THRESHOLD 0x00c0 // Correctable Error Reporting Threshold 973 #define NAND_BLK_WR_PROTECT 0x00c8 // Block Write Protect Enable and Size for EBI_CS0b 974 #define NAND_MULTIPLANE_OPCODES_1 0x00cc // Nand Flash Multiplane Customized Opcodes 975 #define NAND_MULTIPLANE_OPCODES_2 0x00d0 // Nand Flash Multiplane Customized Opcodes 976 #define NAND_MULTIPLANE_CTRL 0x00d4 // Nand Flash Multiplane Control 977 #define NAND_UNCORR_ERROR_COUNT 0x00fc // Read Uncorrectable Event Count 978 #define NAND_CORR_ERROR_COUNT 0x0100 // Read Error Count 979 #define NAND_READ_ERROR_COUNT 0x0104 // Read Error Count 980 #define NAND_BLOCK_LOCK_STATUS 0x0108 // Nand Flash Block Lock Status 981 #define NAND_ECC_CORR_EXT_ADDR 0x010c // ECC Correctable Error Extended Address 982 #define NAND_ECC_CORR_ADDR 0x0110 // ECC Correctable Error Address 983 #define NAND_ECC_UNC_EXT_ADDR 0x0114 // ECC Uncorrectable Error Extended Address 984 #define NAND_ECC_UNC_ADDR 0x0118 // ECC Uncorrectable Error Address 985 #define NAND_FLASH_READ_EXT_ADDR 0x011c // Flash Read Data Extended Address 986 #define NAND_FLASH_READ_ADDR 0x0120 // Flash Read Data Address 987 #define NAND_PROGRAM_PAGE_EXT_ADDR 0x0124 // Page Program Extended Address 988 #define NAND_PROGRAM_PAGE_ADDR 0x0128 // Page Program Address 989 #define NAND_COPY_BACK_EXT_ADDR 0x012c // Copy Back Extended Address 990 #define NAND_COPY_BACK_ADDR 0x0130 // Copy Back Address 991 #define NAND_BLOCK_ERASE_EXT_ADDR 0x0134 // Block Erase Extended Address 992 #define NAND_BLOCK_ERASE_ADDR 0x0138 // Block Erase Address 993 #define NAND_INV_READ_EXT_ADDR 0x013c // Flash Invalid Data Extended Address 994 #define NAND_INV_READ_ADDR 0x0140 // Flash Invalid Data Address 995 #define NAND_INIT_STATUS 0x0144 // Initialization status 996 #define NAND_ONFI_STATUS 0x0148 // ONFI Status 997 #define NAND_ONFI_DEBUG_DATA 0x014c // ONFI Debug Data 998 #define NAND_SEMAPHORE 0x0150 // Semaphore 999 #define NAND_FLASH_DEVICE_ID 0x0194 // Nand Flash Device ID 1000 #define NAND_FLASH_DEVICE_ID_EXT 0x0198 // Nand Flash Extended Device ID 1001 #define NAND_LL_RDDATA 0x019c // Nand Flash Low Level Read Data 1002 1003 #define NAND_SPARE_AREA_READ_OFSn(n) (0x0200+4*(n)) // Nand Flash Spare Area Read Bytes 1004 #define NAND_SPARE_AREA_WRITE_OFSn(n) (0x0280+4*(n)) // Nand Flash Spare Area Write Bytes 8-11 1005 #define NAND_FLASH_CACHEn(n) (0x0400+4*(n)) // Flash Cache Buffer Read Access 1006 1007 #define NAND_DIRECT_READ_RD_MISS 0x0f00 // Interrupt from Nand indicating a read miss on internal memory 1008 #define NAND_BLOCK_ERASE_COMPLETE 0x0f04 // Interrupt from Nand indicating block erase 1009 #define NAND_COPY_BACK_COMPLETE 0x0f08 // Interrupt from Nand indicating Copy-Back complete. 1010 #define NAND_PROGRAM_PAGE_COMPLETE 0x0f0c // Interrupt from nand indicating page program is complete. 1011 #define NAND_RO_CTLR_READY 0x0f10 // Interrupt from nand indicating controller ready 1012 #define NAND_NAND_RB_B 0x0f14 // Interrupt from nand indicating status of Nand Flash ready_bus pin 1013 #define NAND_ECC_MIPS_UNCORR 0x0f18 // Interrupt from Nand indicating Uncorrectable error 1014 #define NAND_ECC_MIPS_CORR 0x0f1c // Interrupt from Nand indicating correctable error 1015 1016 #define NAND_CMD_START_OPCODE __BITS(28,24) 1017 #define NAND_CMD_START_OPCODE_DEFAULT 0 1018 #define NAND_CMD_START_OPCODE_NULL 0 1019 #define NAND_CMD_START_OPCODE_PAGE_READ 1 1020 #define NAND_CMD_START_OPCODE_SPARE_AREA_READ 2 1021 #define NAND_CMD_START_OPCODE_STATUS_READ 3 1022 #define NAND_CMD_START_OPCODE_PROGRAM_PAGE 4 1023 #define NAND_CMD_START_OPCODE_PROGRAM_SPARE_AREA 5 1024 #define NAND_CMD_START_OPCODE_COPY_BACK 6 1025 #define NAND_CMD_START_OPCODE_DEVICE_ID_READ 7 1026 #define NAND_CMD_START_OPCODE_BLOCK_ERASE 8 1027 #define NAND_CMD_START_OPCODE_FLASH_RESET 9 1028 #define NAND_CMD_START_OPCODE_BLOCKS_LOCK 10 1029 #define NAND_CMD_START_OPCODE_BLOCKS_LOCK_DOWN 11 1030 #define NAND_CMD_START_OPCODE_BLOCKS_UNLOCK 12 1031 #define NAND_CMD_START_OPCODE_READ_BLOCKS_LOCK_STATUS 13 1032 #define NAND_CMD_START_OPCODE_PARAMETER_READ 14 1033 #define NAND_CMD_START_OPCODE_PARAMETER_CHANGE_COL 15 1034 #define NAND_CMD_START_OPCODE_LOW_LEVEL_OP 16 1035 #define NAND_CMD_START_OPCODE_PAGE_READ_MULTI 17 1036 #define NAND_CMD_START_OPCODE_STATUS_READ_MULTI 18 1037 #define NAND_CMD_START_OPCODE_PROGRAM_PAGE_MULTI 19 1038 #define NAND_CMD_START_OPCODE_PROGRAM_PAGE_MULTI_CACHE 20 1039 #define NAND_CMD_START_OPCODE_BLOCK_ERASE_MULTI 21 1040 #define NAND_CMD_START_CSEL __BITS(18,16) 1041 #define NAND_CMD_EXT_ADDRESS __BITS(15,0) 1042 1043 #define BCM_NAND_IDM_IO_CONTROL_APB_LE_MODE_BIT __BIT(24) 1044 1045 1046 #endif /* NAND_PRIVATE */ 1047 1048 #endif /* _ARM_BROADCOM_BCM53XX_REG_H_ */ 1049