1 /*- 2 * Copyright (c) 2012 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas of 3am Software Foundry. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #ifndef _ARM_BROADCOM_BCM53XX_REG_H_ 31 #define _ARM_BROADCOM_BCM53XX_REG_H_ 32 33 /* 34 * 0x0000_0000..0x07ff_ffff 128MB DDR2/3 DRAM Memory Region (dual map) 35 * 0x0800_0000..0x0fff_ffff 128MB PCIe 0 Address Match Region 36 * 0x1800_0000..0x180f_ffff 1MB Core Register Region 37 * 0x1810_0000..0x181f_ffff 1MB IDM Register Region 38 * 0x1900_0000..0x190f_ffff 1MB ARMcore (CORTEX-A9) Register Region 39 * 0x1c00_0000..0x1dff_ffff 1MB NAND Flash Region 40 * 0x1e00_0000..0x1dff_ffff 1MB Serial Flash Region 41 * 0x4000_0000..0x47ff_ffff 128MB PCIe 1 Address Match Region 42 * 0x4800_0000..0x4fff_ffff 128MB PCIe 2 Address Match Region 43 * 0x8000_0000..0xbfff_ffff 1024MB DDR2/3 DRAM Memory Region 44 * 0xfffd_0000..0xfffe_ffff 128KB Internal Boot ROM Region 45 * 0xffff_0000..0xffff_043f 1088B Internal SKU ROM Region 46 * 0xffff_1000..0xffff_1fff 4KB Enumeration ROM Register Region 47 */ 48 #define BCM53XX_PCIE0_OWIN_PBASE 0x08000000 49 #define BCM53XX_PCIE0_OWIN_SIZE 0x04000000 50 #define BCM53XX_PCIE0_OWIN_MAX 0x08000000 51 52 #define BCM53XX_IOREG_PBASE 0x18000000 53 #define BCM53XX_IOREG_SIZE 0x00200000 54 55 #define BCM53XX_ARMCORE_PBASE 0x19000000 56 #define BCM53XX_ARMCORE_SIZE 0x00100000 57 58 #define BCM53XX_NAND_PBASE 0x1c000000 59 #define BCM53XX_NAND_SIZE 0x01000000 60 61 #define BCM53XX_SPIFLASH_PBASE 0x1d000000 62 #define BCM53XX_SPIFLASH_SIZE 0x01000000 63 64 #define BCM53XX_PCIE1_OWIN_PBASE 0x40000000 65 #define BCM53XX_PCIE1_OWIN_SIZE 0x04000000 66 #define BCM53XX_PCIE1_OWIN_MAX 0x08000000 67 68 #define BCM53XX_PCIE2_OWIN_PBASE 0x48000000 69 #define BCM53XX_PCIE2_OWIN_SIZE 0x04000000 70 #define BCM53XX_PCIE2_OWIN_MAX 0x08000000 71 72 #define BCM53XX_IO_SIZE (BCM53XX_IOREG_SIZE \ 73 + BCM53XX_ARMCORE_SIZE \ 74 + BCM53XX_PCIE0_OWIN_SIZE \ 75 + BCM53XX_PCIE1_OWIN_SIZE \ 76 + BCM53XX_PCIE2_OWIN_SIZE) 77 78 #define BCM53XX_REF_CLK (25*1000*1000) 79 80 #define CCA_UART_FREQ BCM53XX_REF_CLK 81 82 /* Chip Common A */ 83 #define CCA_MISC_BASE 0x000000 84 #define CCA_MISC_SIZE 0x001000 85 #define CCA_UART0_BASE 0x000300 86 #define CCA_UART1_BASE 0x000400 87 88 /* Chip Common B */ 89 #define CCB_BASE 0x000000 90 #define CCB_SIZE 0x030000 91 #define PWM_BASE 0x002000 92 #define MII_BASE 0x003000 93 #define RNG_BASE 0x004000 94 #define TIMER0_BASE 0x005000 95 #define TIMER1_BASE 0x006000 96 #define SRAB_BASE 0x007000 97 #define UART2_BASE 0x008000 98 #define SMBUS_BASE 0x009000 99 100 #define CRU_BASE 0x00b000 101 #define DMU_BASE 0x00c000 102 103 #define DDR_BASE 0x010000 104 105 #define PCIE0_BASE 0x012000 106 #define PCIE1_BASE 0x013000 107 #define PCIE2_BASE 0x014000 108 109 #define SDIO_BASE 0x020000 110 #define EHCI_BASE 0x021000 111 #define OHCI_BASE 0x022000 112 113 #define GMAC0_BASE 0x024000 114 #define GMAC1_BASE 0x025000 115 #define GMAC2_BASE 0x026000 116 #define GMAC3_BASE 0x027000 117 118 #define IDM_BASE 0x100000 119 #define IDM_SIZE 0x100000 120 121 /* Chip Common A */ 122 123 #ifdef CCA_PRIVATE 124 125 #define MISC_CHIPID 0x000 126 #define CHIPID_REV __BITS(19,16) 127 #define CHIPID_ID __BITS(15,0) 128 #define ID_BCM53010 0xcf12 // 53010 129 #define ID_BCM53011 0xcf13 // 53011 130 #define ID_BCM53012 0xcf14 // 53012 131 #define ID_BCM53013 0xcf15 // 53013 132 133 #define MISC_CAPABILITY 0x004 134 #define CAPABILITY_JTAG_PRESENT __BIT(22) 135 #define CAPABILITY_UART_CLKSEL __BITS(4,3) 136 #define UART_CLKSEL_REFCLK 0 137 #define UART_CLKSEL_INTCLK 1 138 /* 2 & 3 are reserved */ 139 #define CAPABILITY_BIG_ENDIAN __BIT(2) 140 #define CAPABILITY_UART_COUNT __BITS(1,0) 141 142 #define MISC_CORECTL 0x008 143 #define CORECTL_UART_CLK_EN __BIT(3) 144 #define CORECTL_GPIO_ASYNC_INT_EN __BIT(2) 145 #define CORECTL_UART_CLK_OVERRIDE __BIT(0) 146 147 #define MISC_INTSTATUS 0x020 148 #define INTSTATUS_WDRESET __BIT(31) // WO2C 149 #define INTSTATUS_UARTINT __BIT(6) // RO 150 #define INTSTATUS_GPIOINT __BIT(0) // RO 151 152 #define MISC_INTMASK 0x024 153 #define INTMASK_UARTINT __BIT(6) // 1 = enabled 154 #define INTMASK_GPIOINT __BIT(0) // 1 = enabled 155 156 /* Only bits [23:0] are used in the GPIO registers */ 157 #define GPIO_INPUT 0x060 // RO 158 #define GPIO_OUT 0x064 159 #define GPIO_OUTEN 0x068 160 #define GPIO_INTPOLARITY 0x070 // 1 = active low 161 #define GPIO_INTMASK 0x074 // 1 = enabled (level) 162 #define GPIO_EVENT 0x078 // W1C, 1 = edge seen 163 #define GPIO_EVENT_INTMASK 0x07c // 1 = enabled (edge) 164 #define GPIO_EVENT_INTPOLARITY 0x084 // 1 = falling 165 #define GPIO_TIMER_VAL 0x088 166 #define TIMERVAL_ONCOUNT __BITS(31,16) 167 #define TIMERVAL_OFFCOUNT __BITS(15,0) 168 #define GPIO_TIMER_OUTMASK 0x08c 169 #define GPIO_DEBUG_SEL 0x0a8 170 171 #define MISC_WATCHDOG 0x080 // 0 disables, 1 resets 172 173 #define MISC_CLKDIV 0x0a4 174 #define CLKDIV_JTAG_MASTER_CLKDIV __BITS(13,9) 175 #define CLKDIV_UART_CLKDIV __BITS(7,1) 176 177 #define MISC_CAPABILITY2 0x0ac 178 #define CAPABILITY2_GSIO_PRESENT __BIT(1) // SPI exists 179 180 #define MISC_GSIOCTL 0x0e4 181 #define GSIOCTL_STARTBUSY __BIT(31) 182 #define GSIOCTL_GSIOMODE __BIT(30) // 0 = SPI 183 #define GSIOCTL_ERROR __BIT(23) 184 #define GSIOCTL_BIGENDIAN __BIT(22) 185 #define GSIOCTL_GSIOGO __BIT(21) 186 #define GSIOCTL_NUM_DATABYTES __BITS(17,16) // actual is + 1 187 #define GSIOCTL_NUM_WAITCYCLES __BITS(15,14) // actual is + 1 188 #define GSIOCTL_NUM_ADDRESSBYTES __BITS(13,12) // actual is + 1 189 #define GSIOCTL_GSIOCODE __BITS(10,8) 190 #define GSIOCODE_OP_RD1DATA 0 191 #define GSIOCODE_OP_WRADDR_RDADDR 1 192 #define GSIOCODE_OP_WRADDR_XFRDATA 2 193 #define GSIOCODE_OP_WRADDR_WAIT_XFRDATA 3 194 #define GSIOCODE_XFRDATA 4 195 #define GSIOCTL_GSIOOP __BITS(7,0) 196 197 #define MISC_GSIOADDRESS 0x0e8 198 #define MISC_GSIODATA 0x0ec 199 200 #define MISC_CLKDIV2 0x0f0 201 #define CLKDIV2_GSIODIV __BITS(20,5) 202 203 #define MISC_EROM_PTR_OFFSET 0x0fc 204 205 #endif /* CCA_PRIVATE */ 206 207 /* 208 * UART0 & 1 use the standard 16550 register layout (normal 1 byte stride) 209 * and have 64-byte FIFOs 210 */ 211 212 /* TIMER0 & 1 are implemented by the dtimer driver */ 213 214 #define TIMER_FREQ BCM53XX_REF_CLK 215 216 #ifdef SRAB_PRIVATE 217 #define SRAB_CMDSTAT 0x002c 218 #define SRA_PAGE __BITS(31,24) 219 #define SRA_OFFSET __BITS(23,16) 220 #define SRA_PAGEOFFSET __BITS(31,16) 221 #define SRA_RST __BIT(2) 222 #define SRA_WRITE __BIT(1) 223 #define SRA_GORDYN __BIT(0) 224 #define SRAB_WDH 0x0030 225 #define SRAB_WDL 0x0034 226 #define SRAB_RDH 0x0038 227 #define SRAB_RDL 0x003c 228 #endif 229 230 #ifdef MII_PRIVATE 231 #define MII_INTERNAL 0x0038003 /* internal phy bitmask */ 232 #define MIIMGT 0x000 233 #define MIIMGT_BYP __BIT(10) 234 #define MIIMGT_EXT __BIT(9) 235 #define MIIMGT_BSY __BIT(8) 236 #define MIIMGT_PRE __BIT(7) 237 #define MIIMGT_MDCDIV __BITS(6,0) 238 #define MIICMD 0x004 239 #define MIICMD_SB __BITS(31,30) 240 #define MIICMD_SB_DEF __SHIFTIN(1, MIICMD_SB) 241 #define MIICMD_OP __BITS(29,28) 242 #define MIICMD_OP_RD __SHIFTIN(2, MIICMD_OP) 243 #define MIICMD_OP_WR __SHIFTIN(1, MIICMD_OP) 244 #define MIICMD_PHY __BITS(27,23) 245 #define MIICMD_REG __BITS(22,18) 246 #define MIICMD_TA __BITS(17,16) 247 #define MIICMD_TA_DEF __SHIFTIN(2, MIICMD_TA) 248 #define MIICMD_DATA __BITS(15,0) 249 250 #define MIICMD_RD_DEF (MIICMD_SB_DEF|MIICMD_OP_RD|MIICMD_TA_DEF) 251 #define MIICMD_WR_DEF (MIICMD_SB_DEF|MIICMD_OP_WR|MIICMD_TA_DEF) 252 #define MIICMD__PHYREG(p,r) (__SHIFTIN(p,MIICMD_PHY)|__SHIFTIN(r,MIICMD_REG)) 253 #define MIICMD_RD(p,r) (MIICMD_RD_DEF|MIICMD__PHYREG((p),(r))) 254 #define MIICMD_WR(p,r,v) (MIICMD_WR_DEF|MIICMD__PHYREG((p),(r))|(v)) 255 #endif /* MII_PRIVATE */ 256 257 #ifdef RNG_PRIVATE 258 #define RNG_CTRL 0x000 259 #define RNG_COMBLK2_OSC_DIS __BITS(27,22) 260 #define RNG_COMBLK1_OSC_DIS __BITS(21,16) 261 #define RNG_ICLK_BYP_DIV_CNT __BITS(15,8) 262 #define RNG_JCLK_BYP_SRC __BIT(5) 263 #define RNG_JCLK_BYP_SEL __BIT(4) 264 #define RNG_RBG2X __BIT(1) 265 #define RNG_RBGEN __BIT(0) 266 #define RNG_STATUS 0x004 267 #define RNG_VAL __BITS(31,24) 268 #define RNG_WARM_CNT __BITS(19,0) 269 270 #define RNG_DATA 0x008 271 #define RNG_FF_THRESHOLD 0x00c 272 #define RNG_INT_MASK 0x010 273 #define RNG_INT_OFF __BIT(0) 274 #endif /* RNG_PRIVATE */ 275 276 #ifdef UART2_PRIVATE 277 /* 278 * UART2 (ChipCommonB) uses a 4-byte stride and 16-byte FIFO. 279 * Its frequency is the APB clock. 280 */ 281 #define UART2_LPDLL 0x020 282 #define UART2_LPDLH 0x024 283 #endif 284 285 #ifdef CRU_PRIVATE 286 287 #define CRU_CONTROL 0x000 288 #define CRUCTL_QSPI_CLK_SEL __BITS(2,1) 289 #define QSPI_CLK_25MHZ 0 // iproc_ref_clk 290 #define QSPI_CLK_50MHZ 1 // iproc_sdio_clk / 4 291 #define QSPI_CLK_31dot25MHZ 2 // iproc_clk250 / 8 292 #define QSPI_CLK_62dot5MHZ 3 // iproc_clk250 / 4 293 #define CRUCTL_SW_RESET __BIT(0) 294 295 #define CRU_GENPLL_CONTROL5 0x1154 296 #define GENPLL_CONTROL5_NDIV_INT __BITS(29,20) // = (n ? n : 1024) 297 #define GENPLL_CONTROL5_NDIV_FRAC __BITS(19,0) // = 1 / n 298 #define CRU_GENPLL_CONTROL6 0x1158 299 #define GENPLL_CONTROL6_PDIV __BITS(26,24) // = (n ? n : 8) 300 #define GENPLL_CONTROL6_CH0_MDIV __BITS(23,16) // = (n ? n : 256), clk_mac 301 #define GENPLL_CONTROL6_CH1_MDIV __BITS(15,8) // = (n ? n : 256), clk_robo 302 #define GENPLL_CONTROL6_CH2_MDIV __BITS(7,0) // = (n ? n : 256), clf_usb2 303 #define CRU_GENPLL_CONTROL7 0x115c 304 #define GENPLL_CONTROL7_CH3_MDIV __BITS(23,16) // = (n ? n : 256), clk_iproc 305 306 #define USB2_REF_CLK (1920*1000*1000) 307 #define CRU_USB2_CONTROL 0x1164 308 #define USB2_CONTROL_KA __BITS(24,22) 309 #define USB2_CONTROL_KI __BITS(31,19) 310 #define USB2_CONTROL_KP __BITS(18,15) 311 #define USB2_CONTROL_PDIV __BITS(14,12) // = (n ? n : 8) 312 #define USB2_CONTROL_NDIV_INT __BITS(11,2) // = (n ? n : 1024) 313 #define USB2_CONTROL_PLL_PCIEUSB3_RESET __BIT(1) // inverted 1=normal 314 #define USB2_CONTROL_PLL_USB2_RESET __BIT(0) // inverted 1=normal 315 316 #define CRU_CLKSET_KEY 0x1180 317 #define CRU_CLKSET_KEY_MAGIC 0xea68 318 319 #define CRU_GPIO_SELECT 0x11c0 // CRU GPIO Select 320 #define CRU_GPIO_DRIVE_SEL2 0x11c4 321 #define CRU_GPIO_DRIVE_SEL1 0x11c8 322 #define CRU_GPIO_DRIVE_SEL0 0x11cc 323 #define CRU_GPIO_INPUT_DISABLE 0x11d0 324 #define CRU_GPIO_HYSTERESIS 0x11d4 325 #define CRU_GPIO_SLEW_RATE 0x11d8 326 #define CRU_GPIO_PULL_UP 0x11dc 327 #define CRU_GPIO_PULL_DOWN 0x11e0 328 329 #define CRU_STRAPS_CONTROL 0x12a0 330 #define STRAP_BOOT_DEV __BITS(17,16) 331 #define STRAP_NAND_TYPE __BITS(15,12) 332 #define STRAP_NAND_PAGE __BITS(11,10) 333 #define STRAP_DDR3 __BIT(9) 334 #define STRAP_P5_VOLT_15 __BIT(8) 335 #define STRAP_P5_MODE __BITS(7,6) 336 #define STRAP_PCIE0_MODE __BIT(5) 337 #define STRAP_USB3_SEL __BIT(4) 338 #define STRAP_EX_EXTCLK __BIT(3) 339 #define STRAP_HW_FWDG_EN __BIT(2) 340 #define STRAP_LED_SERIAL_MODE __BIT(1) 341 #define STRAP_BISR_BYPASS_AUTOLOAD __BIT(0) 342 343 #endif /* CRU_PRIVATE */ 344 345 #ifdef DMU_PRIVATE 346 347 #define DMU_LCPLL_CONTROL0 0x100 348 #define DMU_LCPLL_CONTROL1 0x104 349 #define LCPLL_CONTROL1_PDIV __BITS(30,28) // = (n ? n : 8) 350 #define LCPLL_CONTROL1_NDIV_INT __BITS(27,20) // = (n ? n : 256) 351 #define LCPLL_CONTROL1_NDIV_FRAC __BITS(19,0) // = 1 / n 352 /* 353 * SYS_CLK = (1 / pdiv) * (ndiv_int + (ndiv_frac / 0x40000000)) x F(ref) 354 */ 355 #define DMU_LCPLL_CONTROL2 0x108 356 #define LCPLL_CONTROL2_CH0_MDIV __BITS(31,24) // = (n ? n : 256), clk_pcie_ref 357 #define LCPLL_CONTROL2_CH1_MDIV __BITS(23,16) // = (n ? n : 256), clk_sdio 358 #define LCPLL_CONTROL2_CH2_MDIV __BITS(15,8) // = (n ? n : 256), clk_ddr 359 #define LCPLL_CONTROL2_CH3_MDIV __BITS(7,0) // = (n ? n : 256), clf_dft 360 361 #endif /* DMU_PRIVATE */ 362 363 #ifdef DDR_PRIVATE 364 /* 365 * DDR CTL register has such inspired names. 366 */ 367 #define DDR_CTL_01 0x004 368 #define CTL_01_MAX_CHIP_SEL __BITS(18,16) // not documented as such 369 #define CTL_01_MAX_COL __BITS(11,8) 370 #define CTL_01_MAX_ROW __BITS(4,0) 371 372 #define DDR_CTL_82 0x148 373 #define CTL_82_COL_DIFF __BITS(26,24) 374 #define CTL_82_ROW_DIFF __BITS(18,16) 375 #define CTL_82_BANK_DIFF __BITS(9,8) 376 #define CTL_82_ZQCS_ROTATE __BIT(0) 377 378 #define DDR_CTL_86 0x158 379 #define CTL_86_CS_MAP __BITS(27,24) 380 #define CTL_86_INHIBIT_DRAM_CMD __BIT(16) 381 #define CTL_86_DIS_RD_INTRLV __BIT(8) 382 #define CTL_86_NUM_QENT_ACT_DIS __BITS(2,0) 383 384 #define DDR_CTL_87 0x15c 385 #define CTL_87_IN_ORDER_ACCEPT __BIT(24) 386 #define CTL_87_Q_FULLNESS __BITS(18,16) 387 #define CTL_87_REDUC __BIT(8) 388 #define CTL_87_BURST_ON_FLY_BIT __BITS(3,0) 389 390 #define DDR_PHY_CTL_PLL_STATUS 0x810 391 #define PLL_STATUS_LOCK_LOST __BIT(26) 392 #define PLL_STATUS_MHZ __BITS(25,14) 393 #define PLL_STATUS_CLOCKING_4X __BIT(13) 394 #define PLL_STATUS_STATUS __BITS(12,1) 395 #define PLL_STATUS_LOCK __BIT(0) 396 397 #define DDR_PHY_CTL_PLL_DIVIDERS 0x81c 398 #define PLL_DIVIDERS_POST_DIV __BITS(13,11) 399 #define PLL_DIVIDERS_PDIV __BITS(10,8) // 4x: (n ? n : 8), n = n - 4, 4x 400 #define PLL_DIVIDERS_NDIV __BITS(7,0) 401 402 #endif /* DDR_PRIVATE */ 403 404 #ifdef PCIE_PRIVATE 405 406 #define PCIE_CLK_CONTROL 0x000 407 408 #define PCIE_RC_AXI_CONFIG 0x100 409 #define PCIE_AWCACHE_CONFIG __BITS(17,14) 410 #define PCIE_AWUSER_CONFIG __BITS(13,9) 411 #define PCIE_ARCACHE_CONFIG __BITS(8,5) 412 #define PCIE_ARUSER_CONFIG __BITS(4,0) 413 414 #define PCIE_CFG_IND_ADDR 0x120 415 #define CFG_IND_ADDR_FUNC __BITS(15,13) 416 #define CFG_IND_ADDR_LAYER __BITS(12,11) 417 #define CFG_IND_ADDR_REG __BITS(10,2) 418 #define PCIE_CFG_IND_DATA 0x124 419 #define PCIE_CFG_ADDR 0x1f8 420 #define CFG_ADDR_BUS __BITS(27,20) 421 #define CFG_ADDR_DEV __BITS(19,15) 422 #define CFG_ADDR_FUNC __BITS(14,12) 423 #define CFG_ADDR_REG __BITS(11,2) 424 #define CFG_ADDR_TYPE __BITS(1,0) 425 #define CFG_ADDR_TYPE0 __SHIFTIN(0, CFG_ADDR_TYPE) 426 #define CFG_ADDR_TYPE1 __SHIFTIN(1, CFG_ADDR_TYPE) 427 #define PCIE_CFG_DATA 0x1fc 428 #define PCIE_EQ_PAGE 0x200 429 #define PCIE_MSI_PAGE 0x204 430 #define PCIE_MSI_INTR_EN 0x208 431 #define PCIE_MSI_CTRL_0 0x210 432 #define PCIE_MSI_CTRL_1 0x214 433 #define PCIE_MSI_CTRL_2 0x218 434 #define PCIE_MSI_CTRL_3 0x21c 435 #define PCIE_MSI_CTRL_4 0x220 436 #define PCIE_MSI_CTRL_5 0x224 437 #define PCIE_SYS_EQ_HEAD_0 0x250 438 #define PCIE_SYS_EQ_TAIL_0 0x254 439 #define PCIE_SYS_EQ_HEAD_1 0x258 440 #define PCIE_SYS_EQ_TAIL_1 0x25c 441 #define PCIE_SYS_EQ_HEAD_2 0x260 442 #define PCIE_SYS_EQ_TAIL_2 0x264 443 #define PCIE_SYS_EQ_HEAD_3 0x268 444 #define PCIE_SYS_EQ_TAIL_3 0x26c 445 #define PCIE_SYS_EQ_HEAD_4 0x270 446 #define PCIE_SYS_EQ_TAIL_4 0x274 447 #define PCIE_SYS_EQ_HEAD_5 0x278 448 #define PCIE_SYS_EQ_TAIL_5 0x27c 449 #define PCIE_SYS_RC_INTX_EN 0x330 450 #define PCIE_SYS_RC_INTX_CSR 0x334 451 452 #define PCIE_CFG000_BASE 0x400 453 454 #define PCIE_FUNC0_IMAP0_0 0xc00 455 #define PCIE_FUNC0_IMAP0_1 0xc04 456 #define PCIE_FUNC0_IMAP0_2 0xc08 457 #define PCIE_FUNC0_IMAP0_3 0xc0c 458 #define PCIE_FUNC0_IMAP0_4 0xc10 459 #define PCIE_FUNC0_IMAP0_5 0xc14 460 #define PCIE_FUNC0_IMAP0_6 0xc18 461 #define PCIE_FUNC0_IMAP0_7 0xc1c 462 463 #define PCIE_FUNC0_IMAP1 0xc80 464 #define PCIE_FUNC1_IMAP1 0xc88 465 #define PCIE_FUNC0_IMAP2 0xcc0 466 #define PCIE_FUNC1_IMAP2 0xcc8 467 468 #define PCIE_IARR_0_LOWER 0xd00 469 #define PCIE_IARR_0_UPPER 0xd04 470 #define PCIE_IARR_1_LOWER 0xd08 471 #define PCIE_IARR_1_UPPER 0xd0c 472 #define PCIE_IARR_2_LOWER 0xd10 473 #define PCIE_IARR_2_UPPER 0xd14 474 475 #define PCIE_OARR_0 0xd20 476 #define PCIE_OARR_1 0xd28 477 478 #define PCIE_OARR_ADDR __BITS(31,26) 479 480 #define PCIE_OMAP_0_LOWER 0xd40 481 #define PCIE_OMAP_0_UPPER 0xd44 482 #define PCIE_OMAP_1_LOWER 0xd48 483 #define PCIE_OMAP_1_UPPER 0xd4c 484 485 #define PCIE_OMAP_ADDRL __BITS(31,26) 486 487 #define PCIE_FUNC1_IARR_1_SIZE 0xd58 488 #define PCIE_FUNC1_IARR_2_SIZE 0xd5c 489 490 #define PCIE_MEM_CONTROL 0xf00 491 #define PCIE_MEM_ECC_ERR_LOG_0 0xf04 492 #define PCIE_MEM_ECC_ERR_LOG_1 0xf08 493 494 #define PCIE_LINK_STATUS 0xf0c 495 #define PCIE_PHYLINKUP __BIT(3) 496 #define PCIE_DL_ACTIVE __BIT(2) 497 #define PCIE_RX_LOS_TIMEOUT __BIT(1) 498 #define PCIE_LINK_IN_L1 __BIT(0) 499 #define PCIE_STRAP_STATUS 0xf10 500 #define STRAP_PCIE_REPLAY_BUF_TM __BITS(8,4) 501 #define STRAP_PCIE_USER_FOR_CE_GEN1 __BIT(3) 502 #define STRAP_PCIE_USER_FOR_CE_1LANE __BIT(2) 503 #define STRAP_PCIE_IF_ENABLE __BIT(1) 504 #define STRAP_PCIE_USER_RC_MODE __BIT(0) 505 #define PCIE_RESET_STATUS 0xf14 506 507 #define PCIE_RESET_ENABLE_IN_PCIE_LINK_DOWN 0xf18 508 509 #define PCIE_MISC_INTR_EN 0xf1c 510 #define PCIE_TX_DEBUG_CFG 0xf20 511 #define PCIE_ERROR_INTR_EN 0xf30 512 #define PCIE_ERROR_INTR_CLR 0xf34 513 #define PCIE_ERROR_INTR_STS 0xf38 514 515 516 // PCIE_SYS_MSI_INTR_EN 517 #define MSI_INTR_EN_EQ_5 __BIT(5) 518 #define MSI_INTR_EN_EQ_4 __BIT(4) 519 #define MSI_INTR_EN_EQ_3 __BIT(3) 520 #define MSI_INTR_EN_EQ_2 __BIT(2) 521 #define MSI_INTR_EN_EQ_1 __BIT(1) 522 #define MSI_INTR_EN_EQ_0 __BIT(0) 523 524 // PCIE_SYS_MSI_CTRL<n> 525 #define INT_N_DELAY __BITS(9,6) 526 #define INT_N_EVENT __BITS(1,1) 527 #define EQ_ENABLE __BIT(0) 528 529 // PCIE_SYS_EQ_HEAD<n> 530 #define HEAD_PTR __BITS(5,0) 531 532 // PCIE_SYS_EQ_TAIL<n> 533 #define EQ_OVERFLOW __BIT(6) 534 #define TAIL_PTR __BITS(5,0) 535 536 // PCIE_SYS_RC_INTRX_EN 537 #define RC_EN_INTD __BIT(3) 538 #define RC_EN_INTC __BIT(2) 539 #define RC_EN_INTB __BIT(1) 540 #define RC_EN_INTA __BIT(0) 541 542 // PCIE_SYS_RC_INTRX_CSR 543 #define RC_INTD __BIT(3) 544 #define RC_INTC __BIT(2) 545 #define RC_INTB __BIT(1) 546 #define RC_INTA __BIT(0) 547 548 // PCIE_IARR_0_LOWER / UPPER 549 #define IARR0_ADDR __BIT(31,15) 550 #define IARR0_VALID __BIT(0) 551 552 // PCIE_IARR_1_LOWER / UPPER 553 #define IARR1_ADDR __BIT(31,20) 554 #define IARR1_SIZE __BIT(7,0) 555 556 // PCIE_IARR_2_LOWER / UPPER 557 #define IARR2_ADDR __BIT(31,20) 558 #define IARR2_SIZE __BIT(7,0) 559 560 // PCIE_MISC_INTR_EN 561 #define INTR_EN_PCIE_ERR_ATTN __BIT(2) 562 #define INTR_EN_PAXB_ECC_2B_ATTN __BIT(1) 563 #define INTR_EN_PCIE_IN_WAKE_B __BIT(0) 564 565 // PCIE_ERR_INTR_{EN,CLR,STS} 566 #define PCIE_OVERFLOW_UNDERFLOW_INTR __BIT(10) 567 #define PCIE_AXI_MASTER_RRESP_SLV_ERR_INTR __BIT(9) 568 #define PCIE_AXI_MASTER_RRESP_DECERR_INTR __BIT(8) 569 #define PCIE_ECRC_ERR_INTR __BIT(7) 570 #define PCIE_CMPL_TIMEROUT_INTR __BIT(6) 571 #define PCIE_ERR_ATTN_INTR __BIT(5) 572 #define PCIE_IN_WAKE_B_INTR __BIT(4) 573 #define PCIE_REPLAY_BUF_2B_ECC_ERR_INTR __BIT(3) 574 #define PCIE_RD_CMPL_BUF_1_2B_ECC_ERR_INTR __BIT(2) 575 #define PCIE_RD_CMPL_BUF_0_2B_ECC_ERR_INTR __BIT(1) 576 #define PCIE_WR_DATA_BUF_2B_ECC_ERR_INTR __BIT(0) 577 578 #define REGS_DEVICE_CAPACITY 0x04d4 579 #define REGS_LINK_CAPACITY 0x03dc 580 #define REGS_TL_CONTROL_0 0x0800 581 #define REGS_DL_STATUS 0x1048 582 583 #endif /* PCIE_PRIVATE */ 584 585 #define ARMCORE_SCU_BASE 0x20000 /* CBAR is 19020000 */ 586 #define ARMCORE_L2C_BASE 0x22000 587 588 #ifdef ARMCORE_PRIVATE 589 590 #define ARMCORE_CLK_POLICY_FREQ 0x008 591 #define CLK_POLICY_FREQ_PRIVED __BIT(31) 592 #define CLK_POLICY_FREQ_POLICY3 __BITS(26,24) 593 #define CLK_POLICY_FREQ_POLICY2 __BITS(18,16) 594 #define CLK_POLICY_FREQ_POLICY1 __BITS(10,8) 595 #define CLK_POLICY_FREQ_POLICY0 __BITS(2,0) 596 #define CLK_POLICY_REF_CLK 0 // 25 MHZ 597 #define CLK_POLICY_SYS_CLK 1 // sys clk (200MHZ) 598 #define CLK_POLICY_ARM_PLL_CH0 6 // slow clock 599 #define CLK_POLICY_ARM_PLL_CH1 7 // fast clock 600 601 #define ARMCORE_CLK_APB_DIV 0xa10 602 #define CLK_APB_DIV_PRIVED __BIT(31) 603 #define CLK_APB_DIV_VALUE __BITS(1,0) // n = n + 1 604 605 #define ARMCORE_CLK_APB_DIV_TRIGGER 0xa10 606 #define CLK_APB_DIV_TRIGGER_PRIVED __BIT(31) 607 #define CLK_APB_DIV_TRIGGER_OVERRIDE __BIT(0) 608 609 #define ARMCORE_CLK_PLLARMA 0xc00 610 #define CLK_PLLARMA_PDIV __BITS(26,24) // = (n ? n : 16(?)) 611 #define CLK_PLLARMA_NDIV_INT __BITS(17,8) // = (n ? n : 1024) 612 613 #define ARMCORE_CLK_PLLARMB 0xc04 614 #define CLK_PLLARMB_NDIV_FRAC __BITS(19,0) // = 1 / n 615 616 #endif 617 618 #ifdef IDM_PRIVATE 619 620 #define IDM_ARMCORE_M0_BASE 0x00000 621 #define IDM_PCIE_M0_BASE 0x01000 622 #define IDM_PCIE_M1_BASE 0x02000 623 #define IDM_PCIE_M2_BASE 0x03000 624 #define IDM_USB3_BASE 0x05000 625 #define IDM_ARMCORE_S1_BASE 0x06000 626 #define IDM_ARMCORE_S0_BASE 0x07000 627 #define IDM_DDR_S1_BASE 0x08000 628 #define IDM_DDR_S2_BASE 0x09000 629 #define IDM_ROM_S0_BASE 0x0d000 630 #define IDM_AMAC0_BASE 0x10000 631 #define IDM_AMAC1_BASE 0x11000 632 #define IDM_AMAC2_BASE 0x12000 633 #define IDM_AMAC3_BASE 0x13000 634 #define IDM_DMAC_M0_BASE 0x14000 635 #define IDM_USB2_BASE 0x15000 636 #define IDM_SDIO_BASE 0x16000 637 #define IDM_I2S_M0_BASE 0x17000 638 #define IDM_A9JTAG_M0_BASE 0x18000 639 #define IDM_NAND_BASE 0x1a000 640 #define IDM_QSPI_BASE 0x1b000 641 #define IDM_APBX_BASE 0x21000 642 643 #define IDM_IO_CONTROL_DIRECT 0x0408 644 #define IDM_IO_STATUS 0x0500 645 #define IDM_RESET_CONTROL 0x0800 646 #define IDM_RESET_STATUS 0x0804 647 #define IDM_INTERRUPT_STATUS 0x0a00 648 649 #define IO_CONTROL_DIRECT_ARUSER __BITS(29,25) 650 #define IO_CONTROL_DIRECT_AWUSER __BITS(24,20) 651 #define IO_CONTROL_DIRECT_ARCACHE __BITS(19,16) 652 #define IO_CONTROL_DIRECT_AWCACHE __BITS(10,7) 653 #define AXCACHE_WA __BIT(3) 654 #define AXCACHE_RA __BIT(2) 655 #define AXCACHE_C __BIT(1) 656 #define AXCACHE_B __BIT(0) 657 #define IO_CONTROL_DIRECT_UARTCLKSEL __BIT(17) 658 #define IO_CONTROL_DIRECT_CLK_250_SEL __BIT(6) 659 #define IO_CONTROL_DIRECT_DIRECT_GMII_MODE __BIT(5) 660 #define IO_CONTROL_DIRECT_TX_CLK_OUT_INVERT_EN __BIT(4) 661 #define IO_CONTROL_DIRECT_DEST_SYNC_MODE_EN __BIT(3) 662 #define IO_CONTROL_DIRECT_SOURCE_SYNC_MODE_EN __BIT(2) 663 #define IO_CONTROL_DIRECT_CLK_GATING_EN __BIT(0) 664 665 #define RESET_CONTROL_RESET __BIT(0) 666 667 #endif /* IDM_PRIVATE */ 668 669 #ifdef USBH_PRIVATE 670 #define USBH_PHY_CTRL_P0 0x200 671 #define USBH_PHY_CTRL_P1 0x204 672 673 #define USBH_PHY_CTRL_INIT 0x3ff 674 #endif 675 676 #ifdef GMAC_PRIVATE 677 678 struct gmac_txdb { 679 uint32_t txdb_flags; 680 uint32_t txdb_buflen; 681 uint32_t txdb_addrlo; 682 uint32_t txdb_addrhi; 683 }; 684 #define TXDB_FLAG_SF __BIT(31) // Start oF Frame 685 #define TXDB_FLAG_EF __BIT(30) // End oF Frame 686 #define TXDB_FLAG_IC __BIT(29) // Interupt on Completetion 687 #define TXDB_FLAG_ET __BIT(28) // End Of Table 688 689 struct gmac_rxdb { 690 uint32_t rxdb_flags; 691 uint32_t rxdb_buflen; 692 uint32_t rxdb_addrlo; 693 uint32_t rxdb_addrhi; 694 }; 695 #define RXDB_FLAG_SF __BIT(31) // Start oF Frame (ignored) 696 #define RXDB_FLAG_EF __BIT(30) // End oF Frame (ignored) 697 #define RXDB_FLAG_IC __BIT(29) // Interupt on Completetion 698 #define RXDB_FLAG_ET __BIT(28) // End Of Table 699 700 #define RXSTS_FRAMELEN __BITS(15,0) // # of bytes (including padding) 701 #define RXSTS_PKTTYPE __BITS(17,16) 702 #define RXSTS_PKTTYPE_UC 0 // Unicast 703 #define RXSTS_PKTTYPE_MC 1 // Multicast 704 #define RXSTS_PKTTYPE_BC 2 // Broadcast 705 #define RXSTS_VLAN_PRESENT __BIT(18) 706 #define RXSTS_CRC_ERROR __BIT(19) 707 #define RXSTS_OVERSIZED __BIT(20) 708 #define RXSTS_CTF_HIT __BIT(21) 709 #define RXSTS_CTF_ERROR __BIT(22) 710 #define RXSTS_PKT_OVERFLOW __BIT(23) 711 #define RXSTS_DESC_COUNT __BITS(27,24) // # of descriptors - 1 712 713 #define GMAC_DEVCONTROL 0x000 714 #define ENABLE_DEL_G_TXC __BIT(21) 715 #define ENABLE_DEL_G_RXC __BIT(20) 716 #define TXC_DRNG __BITS(19,18) 717 #define RXC_DRNG __BITS(17,16) 718 #define TXQ_FLUSH __BIT(8) 719 #define NWAY_AUTO_POLL_EN __BIT(7) 720 #define FLOW_CTRL_MODE __BITS(6,5) 721 #define MIB_RD_RESET_EN __BIT(4) 722 #define RGMII_LINK_STATUS_SEL __BIT(3) 723 #define CPU_FLOW_CTRL_ON __BIT(2) 724 #define RXQ_OVERFLOW_CTRL_SEL __BIT(1) 725 #define TXARB_STRICT_MODE __BIT(0) 726 #define GMAC_DEVSTATUS 0x004 727 #define GMAC_BISTSTATUS 0x00c 728 #define GMAC_INTSTATUS 0x020 729 #define GMAC_INTMASK 0x024 730 #define TXQECCUNCORRECTED __BIT(31) 731 #define TXQECCCORRECTED __BIT(30) 732 #define RXQECCUNCORRECTED __BIT(29) 733 #define RXQECCCORRECTED __BIT(28) 734 #define XMTINT_3 __BIT(27) 735 #define XMTINT_2 __BIT(26) 736 #define XMTINT_1 __BIT(25) 737 #define XMTINT_0 __BIT(24) 738 #define RCVINT __BIT(16) 739 #define XMTUF __BIT(15) 740 #define RCVFIFOOF __BIT(14) 741 #define RCVDESCUF __BIT(13) 742 #define DESCPROTOERR __BIT(12) 743 #define DATAERR __BIT(11) 744 #define DESCERR __BIT(10) 745 #define INT_SW_LINK_ST_CHG __BIT(8) 746 #define INT_TIMEOUT __BIT(7) 747 #define MIB_TX_INT __BIT(6) 748 #define MIB_RX_INT __BIT(5) 749 #define MDIOINT __BIT(4) 750 #define NWAYLINKSTATINT __BIT(3) 751 #define TXQ_FLUSH_DONEINT __BIT(2) 752 #define MIB_TX_OVERFLOW __BIT(1) 753 #define MIB_RX_OVERFLOW __BIT(0) 754 #define GMAC_GPTIMER 0x028 755 756 #define GMAC_INTRCVLAZY 0x100 757 #define INTRCVLAZY_FRAMECOUNT __BITS(31,24) 758 #define INTRCVLAZY_TIMEOUT __BITS(23,0) 759 #define GMAC_FLOWCNTL_TH 0x104 760 #define GMAC_TXARB_WRR_TH 0x108 761 #define GMAC_GMACIDLE_CNT_TH 0x10c 762 763 #define GMAC_FIFOACCESSADDR 0x120 764 #define GMAC_FIFOACCESSBYTE 0x124 765 #define GMAC_FIFOACCESSDATA 0x128 766 767 #define GMAC_PHYACCESS 0x180 768 #define GMAC_PHYCONTROL 0x188 769 #define GMAC_TXQCONTROL 0x18c 770 #define GMAC_RXQCONTROL 0x190 771 #define GMAC_GPIOSELECT 0x194 772 #define GMAC_GPIOOUTPUTEN 0x198 773 #define GMAC_TXQRXQMEMORYCONTROL 0x1a0 774 #define GMAC_MEMORYECCSTATUS 0x1a4 775 776 #define GMAC_CLOCKCONTROLSTATUS 0x1e0 777 #define GMAC_POWERCONTROL 0x1e8 778 779 #define GMAC_XMTCONTROL 0x200 780 #define XMTCTL_PREFETCH_THRESH __BITS(25,24) 781 #define XMTCTL_PREFETCH_CTL __BITS(23,21) 782 #define XMTCTL_BURSTLEN __BITS(20,18) 783 #define XMTCTL_ADDREXT __BITS(17,16) 784 #define XMTCTL_DMA_ACT_INDEX __BIT(13) 785 #define XMTCTL_PARITY_DIS __BIT(11) 786 #define XMTCTL_OUTSTANDING_READS __BITS(7,6) 787 #define XMTCTL_BURST_ALIGN_EN __BIT(5) 788 #define XMTCTL_DMA_LOOPBACK __BIT(2) 789 #define XMTCTL_SUSPEND __BIT(1) 790 #define XMTCTL_ENABLE __BIT(0) 791 #define GMAC_XMTPTR 0x204 792 #define XMT_LASTDSCR __BITS(11,4) 793 #define GMAC_XMTADDR_LOW 0x208 794 #define GMAC_XMTADDR_HIGH 0x20c 795 #define GMAC_XMTSTATUS0 0x210 796 #define XMTSTATE __BITS(31,28) 797 #define XMTSTATE_DIS 0 798 #define XMTSTATE_ACTIVE 1 799 #define XMTSTATE_IDLE_WAIT 2 800 #define XMTSTATE_STOPPED 3 801 #define XMTSTATE_SUSP_PENDING 4 802 #define XMT_CURRDSCR __BITS(11,4) 803 #define GMAC_XMTSTATUS1 0x214 804 #define XMTERR __BITS(31,28) 805 #define XMT_ACTIVEDSCR __BITS(11,4) 806 #define GMAC_RCVCONTROL 0x220 807 #define RCVCTL_PREFETCH_THRESH __BITS(25,24) 808 #define RCVCTL_PREFETCH_CTL __BITS(23,21) 809 #define RCVCTL_BURSTLEN __BITS(20,18) 810 #define RCVCTL_ADDREXT __BITS(17,16) 811 #define RCVCTL_DMA_ACT_INDEX __BIT(13) 812 #define RCVCTL_PARITY_DIS __BIT(11) 813 #define RCVCTL_OFLOW_CONTINUE __BIT(10) 814 #define RCVCTL_SEPRXHDRDESC __BIT(9) 815 #define RCVCTL_RCVOFFSET __BITS(7,1) 816 #define RCVCTL_ENABLE __BIT(0) 817 #define GMAC_RCVPTR 0x224 818 #define RCVPTR __BITS(11,4) 819 #define GMAC_RCVADDR_LOW 0x228 820 #define GMAC_RCVADDR_HIGH 0x22c 821 #define GMAC_RCVSTATUS0 0x230 822 #define RCVSTATE __BITS(31,28) 823 #define RCVSTATE_DIS 0 824 #define RCVSTATE_ACTIVE 1 825 #define RCVSTATE_IDLE_WAIT 2 826 #define RCVSTATE_STOPPED 3 827 #define RCVSTATE_SUSP_PENDING 4 828 #define RCV_CURRDSCR __BITS(11,4) 829 #define GMAC_RCVSTATUS1 0x234 830 #define RCV_ACTIVEDSCR __BITS(11,4) 831 832 #define GMAC_TX_GD_OCTETS_LO 0x300 833 834 835 #define UNIMAC_IPG_HD_BPG_CNTL 0x804 836 #define UNIMAC_COMMAND_CONFIG 0x808 837 #define RUNT_FILTER_DIS __BIT(30) 838 #define OOB_EFC_EN __BIT(29) 839 #define IGNORE_TX_PAUSE __BIT(28) 840 #define PRBL_ENA __BIT(27) 841 #define RX_ERR_DIS __BIT(26) 842 #define LINE_LOOPBACK __BIT(25) 843 #define NO_LENGTH_CHECK __BIT(24) 844 #define CNTRL_FRM_ENA __BIT(23) 845 #define ENA_EXT_CONFIG __BIT(22) 846 #define EN_INTERNAL_TX_CRS __BIT(21) 847 #define SW_OVERRIDE_RX __BIT(18) 848 #define SW_OVERRIDE_TX __BIT(17) 849 #define MAC_LOOP_CON __BIT(16) 850 #define LOOP_ENA __BIT(15) 851 #define RCS_CORRUPT_URUN_EN __BIT(14) 852 #define SW_RESET __BIT(13) 853 #define OVERFLOW_EN __BIT(12) 854 #define RX_LOW_LATENCY_EN __BIT(11) 855 #define HD_ENA __BIT(10) 856 #define TX_ADDR_INS __BIT(9) 857 #define PAUSE_IGNORE __BIT(8) 858 #define PAUSE_FWD __BIT(7) 859 #define CRC_FWD __BIT(6) 860 #define PAD_EN __BIT(5) 861 #define PROMISC_EN __BIT(4) 862 #define ETH_SPEED __BITS(3,2) 863 #define ETH_SPEED_10 0 864 #define ETH_SPEED_100 1 865 #define ETH_SPEED_1000 2 866 #define ETH_SPEED_2500 3 867 #define RX_ENA __BIT(1) 868 #define TX_ENA __BIT(0) 869 #define UNIMAC_MAC_0 0x80c // bits 16:47 of macaddr 870 #define UNIMAC_MAC_1 0x810 // bits 0:15 of macaddr 871 #define UNIMAC_FRAME_LEN 0x814 872 #define UNIMAC_PAUSE_QUANTA 0x818 873 #define UNIMAC_TX_TS_SEQ_ID 0x83c 874 #define UNIMAC_MAC_MODE 0x844 875 #define UNIMAC_TAG_0 0x848 876 #define UNIMAC_TAG_1 0x84c 877 #define UNIMAC_RX_PAUSE_QUANTA_SCALE 0x850 878 #define UNIMAC_TX_PREAMBLE 0x854 879 #define UNIMAC_TX_IPG_LENGTH 0x85c 880 #define UNIMAC_PRF_XOFF_TIMER 0x860 881 #define UNIMAC_UMAC_EEE_CTRL 0x864 882 #define UNIMAC_MII_EEE_DELAY_ENTRY_TIMER 0x868 883 #define UNIMAC_GMII_EEE_DELAY_ENTRY_TIMER 0x86c 884 #define UNIMAC_UMAC_EEE_REF_COUNT 0x870 885 #define UNIMAC_UMAX_RX_PKT_DROP_STATUS 0x878 886 887 #define UNIMAC_UMAC_SYMMETRIC_IDLE_THRESHOLD 0x87c // RX IDLE threshold for LPI prediction 888 #define UNIMAC_MII_EEE_WAKE_TIMER 0x880 // MII_EEE Wake timer 889 #define UNIMAC_GMII_EEE_WAKE_TIMER 0x884 // GMII_EEE Wake timer 890 #define UNIMAC_UMAC_REV_ID 0x888 // UNIMAC_REV_ID 891 #define UNIMAC_MAC_PFC_TYPE 0xb00 // Programmable ethertype (GNAT 13440) 892 #define UNIMAC_MAC_PFC_OPCODE 0xb04 // Programmable opcode (GNAT 13440) 893 #define UNIMAC_MAC_PFC_DA_0 0xb08 // lower 32 bits of programmable DA for PPP (GNAT 13897) 894 #define UNIMAC_MAC_PFC_DA_1 0xb0c // upper 16 bits of programmable DA for PPP (GNAT 13897) 895 #define UNIMAC_MACSEC_CNTRL 0xb14 // Miscellaneous control for MACSEC (GNAT 11599,11600,12078,12198) 896 #define UNIMAC_TS_STATUS_CNTRL 0xb18 // Timestamp control/status 897 #define UNIMAC_TX_TS_DATA 0xb1c // Transmit Timestamp data 898 #define UNIMAC_PAUSE_CONTROL 0xb30 // PAUSE frame timer control register 899 #define UNIMAC_FLUSH_CONTROL 0xb34 // Flush enable control register 900 #define UNIMAC_RXFIFO_STAT 0xb38 // RXFIFO status register 901 #define UNIMAC_TXFIFO_STAT 0xb3c // TXFIFO status register 902 #define UNIMAC_MAC_PFC_CTRL 0xb40 // PPP control register 903 #define UNIMAC_MAC_PFC_REFRESH_CTRL 0xb44 // PPP refresh control register 904 905 #endif /* GMAC_PRIVATE */ 906 907 #endif /* _ARM_BROADCOM_BCM53XX_REG_H_ */ 908