1 /* $NetBSD: bcm53xx_board.c,v 1.21 2014/03/26 03:19:11 matt Exp $ */ 2 /*- 3 * Copyright (c) 2012 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas of 3am Software Foundry. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "opt_broadcom.h" 32 #include "arml2cc.h" 33 34 #define _ARM32_BUS_DMA_PRIVATE 35 36 #include <sys/cdefs.h> 37 38 __KERNEL_RCSID(1, "$NetBSD: bcm53xx_board.c,v 1.21 2014/03/26 03:19:11 matt Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/bus.h> 42 #include <sys/cpu.h> 43 #include <sys/device.h> 44 45 #include <prop/proplib.h> 46 47 #include <net/if.h> 48 #include <net/if_ether.h> 49 50 #define CCA_PRIVATE 51 #define CRU_PRIVATE 52 #define DDR_PRIVATE 53 #define DMU_PRIVATE 54 #define ARMCORE_PRIVATE 55 #define SRAB_PRIVATE 56 57 #include <arm/cortex/a9tmr_var.h> 58 #include <arm/cortex/pl310_var.h> 59 #include <arm/mainbus/mainbus.h> 60 61 #include <arm/broadcom/bcm53xx_reg.h> 62 #include <arm/broadcom/bcm53xx_var.h> 63 64 bus_space_tag_t bcm53xx_ioreg_bst = &bcmgen_bs_tag; 65 bus_space_handle_t bcm53xx_ioreg_bsh; 66 bus_space_tag_t bcm53xx_armcore_bst = &bcmgen_bs_tag; 67 bus_space_handle_t bcm53xx_armcore_bsh; 68 69 static struct cpu_softc cpu_softc; 70 71 struct arm32_dma_range bcm53xx_dma_ranges[] = { 72 #ifdef BCM5301X 73 [0] = { 74 .dr_sysbase = 0x80000000, 75 .dr_busbase = 0x80000000, 76 .dr_len = 0x10000000, 77 }, [1] = { 78 .dr_sysbase = 0x90000000, 79 .dr_busbase = 0x90000000, 80 }, 81 #elif defined(BCM563XX) 82 [0] = { 83 .dr_sysbase = 0x60000000, 84 .dr_busbase = 0x60000000, 85 .dr_len = 0x20000000, 86 }, [1] = { 87 .dr_sysbase = 0x80000000, 88 .dr_busbase = 0x80000000, 89 }, 90 #endif 91 }; 92 93 struct arm32_bus_dma_tag bcm53xx_dma_tag = { 94 ._ranges = bcm53xx_dma_ranges, 95 ._nranges = __arraycount(bcm53xx_dma_ranges), 96 _BUS_DMAMAP_FUNCS, 97 _BUS_DMAMEM_FUNCS, 98 _BUS_DMATAG_FUNCS, 99 }; 100 101 struct arm32_dma_range bcm53xx_coherent_dma_ranges[] = { 102 #ifdef BCM5301X 103 [0] = { 104 .dr_sysbase = 0x80000000, 105 .dr_busbase = 0x80000000, 106 .dr_len = 0x10000000, 107 .dr_flags = _BUS_DMAMAP_COHERENT, 108 }, [1] = { 109 .dr_sysbase = 0x90000000, 110 .dr_busbase = 0x90000000, 111 }, 112 #elif defined(BCM563XX) 113 [0] = { 114 .dr_sysbase = 0x60000000, 115 .dr_busbase = 0x60000000, 116 .dr_len = 0x20000000, 117 .dr_flags = _BUS_DMAMAP_COHERENT, 118 }, [1] = { 119 .dr_sysbase = 0x80000000, 120 .dr_busbase = 0x80000000, 121 }, 122 #endif 123 }; 124 125 struct arm32_bus_dma_tag bcm53xx_coherent_dma_tag = { 126 ._ranges = bcm53xx_coherent_dma_ranges, 127 ._nranges = __arraycount(bcm53xx_coherent_dma_ranges), 128 _BUS_DMAMAP_FUNCS, 129 _BUS_DMAMEM_FUNCS, 130 _BUS_DMATAG_FUNCS, 131 }; 132 133 #ifdef _ARM32_NEED_BUS_DMA_BOUNCE 134 struct arm32_bus_dma_tag bcm53xx_bounce_dma_tag = { 135 ._ranges = bcm53xx_coherent_dma_ranges, 136 ._nranges = 1, 137 _BUS_DMAMAP_FUNCS, 138 _BUS_DMAMEM_FUNCS, 139 _BUS_DMATAG_FUNCS, 140 }; 141 #endif 142 143 #ifdef BCM53XX_CONSOLE_EARLY 144 #include <dev/ic/ns16550reg.h> 145 #include <dev/ic/comreg.h> 146 #include <dev/cons.h> 147 148 static vaddr_t com_base; 149 150 static inline uint32_t 151 uart_read(bus_size_t o) 152 { 153 return *(volatile uint8_t *)(com_base + o); 154 } 155 156 static inline void 157 uart_write(bus_size_t o, uint32_t v) 158 { 159 *(volatile uint8_t *)(com_base + o) = v; 160 } 161 162 static int 163 bcm53xx_cngetc(dev_t dv) 164 { 165 if ((uart_read(com_lsr) & LSR_RXRDY) == 0) 166 return -1; 167 168 return uart_read(com_data) & 0xff; 169 } 170 171 static void 172 bcm53xx_cnputc(dev_t dv, int c) 173 { 174 int timo = 150000; 175 176 while ((uart_read(com_lsr) & LSR_TXRDY) == 0 && --timo > 0) 177 ; 178 179 uart_write(com_data, c); 180 181 timo = 150000; 182 while ((uart_read(com_lsr) & LSR_TSRE) == 0 && --timo > 0) 183 ; 184 } 185 186 static struct consdev bcm53xx_earlycons = { 187 .cn_putc = bcm53xx_cnputc, 188 .cn_getc = bcm53xx_cngetc, 189 .cn_pollc = nullcnpollc, 190 }; 191 #endif /* BCM53XX_CONSOLE_EARLY */ 192 193 psize_t 194 bcm53xx_memprobe(void) 195 { 196 bus_space_tag_t bst = bcm53xx_ioreg_bst; 197 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 198 199 /* 200 * First, let's read the magic DDR registers! 201 */ 202 const uint32_t v01 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_01); 203 const uint32_t v82 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_82); 204 const uint32_t v86 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_86); 205 const uint32_t v87 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_87); 206 207 /* 208 * Calculate chip parameters 209 * */ 210 const u_int rows = __SHIFTOUT(v01, CTL_01_MAX_ROW) 211 - __SHIFTOUT(v82, CTL_82_ROW_DIFF); 212 const u_int cols = __SHIFTOUT(v01, CTL_01_MAX_COL) 213 - __SHIFTOUT(v82, CTL_82_COL_DIFF); 214 const u_int banks_log2 = 3 - __SHIFTOUT(v82, CTL_82_BANK_DIFF); 215 216 /* 217 * For each chip select, increase the chip count if if is enabled. 218 */ 219 const u_int max_chips = __SHIFTOUT(v01, CTL_01_MAX_CHIP_SEL); 220 u_int cs_map = __SHIFTOUT(v86, CTL_86_CS_MAP); 221 u_int chips = 0; 222 223 for (u_int i = 0; cs_map != 0 && i < max_chips; i++, cs_map >>= 1) { 224 chips += (cs_map & 1); 225 } 226 227 /* get log2(ddr width) */ 228 229 const u_int ddr_width_log2 = (v87 & CTL_87_REDUC) ? 1 : 2; 230 231 /* 232 * Let's add up all the things that contribute to the size of a chip. 233 */ 234 const u_int chip_size_log2 = cols + rows + banks_log2 + ddr_width_log2; 235 236 /* 237 * Now our memory size is simply the number of chip shifted by the 238 * log2(chip_size). 239 */ 240 return (psize_t) chips << chip_size_log2; 241 } 242 243 static inline uint32_t 244 bcm53xx_freq_calc(struct bcm53xx_clock_info *clk, 245 uint32_t pdiv, uint32_t ndiv_int, uint32_t ndiv_frac) 246 { 247 if (ndiv_frac == 0 && pdiv == 1) 248 return ndiv_int * clk->clk_ref; 249 250 uint64_t freq64 = ((uint64_t)ndiv_int << 30) + ndiv_frac; 251 freq64 *= clk->clk_ref; 252 if (pdiv > 1) 253 freq64 /= pdiv; 254 return (uint32_t) (freq64 >> 30); 255 } 256 257 static uint32_t 258 bcm53xx_value_wrap(uint32_t value, uint32_t mask) 259 { 260 /* 261 * n is n except when n is 0 then n = mask + 1. 262 */ 263 return ((__SHIFTOUT(value, mask) - 1) & __SHIFTOUT(mask, mask)) + 1; 264 } 265 266 static void 267 bcm53xx_genpll_clock_init(struct bcm53xx_clock_info *clk, uint32_t control5, 268 uint32_t control6, uint32_t control7) 269 { 270 const uint32_t pdiv = bcm53xx_value_wrap(control6, 271 GENPLL_CONTROL6_PDIV); 272 const uint32_t ndiv_int = bcm53xx_value_wrap(control5, 273 GENPLL_CONTROL5_NDIV_INT); 274 const uint32_t ndiv_frac = __SHIFTOUT(control5, 275 GENPLL_CONTROL5_NDIV_FRAC); 276 277 clk->clk_genpll = bcm53xx_freq_calc(clk, pdiv, ndiv_int, ndiv_frac); 278 279 const uint32_t ch0_mdiv = bcm53xx_value_wrap(control6, 280 GENPLL_CONTROL6_CH0_MDIV); 281 const uint32_t ch1_mdiv = bcm53xx_value_wrap(control6, 282 GENPLL_CONTROL6_CH1_MDIV); 283 const uint32_t ch2_mdiv = bcm53xx_value_wrap(control6, 284 GENPLL_CONTROL6_CH2_MDIV); 285 const uint32_t ch3_mdiv = bcm53xx_value_wrap(control7, 286 GENPLL_CONTROL7_CH3_MDIV); 287 288 clk->clk_mac = clk->clk_genpll / ch0_mdiv; // GENPLL CH0 289 clk->clk_robo = clk->clk_genpll / ch1_mdiv; // GENPLL CH1 290 clk->clk_usb2 = clk->clk_genpll / ch2_mdiv; // GENPLL CH2 291 clk->clk_iproc = clk->clk_genpll / ch3_mdiv; // GENPLL CH3 292 } 293 294 static void 295 bcm53xx_lcpll_clock_init(struct bcm53xx_clock_info *clk, uint32_t control1, 296 uint32_t control2) 297 { 298 const uint32_t pdiv = bcm53xx_value_wrap(control1, 299 LCPLL_CONTROL1_PDIV); 300 const uint32_t ndiv_int = bcm53xx_value_wrap(control1, 301 LCPLL_CONTROL1_NDIV_INT); 302 const uint32_t ndiv_frac = __SHIFTOUT(control1, 303 LCPLL_CONTROL1_NDIV_FRAC); 304 305 clk->clk_lcpll = bcm53xx_freq_calc(clk, pdiv, ndiv_int, ndiv_frac); 306 307 const uint32_t ch0_mdiv = bcm53xx_value_wrap(control2, 308 LCPLL_CONTROL2_CH0_MDIV); 309 const uint32_t ch1_mdiv = bcm53xx_value_wrap(control2, 310 LCPLL_CONTROL2_CH1_MDIV); 311 const uint32_t ch2_mdiv = bcm53xx_value_wrap(control2, 312 LCPLL_CONTROL2_CH2_MDIV); 313 const uint32_t ch3_mdiv = bcm53xx_value_wrap(control2, 314 LCPLL_CONTROL2_CH3_MDIV); 315 316 clk->clk_pcie_ref = clk->clk_lcpll / ch0_mdiv; // LCPLL CH0 317 clk->clk_sdio = clk->clk_lcpll / ch1_mdiv; // LCPLL CH1 318 clk->clk_ddr_ref = clk->clk_lcpll / ch2_mdiv; // LCPLL CH2 319 clk->clk_axi = clk->clk_lcpll / ch3_mdiv; // LCPLL CH3 320 } 321 322 static void 323 bcm53xx_usb_clock_init(struct bcm53xx_clock_info *clk, uint32_t usb2_control) 324 { 325 const uint32_t pdiv = bcm53xx_value_wrap(usb2_control, 326 USB2_CONTROL_PDIV); 327 const uint32_t ndiv = bcm53xx_value_wrap(usb2_control, 328 USB2_CONTROL_NDIV_INT); 329 330 uint32_t usb_ref = (clk->clk_usb2 / pdiv) * ndiv; 331 if (usb_ref != USB2_REF_CLK) { 332 /* 333 * USB Reference Clock isn't 1.92GHz. So we need to modify 334 * USB2_CONTROL to produce it. 335 */ 336 uint32_t new_ndiv = (USB2_REF_CLK / clk->clk_usb2) * pdiv; 337 usb2_control &= ~USB2_CONTROL_NDIV_INT; 338 usb2_control |= __SHIFTIN(new_ndiv, USB2_CONTROL_NDIV_INT); 339 340 // Allow Clocks to be modified 341 bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh, 342 CRU_BASE + CRU_CLKSET_KEY, CRU_CLKSET_KEY_MAGIC); 343 344 // Update USB2 clock generator 345 bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh, 346 CRU_BASE + CRU_USB2_CONTROL, usb2_control); 347 348 // Prevent Clock modification 349 bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh, 350 CRU_BASE + CRU_CLKSET_KEY, 0); 351 352 usb_ref = (clk->clk_usb2 / pdiv) * new_ndiv; 353 } 354 355 clk->clk_usb_ref = usb_ref; 356 } 357 358 359 static void 360 bcm53xx_clock_init(struct bcm53xx_clock_info *clk) 361 { 362 clk->clk_ref = BCM53XX_REF_CLK; 363 clk->clk_sys = 8*clk->clk_ref; 364 } 365 366 /* 367 * F(ddr) = ((1 / pdiv) * ndiv * CH2) / (post_div * 2) 368 */ 369 static void 370 bcm53xx_get_ddr_freq(struct bcm53xx_clock_info *clk, uint32_t pll_status, 371 uint32_t pll_dividers) 372 { 373 const bool clocking_4x = (pll_status & PLL_STATUS_CLOCKING_4X) != 0; 374 u_int post_div = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_POST_DIV); 375 u_int pdiv = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_PDIV); 376 u_int ndiv = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_NDIV); 377 378 pdiv = ((pdiv - (clocking_4x ? 1 : 5)) & 7) + 1; 379 380 clk->clk_ddr_mhz = __SHIFTOUT(pll_status, PLL_STATUS_MHZ); 381 clk->clk_ddr = (clk->clk_ddr_ref / pdiv) * ndiv / (2 + post_div); 382 } 383 384 /* 385 * CPU_CLK = (1 / pdiv) * (ndiv_int + (ndiv_frac / 0x40000000)) x F(ref) 386 */ 387 static void 388 bcm53xx_get_cpu_freq(struct bcm53xx_clock_info *clk, 389 uint32_t pllarma, uint32_t pllarmb, uint32_t policy) 390 { 391 policy = __SHIFTOUT(policy, CLK_POLICY_FREQ_POLICY2); 392 393 if (policy == CLK_POLICY_REF_CLK) { 394 clk->clk_cpu = clk->clk_ref; 395 clk->clk_apb = clk->clk_cpu; 396 return; 397 } 398 399 if (policy == CLK_POLICY_SYS_CLK) { 400 clk->clk_cpu = clk->clk_sys; 401 clk->clk_apb = clk->clk_cpu / 4; 402 return; 403 } 404 405 const u_int pdiv = bcm53xx_value_wrap(pllarma, CLK_PLLARMA_PDIV); 406 const u_int ndiv_int = bcm53xx_value_wrap(pllarma, CLK_PLLARMA_NDIV_INT); 407 const u_int ndiv_frac = __SHIFTOUT(pllarmb, CLK_PLLARMB_NDIV_FRAC); 408 // const u_int apb_clk_div = __SHIFTOUT(apb_clk_div, CLK_APB_DIV_VALUE)+1; 409 410 const u_int cpu_div = (policy == CLK_POLICY_ARM_PLL_CH0) ? 4 : 2; 411 412 clk->clk_cpu = bcm53xx_freq_calc(clk, pdiv, ndiv_int, ndiv_frac) / cpu_div; 413 clk->clk_apb = clk->clk_cpu / 4; 414 } 415 416 struct bcm53xx_chip_state { 417 uint32_t bcs_lcpll_control1; 418 uint32_t bcs_lcpll_control2; 419 420 uint32_t bcs_genpll_control5; 421 uint32_t bcs_genpll_control6; 422 uint32_t bcs_genpll_control7; 423 424 uint32_t bcs_usb2_control; 425 426 uint32_t bcs_ddr_phy_ctl_pll_status; 427 uint32_t bcs_ddr_phy_ctl_pll_dividers; 428 429 uint32_t bcs_armcore_clk_policy; 430 uint32_t bcs_armcore_clk_pllarma; 431 uint32_t bcs_armcore_clk_pllarmb; 432 }; 433 434 static void 435 bcm53xx_get_chip_ioreg_state(struct bcm53xx_chip_state *bcs, 436 bus_space_tag_t bst, bus_space_handle_t bsh) 437 { 438 bcs->bcs_lcpll_control1 = bus_space_read_4(bst, bsh, 439 DMU_BASE + DMU_LCPLL_CONTROL1); 440 bcs->bcs_lcpll_control2 = bus_space_read_4(bst, bsh, 441 DMU_BASE + DMU_LCPLL_CONTROL2); 442 443 bcs->bcs_genpll_control5 = bus_space_read_4(bst, bsh, 444 CRU_BASE + CRU_GENPLL_CONTROL5); 445 bcs->bcs_genpll_control6 = bus_space_read_4(bst, bsh, 446 CRU_BASE + CRU_GENPLL_CONTROL6); 447 bcs->bcs_genpll_control7 = bus_space_read_4(bst, bsh, 448 CRU_BASE + CRU_GENPLL_CONTROL7); 449 450 bcs->bcs_usb2_control = bus_space_read_4(bst, bsh, 451 CRU_BASE + CRU_USB2_CONTROL); 452 453 bcs->bcs_ddr_phy_ctl_pll_status = bus_space_read_4(bst, bsh, 454 DDR_BASE + DDR_PHY_CTL_PLL_STATUS); 455 bcs->bcs_ddr_phy_ctl_pll_dividers = bus_space_read_4(bst, bsh, 456 DDR_BASE + DDR_PHY_CTL_PLL_DIVIDERS); 457 } 458 459 static void 460 bcm53xx_get_chip_armcore_state(struct bcm53xx_chip_state *bcs, 461 bus_space_tag_t bst, bus_space_handle_t bsh) 462 { 463 bcs->bcs_armcore_clk_policy = bus_space_read_4(bst, bsh, 464 ARMCORE_CLK_POLICY_FREQ); 465 bcs->bcs_armcore_clk_pllarma = bus_space_read_4(bst, bsh, 466 ARMCORE_CLK_PLLARMA); 467 bcs->bcs_armcore_clk_pllarmb = bus_space_read_4(bst, bsh, 468 ARMCORE_CLK_PLLARMB); 469 } 470 471 void 472 bcm53xx_cpu_softc_init(struct cpu_info *ci) 473 { 474 struct cpu_softc * const cpu = ci->ci_softc; 475 476 cpu->cpu_ioreg_bst = bcm53xx_ioreg_bst; 477 cpu->cpu_ioreg_bsh = bcm53xx_ioreg_bsh; 478 479 cpu->cpu_armcore_bst = bcm53xx_armcore_bst; 480 cpu->cpu_armcore_bsh = bcm53xx_armcore_bsh; 481 482 const uint32_t chipid = bus_space_read_4(cpu->cpu_ioreg_bst, 483 cpu->cpu_ioreg_bsh, CCA_MISC_BASE + MISC_CHIPID); 484 485 cpu->cpu_chipid = __SHIFTOUT(chipid, CHIPID_ID); 486 } 487 488 void 489 bcm53xx_print_clocks(void) 490 { 491 #if defined(VERBOSE_INIT_ARM) 492 const struct bcm53xx_clock_info * const clk = &cpu_softc.cpu_clk; 493 printf("ref clk = %u (%#x)\n", clk->clk_ref, clk->clk_ref); 494 printf("sys clk = %u (%#x)\n", clk->clk_sys, clk->clk_sys); 495 printf("lcpll clk = %u (%#x)\n", clk->clk_lcpll, clk->clk_lcpll); 496 printf("pcie ref clk = %u (%#x) [CH0]\n", clk->clk_pcie_ref, clk->clk_pcie_ref); 497 printf("sdio clk = %u (%#x) [CH1]\n", clk->clk_sdio, clk->clk_sdio); 498 printf("ddr ref clk = %u (%#x) [CH2]\n", clk->clk_ddr_ref, clk->clk_ddr_ref); 499 printf("axi clk = %u (%#x) [CH3]\n", clk->clk_axi, clk->clk_axi); 500 printf("genpll clk = %u (%#x)\n", clk->clk_genpll, clk->clk_genpll); 501 printf("mac clk = %u (%#x) [CH0]\n", clk->clk_mac, clk->clk_mac); 502 printf("robo clk = %u (%#x) [CH1]\n", clk->clk_robo, clk->clk_robo); 503 printf("usb2 clk = %u (%#x) [CH2]\n", clk->clk_usb2, clk->clk_usb2); 504 printf("iproc clk = %u (%#x) [CH3]\n", clk->clk_iproc, clk->clk_iproc); 505 printf("ddr clk = %u (%#x)\n", clk->clk_ddr, clk->clk_ddr); 506 printf("ddr mhz = %u (%#x)\n", clk->clk_ddr_mhz, clk->clk_ddr_mhz); 507 printf("cpu clk = %u (%#x)\n", clk->clk_cpu, clk->clk_cpu); 508 printf("apb clk = %u (%#x)\n", clk->clk_apb, clk->clk_apb); 509 printf("usb ref clk = %u (%#x)\n", clk->clk_usb_ref, clk->clk_usb_ref); 510 #endif 511 } 512 513 void 514 bcm53xx_bootstrap(vaddr_t iobase) 515 { 516 struct bcm53xx_chip_state bcs; 517 int error; 518 519 #ifdef BCM53XX_CONSOLE_EARLY 520 com_base = iobase + CCA_UART0_BASE; 521 cn_tab = &bcm53xx_earlycons; 522 #endif 523 524 bcm53xx_ioreg_bsh = (bus_space_handle_t) iobase; 525 error = bus_space_map(bcm53xx_ioreg_bst, BCM53XX_IOREG_PBASE, 526 BCM53XX_IOREG_SIZE, 0, &bcm53xx_ioreg_bsh); 527 if (error) 528 panic("%s: failed to map BCM53xx %s registers: %d", 529 __func__, "io", error); 530 531 bcm53xx_armcore_bsh = (bus_space_handle_t) iobase + BCM53XX_IOREG_SIZE; 532 error = bus_space_map(bcm53xx_armcore_bst, BCM53XX_ARMCORE_PBASE, 533 BCM53XX_ARMCORE_SIZE, 0, &bcm53xx_armcore_bsh); 534 if (error) 535 panic("%s: failed to map BCM53xx %s registers: %d", 536 __func__, "armcore", error); 537 538 curcpu()->ci_softc = &cpu_softc; 539 540 bcm53xx_get_chip_ioreg_state(&bcs, bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh); 541 bcm53xx_get_chip_armcore_state(&bcs, bcm53xx_armcore_bst, bcm53xx_armcore_bsh); 542 543 struct bcm53xx_clock_info * const clk = &cpu_softc.cpu_clk; 544 545 bcm53xx_clock_init(clk); 546 bcm53xx_lcpll_clock_init(clk, bcs.bcs_lcpll_control1, 547 bcs.bcs_lcpll_control2); 548 bcm53xx_genpll_clock_init(clk, bcs.bcs_genpll_control5, 549 bcs.bcs_genpll_control6, bcs.bcs_genpll_control7); 550 bcm53xx_usb_clock_init(clk, bcs.bcs_usb2_control); 551 bcm53xx_get_ddr_freq(clk, bcs.bcs_ddr_phy_ctl_pll_status, 552 bcs.bcs_ddr_phy_ctl_pll_dividers); 553 bcm53xx_get_cpu_freq(clk, bcs.bcs_armcore_clk_pllarma, 554 bcs.bcs_armcore_clk_pllarmb, bcs.bcs_armcore_clk_policy); 555 556 curcpu()->ci_data.cpu_cc_freq = clk->clk_cpu; 557 558 #if NARML2CC > 0 559 arml2cc_init(bcm53xx_armcore_bst, bcm53xx_armcore_bsh, 560 ARMCORE_L2C_BASE); 561 #endif 562 } 563 564 void 565 bcm53xx_dma_bootstrap(psize_t memsize) 566 { 567 if (memsize <= 256*1024*1024) { 568 bcm53xx_dma_ranges[0].dr_len = memsize; 569 bcm53xx_coherent_dma_ranges[0].dr_len = memsize; 570 bcm53xx_dma_tag._nranges = 1; 571 bcm53xx_coherent_dma_tag._nranges = 1; 572 } else { 573 /* 574 * By setting up two ranges, bus_dmamem_alloc will always 575 * try to allocate from range 0 first resulting in allocations 576 * below 256MB which for PCI and GMAC are coherent. 577 */ 578 bcm53xx_dma_ranges[1].dr_len = memsize - 0x10000000; 579 bcm53xx_coherent_dma_ranges[1].dr_len = memsize - 0x10000000; 580 } 581 KASSERT(bcm53xx_dma_tag._ranges[0].dr_flags == 0); 582 KASSERT(bcm53xx_coherent_dma_tag._ranges[0].dr_flags == _BUS_DMAMAP_COHERENT); 583 #ifdef _ARM32_NEED_BUS_DMA_BOUNCE 584 KASSERT(bcm53xx_bounce_dma_tag._ranges[0].dr_flags == _BUS_DMAMAP_COHERENT); 585 #endif 586 } 587 588 #ifdef MULTIPROCESSOR 589 void 590 bcm53xx_cpu_hatch(struct cpu_info *ci) 591 { 592 a9tmr_init_cpu_clock(ci); 593 } 594 #endif 595 596 void 597 bcm53xx_device_register(device_t self, void *aux) 598 { 599 prop_dictionary_t dict = device_properties(self); 600 601 if (device_is_a(self, "armperiph") 602 && device_is_a(device_parent(self), "mainbus")) { 603 /* 604 * XXX KLUDGE ALERT XXX 605 * The iot mainbus supplies is completely wrong since it scales 606 * addresses by 2. The simpliest remedy is to replace with our 607 * bus space used for the armcore regisers (which armperiph uses). 608 */ 609 struct mainbus_attach_args * const mb = aux; 610 mb->mb_iot = bcm53xx_armcore_bst; 611 return; 612 } 613 614 /* 615 * We need to tell the A9 Global/Watchdog Timer 616 * what frequency it runs at. 617 */ 618 if (device_is_a(self, "a9tmr") || device_is_a(self, "a9wdt")) { 619 /* 620 * This clock always runs at (arm_clk div 2) and only goes 621 * to timers that are part of the A9 MP core subsystem. 622 */ 623 prop_dictionary_set_uint32(dict, "frequency", 624 cpu_softc.cpu_clk.clk_cpu / 2); 625 return; 626 } 627 628 if (device_is_a(self, "bcmeth")) { 629 const struct bcmccb_attach_args * const ccbaa = aux; 630 const uint8_t enaddr[ETHER_ADDR_LEN] = { 631 0x00, 0x01, 0x02, 0x03, 0x04, 632 0x05 + 2 * ccbaa->ccbaa_loc.loc_port, 633 }; 634 prop_data_t pd = prop_data_create_data(enaddr, ETHER_ADDR_LEN); 635 KASSERT(pd != NULL); 636 if (prop_dictionary_set(device_properties(self), "mac-address", pd) == false) { 637 printf("WARNING: Unable to set mac-address property for %s\n", device_xname(self)); 638 } 639 prop_object_release(pd); 640 } 641 } 642 643 #ifdef SRAB_BASE 644 static kmutex_t srab_lock __cacheline_aligned; 645 646 void 647 bcm53xx_srab_init(void) 648 { 649 mutex_init(&srab_lock, MUTEX_DEFAULT, IPL_VM); 650 651 bcm53xx_srab_write_4(0x0079, 0x90); // reset switch 652 for (u_int port = 0; port < 8; port++) { 653 /* per port control: no stp */ 654 bcm53xx_srab_write_4(port, 0x00); 655 } 656 bcm53xx_srab_write_4(0x0008, 0x1c); // IMP port (enab UC/MC/BC) 657 bcm53xx_srab_write_4(0x000e, 0xbb); // IMP port force-link 1G 658 bcm53xx_srab_write_4(0x005d, 0x7b); // port5 force-link 1G 659 bcm53xx_srab_write_4(0x005f, 0x7b); // port7 force-link 1G 660 bcm53xx_srab_write_4(0x000b, 0x7); // management mode 661 bcm53xx_srab_write_4(0x0203, 0x0); // disable BRCM tag 662 bcm53xx_srab_write_4(0x0200, 0x80); // enable IMP=port8 663 } 664 665 static inline void 666 bcm53xx_srab_busywait(bus_space_tag_t bst, bus_space_handle_t bsh) 667 { 668 while (bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT) & SRA_GORDYN) { 669 delay(10); 670 } 671 } 672 673 uint32_t 674 bcm53xx_srab_read_4(u_int pageoffset) 675 { 676 bus_space_tag_t bst = bcm53xx_ioreg_bst; 677 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 678 uint32_t rv; 679 680 mutex_spin_enter(&srab_lock); 681 682 bcm53xx_srab_busywait(bst, bsh); 683 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT, 684 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_GORDYN); 685 bcm53xx_srab_busywait(bst, bsh); 686 rv = bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_RDL); 687 688 mutex_spin_exit(&srab_lock); 689 return rv; 690 } 691 692 uint64_t 693 bcm53xx_srab_read_8(u_int pageoffset) 694 { 695 bus_space_tag_t bst = bcm53xx_ioreg_bst; 696 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 697 uint64_t rv; 698 699 mutex_spin_enter(&srab_lock); 700 701 bcm53xx_srab_busywait(bst, bsh); 702 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT, 703 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_GORDYN); 704 bcm53xx_srab_busywait(bst, bsh); 705 rv = bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_RDH); 706 rv <<= 32; 707 rv |= bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_RDL); 708 709 mutex_spin_exit(&srab_lock); 710 return rv; 711 } 712 713 void 714 bcm53xx_srab_write_4(u_int pageoffset, uint32_t val) 715 { 716 bus_space_tag_t bst = bcm53xx_ioreg_bst; 717 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 718 719 mutex_spin_enter(&srab_lock); 720 721 bcm53xx_srab_busywait(bst, bsh); 722 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_WDL, val); 723 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT, 724 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_WRITE | SRA_GORDYN); 725 bcm53xx_srab_busywait(bst, bsh); 726 727 mutex_spin_exit(&srab_lock); 728 } 729 730 void 731 bcm53xx_srab_write_8(u_int pageoffset, uint64_t val) 732 { 733 bus_space_tag_t bst = bcm53xx_ioreg_bst; 734 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 735 736 mutex_spin_enter(&srab_lock); 737 738 bcm53xx_srab_busywait(bst, bsh); 739 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_WDL, val); 740 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_WDH, val >> 32); 741 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT, 742 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_WRITE | SRA_GORDYN); 743 bcm53xx_srab_busywait(bst, bsh); 744 mutex_spin_exit(&srab_lock); 745 } 746 #endif 747