1 /* $NetBSD: bcm53xx_board.c,v 1.17 2013/10/28 22:51:16 matt Exp $ */ 2 /*- 3 * Copyright (c) 2012 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas of 3am Software Foundry. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "opt_broadcom.h" 32 33 #define _ARM32_BUS_DMA_PRIVATE 34 35 #include <sys/cdefs.h> 36 37 __KERNEL_RCSID(1, "$NetBSD: bcm53xx_board.c,v 1.17 2013/10/28 22:51:16 matt Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/bus.h> 41 #include <sys/cpu.h> 42 #include <sys/device.h> 43 44 #include <prop/proplib.h> 45 46 #include <net/if.h> 47 #include <net/if_ether.h> 48 49 #define CCA_PRIVATE 50 #define CRU_PRIVATE 51 #define DDR_PRIVATE 52 #define DMU_PRIVATE 53 #define ARMCORE_PRIVATE 54 #define SRAB_PRIVATE 55 56 #include <arm/cortex/a9tmr_var.h> 57 #include <arm/cortex/pl310_var.h> 58 #include <arm/mainbus/mainbus.h> 59 60 #include <arm/broadcom/bcm53xx_reg.h> 61 #include <arm/broadcom/bcm53xx_var.h> 62 63 bus_space_tag_t bcm53xx_ioreg_bst = &bcmgen_bs_tag; 64 bus_space_handle_t bcm53xx_ioreg_bsh; 65 bus_space_tag_t bcm53xx_armcore_bst = &bcmgen_bs_tag; 66 bus_space_handle_t bcm53xx_armcore_bsh; 67 68 static struct cpu_softc cpu_softc; 69 70 struct arm32_dma_range bcm53xx_dma_ranges[] = { 71 #ifdef BCM5301X 72 [0] = { 73 .dr_sysbase = 0x80000000, 74 .dr_busbase = 0x80000000, 75 .dr_len = 0x10000000, 76 }, [1] = { 77 .dr_sysbase = 0x90000000, 78 .dr_busbase = 0x90000000, 79 }, 80 #elif defined(BCM56340) 81 [0] = { 82 .dr_sysbase = 0x60000000, 83 .dr_busbase = 0x60000000, 84 .dr_len = 0x20000000, 85 }, [1] = { 86 .dr_sysbase = 0xa0000000, 87 .dr_busbase = 0xa0000000, 88 }. 89 #endif 90 }; 91 92 struct arm32_bus_dma_tag bcm53xx_dma_tag = { 93 ._ranges = bcm53xx_dma_ranges, 94 ._nranges = __arraycount(bcm53xx_dma_ranges), 95 _BUS_DMAMAP_FUNCS, 96 _BUS_DMAMEM_FUNCS, 97 _BUS_DMATAG_FUNCS, 98 }; 99 100 struct arm32_dma_range bcm53xx_coherent_dma_ranges[] = { 101 #ifdef BCM5301X 102 [0] = { 103 .dr_sysbase = 0x80000000, 104 .dr_busbase = 0x80000000, 105 .dr_len = 0x10000000, 106 .dr_flags = _BUS_DMAMAP_COHERENT, 107 }, [1] = { 108 .dr_sysbase = 0x90000000, 109 .dr_busbase = 0x90000000, 110 }, 111 #elif defined(BCM563XX) 112 [0] = { 113 .dr_sysbase = 0x60000000, 114 .dr_busbase = 0x60000000, 115 .dr_len = 0x20000000, 116 .dr_flags = _BUS_DMAMAP_COHERENT, 117 }, [1] = { 118 .dr_sysbase = 0xa0000000, 119 .dr_busbase = 0xa0000000, 120 }, 121 #endif 122 }; 123 124 struct arm32_bus_dma_tag bcm53xx_coherent_dma_tag = { 125 ._ranges = bcm53xx_coherent_dma_ranges, 126 ._nranges = __arraycount(bcm53xx_coherent_dma_ranges), 127 _BUS_DMAMAP_FUNCS, 128 _BUS_DMAMEM_FUNCS, 129 _BUS_DMATAG_FUNCS, 130 }; 131 132 #ifdef _ARM32_NEED_BUS_DMA_BOUNCE 133 struct arm32_bus_dma_tag bcm53xx_bounce_dma_tag = { 134 ._ranges = bcm53xx_coherent_dma_ranges, 135 ._nranges = 1, 136 _BUS_DMAMAP_FUNCS, 137 _BUS_DMAMEM_FUNCS, 138 _BUS_DMATAG_FUNCS, 139 }; 140 #endif 141 142 #ifdef BCM53XX_CONSOLE_EARLY 143 #include <dev/ic/ns16550reg.h> 144 #include <dev/ic/comreg.h> 145 #include <dev/cons.h> 146 147 static vaddr_t com_base; 148 149 static inline uint32_t 150 uart_read(bus_size_t o) 151 { 152 return *(volatile uint8_t *)(com_base + o); 153 } 154 155 static inline void 156 uart_write(bus_size_t o, uint32_t v) 157 { 158 *(volatile uint8_t *)(com_base + o) = v; 159 } 160 161 static int 162 bcm53xx_cngetc(dev_t dv) 163 { 164 if ((uart_read(com_lsr) & LSR_RXRDY) == 0) 165 return -1; 166 167 return uart_read(com_data) & 0xff; 168 } 169 170 static void 171 bcm53xx_cnputc(dev_t dv, int c) 172 { 173 int timo = 150000; 174 175 while ((uart_read(com_lsr) & LSR_TXRDY) == 0 && --timo > 0) 176 ; 177 178 uart_write(com_data, c); 179 180 timo = 150000; 181 while ((uart_read(com_lsr) & LSR_TSRE) == 0 && --timo > 0) 182 ; 183 } 184 185 static struct consdev bcm53xx_earlycons = { 186 .cn_putc = bcm53xx_cnputc, 187 .cn_getc = bcm53xx_cngetc, 188 .cn_pollc = nullcnpollc, 189 }; 190 #endif /* BCM53XX_CONSOLE_EARLY */ 191 192 psize_t 193 bcm53xx_memprobe(void) 194 { 195 bus_space_tag_t bst = bcm53xx_ioreg_bst; 196 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 197 198 /* 199 * First, let's read the magic DDR registers! 200 */ 201 const uint32_t v01 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_01); 202 const uint32_t v82 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_82); 203 const uint32_t v86 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_86); 204 const uint32_t v87 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_87); 205 206 /* 207 * Calculate chip parameters 208 * */ 209 const u_int rows = __SHIFTOUT(v01, CTL_01_MAX_ROW) 210 - __SHIFTOUT(v82, CTL_82_ROW_DIFF); 211 const u_int cols = __SHIFTOUT(v01, CTL_01_MAX_COL) 212 - __SHIFTOUT(v82, CTL_82_COL_DIFF); 213 const u_int banks_log2 = 3 - __SHIFTOUT(v82, CTL_82_BANK_DIFF); 214 215 /* 216 * For each chip select, increase the chip count if if is enabled. 217 */ 218 const u_int max_chips = __SHIFTOUT(v01, CTL_01_MAX_CHIP_SEL); 219 u_int cs_map = __SHIFTOUT(v86, CTL_86_CS_MAP); 220 u_int chips = 0; 221 222 for (u_int i = 0; cs_map != 0 && i < max_chips; i++, cs_map >>= 1) { 223 chips += (cs_map & 1); 224 } 225 226 /* get log2(ddr width) */ 227 228 const u_int ddr_width_log2 = (v87 & CTL_87_REDUC) ? 1 : 2; 229 230 /* 231 * Let's add up all the things that contribute to the size of a chip. 232 */ 233 const u_int chip_size_log2 = cols + rows + banks_log2 + ddr_width_log2; 234 235 /* 236 * Now our memory size is simply the number of chip shifted by the 237 * log2(chip_size). 238 */ 239 return (psize_t) chips << chip_size_log2; 240 } 241 242 static inline uint32_t 243 bcm53xx_freq_calc(struct bcm53xx_clock_info *clk, 244 uint32_t pdiv, uint32_t ndiv_int, uint32_t ndiv_frac) 245 { 246 if (ndiv_frac == 0 && pdiv == 1) 247 return ndiv_int * clk->clk_ref; 248 249 uint64_t freq64 = ((uint64_t)ndiv_int << 30) + ndiv_frac; 250 freq64 *= clk->clk_ref; 251 if (pdiv > 1) 252 freq64 /= pdiv; 253 return (uint32_t) (freq64 >> 30); 254 } 255 256 static uint32_t 257 bcm53xx_value_wrap(uint32_t value, uint32_t mask) 258 { 259 /* 260 * n is n except when n is 0 then n = mask + 1. 261 */ 262 return ((__SHIFTOUT(value, mask) - 1) & __SHIFTOUT(mask, mask)) + 1; 263 } 264 265 static void 266 bcm53xx_genpll_clock_init(struct bcm53xx_clock_info *clk, uint32_t control5, 267 uint32_t control6, uint32_t control7) 268 { 269 const uint32_t pdiv = bcm53xx_value_wrap(control6, 270 GENPLL_CONTROL6_PDIV); 271 const uint32_t ndiv_int = bcm53xx_value_wrap(control5, 272 GENPLL_CONTROL5_NDIV_INT); 273 const uint32_t ndiv_frac = __SHIFTOUT(control5, 274 GENPLL_CONTROL5_NDIV_FRAC); 275 276 clk->clk_genpll = bcm53xx_freq_calc(clk, pdiv, ndiv_int, ndiv_frac); 277 278 const uint32_t ch0_mdiv = bcm53xx_value_wrap(control6, 279 GENPLL_CONTROL6_CH0_MDIV); 280 const uint32_t ch1_mdiv = bcm53xx_value_wrap(control6, 281 GENPLL_CONTROL6_CH1_MDIV); 282 const uint32_t ch2_mdiv = bcm53xx_value_wrap(control6, 283 GENPLL_CONTROL6_CH2_MDIV); 284 const uint32_t ch3_mdiv = bcm53xx_value_wrap(control7, 285 GENPLL_CONTROL7_CH3_MDIV); 286 287 clk->clk_mac = clk->clk_genpll / ch0_mdiv; // GENPLL CH0 288 clk->clk_robo = clk->clk_genpll / ch1_mdiv; // GENPLL CH1 289 clk->clk_usb2 = clk->clk_genpll / ch2_mdiv; // GENPLL CH2 290 clk->clk_iproc = clk->clk_genpll / ch3_mdiv; // GENPLL CH3 291 } 292 293 static void 294 bcm53xx_lcpll_clock_init(struct bcm53xx_clock_info *clk, uint32_t control1, 295 uint32_t control2) 296 { 297 const uint32_t pdiv = bcm53xx_value_wrap(control1, 298 LCPLL_CONTROL1_PDIV); 299 const uint32_t ndiv_int = bcm53xx_value_wrap(control1, 300 LCPLL_CONTROL1_NDIV_INT); 301 const uint32_t ndiv_frac = __SHIFTOUT(control1, 302 LCPLL_CONTROL1_NDIV_FRAC); 303 304 clk->clk_lcpll = bcm53xx_freq_calc(clk, pdiv, ndiv_int, ndiv_frac); 305 306 const uint32_t ch0_mdiv = bcm53xx_value_wrap(control2, 307 LCPLL_CONTROL2_CH0_MDIV); 308 const uint32_t ch1_mdiv = bcm53xx_value_wrap(control2, 309 LCPLL_CONTROL2_CH1_MDIV); 310 const uint32_t ch2_mdiv = bcm53xx_value_wrap(control2, 311 LCPLL_CONTROL2_CH2_MDIV); 312 const uint32_t ch3_mdiv = bcm53xx_value_wrap(control2, 313 LCPLL_CONTROL2_CH3_MDIV); 314 315 clk->clk_pcie_ref = clk->clk_lcpll / ch0_mdiv; // LCPLL CH0 316 clk->clk_sdio = clk->clk_lcpll / ch1_mdiv; // LCPLL CH1 317 clk->clk_ddr_ref = clk->clk_lcpll / ch2_mdiv; // LCPLL CH2 318 clk->clk_axi = clk->clk_lcpll / ch3_mdiv; // LCPLL CH3 319 } 320 321 static void 322 bcm53xx_usb_clock_init(struct bcm53xx_clock_info *clk, uint32_t usb2_control) 323 { 324 const uint32_t pdiv = bcm53xx_value_wrap(usb2_control, 325 USB2_CONTROL_PDIV); 326 const uint32_t ndiv = bcm53xx_value_wrap(usb2_control, 327 USB2_CONTROL_NDIV_INT); 328 329 uint32_t usb_ref = (clk->clk_usb2 / pdiv) * ndiv; 330 if (usb_ref != USB2_REF_CLK) { 331 /* 332 * USB Reference Clock isn't 1.92GHz. So we need to modify 333 * USB2_CONTROL to produce it. 334 */ 335 uint32_t new_ndiv = (USB2_REF_CLK / clk->clk_usb2) * pdiv; 336 usb2_control &= ~USB2_CONTROL_NDIV_INT; 337 usb2_control |= __SHIFTIN(new_ndiv, USB2_CONTROL_NDIV_INT); 338 339 // Allow Clocks to be modified 340 bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh, 341 CRU_BASE + CRU_CLKSET_KEY, CRU_CLKSET_KEY_MAGIC); 342 343 // Update USB2 clock generator 344 bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh, 345 CRU_BASE + CRU_USB2_CONTROL, usb2_control); 346 347 // Prevent Clock modification 348 bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh, 349 CRU_BASE + CRU_CLKSET_KEY, 0); 350 351 usb_ref = (clk->clk_usb2 / pdiv) * new_ndiv; 352 } 353 354 clk->clk_usb_ref = usb_ref; 355 } 356 357 358 static void 359 bcm53xx_clock_init(struct bcm53xx_clock_info *clk) 360 { 361 clk->clk_ref = BCM53XX_REF_CLK; 362 clk->clk_sys = 8*clk->clk_ref; 363 } 364 365 /* 366 * F(ddr) = ((1 / pdiv) * ndiv * CH2) / (post_div * 2) 367 */ 368 static void 369 bcm53xx_get_ddr_freq(struct bcm53xx_clock_info *clk, uint32_t pll_status, 370 uint32_t pll_dividers) 371 { 372 const bool clocking_4x = (pll_status & PLL_STATUS_CLOCKING_4X) != 0; 373 u_int post_div = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_POST_DIV); 374 u_int pdiv = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_PDIV); 375 u_int ndiv = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_NDIV); 376 377 pdiv = ((pdiv - (clocking_4x ? 1 : 5)) & 7) + 1; 378 379 clk->clk_ddr_mhz = __SHIFTOUT(pll_status, PLL_STATUS_MHZ); 380 clk->clk_ddr = (clk->clk_ddr_ref / pdiv) * ndiv / (2 + post_div); 381 } 382 383 /* 384 * CPU_CLK = (1 / pdiv) * (ndiv_int + (ndiv_frac / 0x40000000)) x F(ref) 385 */ 386 static void 387 bcm53xx_get_cpu_freq(struct bcm53xx_clock_info *clk, 388 uint32_t pllarma, uint32_t pllarmb, uint32_t policy) 389 { 390 policy = __SHIFTOUT(policy, CLK_POLICY_FREQ_POLICY2); 391 392 if (policy == CLK_POLICY_REF_CLK) { 393 clk->clk_cpu = clk->clk_ref; 394 clk->clk_apb = clk->clk_cpu; 395 return; 396 } 397 398 if (policy == CLK_POLICY_SYS_CLK) { 399 clk->clk_cpu = clk->clk_sys; 400 clk->clk_apb = clk->clk_cpu / 4; 401 return; 402 } 403 404 const u_int pdiv = bcm53xx_value_wrap(pllarma, CLK_PLLARMA_PDIV); 405 const u_int ndiv_int = bcm53xx_value_wrap(pllarma, CLK_PLLARMA_NDIV_INT); 406 const u_int ndiv_frac = __SHIFTOUT(pllarmb, CLK_PLLARMB_NDIV_FRAC); 407 // const u_int apb_clk_div = __SHIFTOUT(apb_clk_div, CLK_APB_DIV_VALUE)+1; 408 409 const u_int cpu_div = (policy == CLK_POLICY_ARM_PLL_CH0) ? 4 : 2; 410 411 clk->clk_cpu = bcm53xx_freq_calc(clk, pdiv, ndiv_int, ndiv_frac) / cpu_div; 412 clk->clk_apb = clk->clk_cpu / 4; 413 } 414 415 struct bcm53xx_chip_state { 416 uint32_t bcs_lcpll_control1; 417 uint32_t bcs_lcpll_control2; 418 419 uint32_t bcs_genpll_control5; 420 uint32_t bcs_genpll_control6; 421 uint32_t bcs_genpll_control7; 422 423 uint32_t bcs_usb2_control; 424 425 uint32_t bcs_ddr_phy_ctl_pll_status; 426 uint32_t bcs_ddr_phy_ctl_pll_dividers; 427 428 uint32_t bcs_armcore_clk_policy; 429 uint32_t bcs_armcore_clk_pllarma; 430 uint32_t bcs_armcore_clk_pllarmb; 431 }; 432 433 static void 434 bcm53xx_get_chip_ioreg_state(struct bcm53xx_chip_state *bcs, 435 bus_space_tag_t bst, bus_space_handle_t bsh) 436 { 437 bcs->bcs_lcpll_control1 = bus_space_read_4(bst, bsh, 438 DMU_BASE + DMU_LCPLL_CONTROL1); 439 bcs->bcs_lcpll_control2 = bus_space_read_4(bst, bsh, 440 DMU_BASE + DMU_LCPLL_CONTROL2); 441 442 bcs->bcs_genpll_control5 = bus_space_read_4(bst, bsh, 443 CRU_BASE + CRU_GENPLL_CONTROL5); 444 bcs->bcs_genpll_control6 = bus_space_read_4(bst, bsh, 445 CRU_BASE + CRU_GENPLL_CONTROL6); 446 bcs->bcs_genpll_control7 = bus_space_read_4(bst, bsh, 447 CRU_BASE + CRU_GENPLL_CONTROL7); 448 449 bcs->bcs_usb2_control = bus_space_read_4(bst, bsh, 450 CRU_BASE + CRU_USB2_CONTROL); 451 452 bcs->bcs_ddr_phy_ctl_pll_status = bus_space_read_4(bst, bsh, 453 DDR_BASE + DDR_PHY_CTL_PLL_STATUS); 454 bcs->bcs_ddr_phy_ctl_pll_dividers = bus_space_read_4(bst, bsh, 455 DDR_BASE + DDR_PHY_CTL_PLL_DIVIDERS); 456 } 457 458 static void 459 bcm53xx_get_chip_armcore_state(struct bcm53xx_chip_state *bcs, 460 bus_space_tag_t bst, bus_space_handle_t bsh) 461 { 462 bcs->bcs_armcore_clk_policy = bus_space_read_4(bst, bsh, 463 ARMCORE_CLK_POLICY_FREQ); 464 bcs->bcs_armcore_clk_pllarma = bus_space_read_4(bst, bsh, 465 ARMCORE_CLK_PLLARMA); 466 bcs->bcs_armcore_clk_pllarmb = bus_space_read_4(bst, bsh, 467 ARMCORE_CLK_PLLARMB); 468 } 469 470 void 471 bcm53xx_cpu_softc_init(struct cpu_info *ci) 472 { 473 struct cpu_softc * const cpu = ci->ci_softc; 474 475 cpu->cpu_ioreg_bst = bcm53xx_ioreg_bst; 476 cpu->cpu_ioreg_bsh = bcm53xx_ioreg_bsh; 477 478 cpu->cpu_armcore_bst = bcm53xx_armcore_bst; 479 cpu->cpu_armcore_bsh = bcm53xx_armcore_bsh; 480 481 const uint32_t chipid = bus_space_read_4(cpu->cpu_ioreg_bst, 482 cpu->cpu_ioreg_bsh, CCA_MISC_BASE + MISC_CHIPID); 483 484 cpu->cpu_chipid = __SHIFTOUT(chipid, CHIPID_ID); 485 } 486 487 void 488 bcm53xx_print_clocks(void) 489 { 490 #if defined(VERBOSE_INIT_ARM) 491 const struct bcm53xx_clock_info * const clk = &cpu_softc.cpu_clk; 492 printf("ref clk = %u (%#x)\n", clk->clk_ref, clk->clk_ref); 493 printf("sys clk = %u (%#x)\n", clk->clk_sys, clk->clk_sys); 494 printf("lcpll clk = %u (%#x)\n", clk->clk_lcpll, clk->clk_lcpll); 495 printf("pcie ref clk = %u (%#x) [CH0]\n", clk->clk_pcie_ref, clk->clk_pcie_ref); 496 printf("sdio clk = %u (%#x) [CH1]\n", clk->clk_sdio, clk->clk_sdio); 497 printf("ddr ref clk = %u (%#x) [CH2]\n", clk->clk_ddr_ref, clk->clk_ddr_ref); 498 printf("axi clk = %u (%#x) [CH3]\n", clk->clk_axi, clk->clk_axi); 499 printf("genpll clk = %u (%#x)\n", clk->clk_genpll, clk->clk_genpll); 500 printf("mac clk = %u (%#x) [CH0]\n", clk->clk_mac, clk->clk_mac); 501 printf("robo clk = %u (%#x) [CH1]\n", clk->clk_robo, clk->clk_robo); 502 printf("usb2 clk = %u (%#x) [CH2]\n", clk->clk_usb2, clk->clk_usb2); 503 printf("iproc clk = %u (%#x) [CH3]\n", clk->clk_iproc, clk->clk_iproc); 504 printf("ddr clk = %u (%#x)\n", clk->clk_ddr, clk->clk_ddr); 505 printf("ddr mhz = %u (%#x)\n", clk->clk_ddr_mhz, clk->clk_ddr_mhz); 506 printf("cpu clk = %u (%#x)\n", clk->clk_cpu, clk->clk_cpu); 507 printf("apb clk = %u (%#x)\n", clk->clk_apb, clk->clk_apb); 508 printf("usb ref clk = %u (%#x)\n", clk->clk_usb_ref, clk->clk_usb_ref); 509 #endif 510 } 511 512 void 513 bcm53xx_bootstrap(vaddr_t iobase) 514 { 515 struct bcm53xx_chip_state bcs; 516 int error; 517 518 #ifdef BCM53XX_CONSOLE_EARLY 519 com_base = iobase + CCA_UART0_BASE; 520 cn_tab = &bcm53xx_earlycons; 521 #endif 522 523 bcm53xx_ioreg_bsh = (bus_space_handle_t) iobase; 524 error = bus_space_map(bcm53xx_ioreg_bst, BCM53XX_IOREG_PBASE, 525 BCM53XX_IOREG_SIZE, 0, &bcm53xx_ioreg_bsh); 526 if (error) 527 panic("%s: failed to map BCM53xx %s registers: %d", 528 __func__, "io", error); 529 530 bcm53xx_armcore_bsh = (bus_space_handle_t) iobase + BCM53XX_IOREG_SIZE; 531 error = bus_space_map(bcm53xx_armcore_bst, BCM53XX_ARMCORE_PBASE, 532 BCM53XX_ARMCORE_SIZE, 0, &bcm53xx_armcore_bsh); 533 if (error) 534 panic("%s: failed to map BCM53xx %s registers: %d", 535 __func__, "armcore", error); 536 537 curcpu()->ci_softc = &cpu_softc; 538 539 bcm53xx_get_chip_ioreg_state(&bcs, bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh); 540 bcm53xx_get_chip_armcore_state(&bcs, bcm53xx_armcore_bst, bcm53xx_armcore_bsh); 541 542 struct bcm53xx_clock_info * const clk = &cpu_softc.cpu_clk; 543 544 bcm53xx_clock_init(clk); 545 bcm53xx_lcpll_clock_init(clk, bcs.bcs_lcpll_control1, 546 bcs.bcs_lcpll_control2); 547 bcm53xx_genpll_clock_init(clk, bcs.bcs_genpll_control5, 548 bcs.bcs_genpll_control6, bcs.bcs_genpll_control7); 549 bcm53xx_usb_clock_init(clk, bcs.bcs_usb2_control); 550 bcm53xx_get_ddr_freq(clk, bcs.bcs_ddr_phy_ctl_pll_status, 551 bcs.bcs_ddr_phy_ctl_pll_dividers); 552 bcm53xx_get_cpu_freq(clk, bcs.bcs_armcore_clk_pllarma, 553 bcs.bcs_armcore_clk_pllarmb, bcs.bcs_armcore_clk_policy); 554 555 curcpu()->ci_data.cpu_cc_freq = clk->clk_cpu; 556 557 arml2cc_init(bcm53xx_armcore_bst, bcm53xx_armcore_bsh, 558 ARMCORE_L2C_BASE); 559 } 560 561 void 562 bcm53xx_dma_bootstrap(psize_t memsize) 563 { 564 if (memsize <= 256*1024*1024) { 565 bcm53xx_dma_ranges[0].dr_len = memsize; 566 bcm53xx_coherent_dma_ranges[0].dr_len = memsize; 567 bcm53xx_dma_tag._nranges = 1; 568 bcm53xx_coherent_dma_tag._nranges = 1; 569 } else { 570 /* 571 * By setting up two ranges, bus_dmamem_alloc will always 572 * try to allocate from range 0 first resulting in allocations 573 * below 256MB which for PCI and GMAC are coherent. 574 */ 575 bcm53xx_dma_ranges[1].dr_len = memsize - 0x10000000; 576 bcm53xx_coherent_dma_ranges[1].dr_len = memsize - 0x10000000; 577 } 578 KASSERT(bcm53xx_dma_tag._ranges[0].dr_flags == 0); 579 KASSERT(bcm53xx_coherent_dma_tag._ranges[0].dr_flags == _BUS_DMAMAP_COHERENT); 580 #ifdef _ARM32_NEED_BUS_DMA_BOUNCE 581 KASSERT(bcm53xx_bounce_dma_tag._ranges[0].dr_flags == _BUS_DMAMAP_COHERENT); 582 #endif 583 } 584 585 #ifdef MULTIPROCESSOR 586 void 587 bcm53xx_cpu_hatch(struct cpu_info *ci) 588 { 589 a9tmr_init_cpu_clock(ci); 590 } 591 #endif 592 593 void 594 bcm53xx_device_register(device_t self, void *aux) 595 { 596 prop_dictionary_t dict = device_properties(self); 597 598 if (device_is_a(self, "armperiph") 599 && device_is_a(device_parent(self), "mainbus")) { 600 /* 601 * XXX KLUDGE ALERT XXX 602 * The iot mainbus supplies is completely wrong since it scales 603 * addresses by 2. The simpliest remedy is to replace with our 604 * bus space used for the armcore regisers (which armperiph uses). 605 */ 606 struct mainbus_attach_args * const mb = aux; 607 mb->mb_iot = bcm53xx_armcore_bst; 608 return; 609 } 610 611 /* 612 * We need to tell the A9 Global/Watchdog Timer 613 * what frequency it runs at. 614 */ 615 if (device_is_a(self, "a9tmr") || device_is_a(self, "a9wdt")) { 616 /* 617 * This clock always runs at (arm_clk div 2) and only goes 618 * to timers that are part of the A9 MP core subsystem. 619 */ 620 prop_dictionary_set_uint32(dict, "frequency", 621 cpu_softc.cpu_clk.clk_cpu / 2); 622 return; 623 } 624 625 if (device_is_a(self, "bcmeth")) { 626 const struct bcmccb_attach_args * const ccbaa = aux; 627 const uint8_t enaddr[ETHER_ADDR_LEN] = { 628 0x00, 0x01, 0x02, 0x03, 0x04, 629 0x05 + 2 * ccbaa->ccbaa_loc.loc_port, 630 }; 631 prop_data_t pd = prop_data_create_data(enaddr, ETHER_ADDR_LEN); 632 KASSERT(pd != NULL); 633 if (prop_dictionary_set(device_properties(self), "mac-address", pd) == false) { 634 printf("WARNING: Unable to set mac-address property for %s\n", device_xname(self)); 635 } 636 prop_object_release(pd); 637 } 638 } 639 640 static kmutex_t srab_lock __cacheline_aligned; 641 642 void 643 bcm53xx_srab_init(void) 644 { 645 mutex_init(&srab_lock, MUTEX_DEFAULT, IPL_VM); 646 647 bcm53xx_srab_write_4(0x0079, 0x90); // reset switch 648 for (u_int port = 0; port < 8; port++) { 649 /* per port control: no stp */ 650 bcm53xx_srab_write_4(port, 0x00); 651 } 652 bcm53xx_srab_write_4(0x0008, 0x1c); // IMP port (enab UC/MC/BC) 653 bcm53xx_srab_write_4(0x000e, 0xbb); // IMP port force-link 1G 654 bcm53xx_srab_write_4(0x005d, 0x7b); // port5 force-link 1G 655 bcm53xx_srab_write_4(0x005f, 0x7b); // port7 force-link 1G 656 bcm53xx_srab_write_4(0x000b, 0x7); // management mode 657 bcm53xx_srab_write_4(0x0203, 0x0); // disable BRCM tag 658 bcm53xx_srab_write_4(0x0200, 0x80); // enable IMP=port8 659 } 660 661 static inline void 662 bcm53xx_srab_busywait(bus_space_tag_t bst, bus_space_handle_t bsh) 663 { 664 while (bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT) & SRA_GORDYN) { 665 delay(10); 666 } 667 } 668 669 uint32_t 670 bcm53xx_srab_read_4(u_int pageoffset) 671 { 672 bus_space_tag_t bst = bcm53xx_ioreg_bst; 673 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 674 uint32_t rv; 675 676 mutex_spin_enter(&srab_lock); 677 678 bcm53xx_srab_busywait(bst, bsh); 679 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT, 680 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_GORDYN); 681 bcm53xx_srab_busywait(bst, bsh); 682 rv = bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_RDL); 683 684 mutex_spin_exit(&srab_lock); 685 return rv; 686 } 687 688 uint64_t 689 bcm53xx_srab_read_8(u_int pageoffset) 690 { 691 bus_space_tag_t bst = bcm53xx_ioreg_bst; 692 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 693 uint64_t rv; 694 695 mutex_spin_enter(&srab_lock); 696 697 bcm53xx_srab_busywait(bst, bsh); 698 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT, 699 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_GORDYN); 700 bcm53xx_srab_busywait(bst, bsh); 701 rv = bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_RDH); 702 rv <<= 32; 703 rv |= bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_RDL); 704 705 mutex_spin_exit(&srab_lock); 706 return rv; 707 } 708 709 void 710 bcm53xx_srab_write_4(u_int pageoffset, uint32_t val) 711 { 712 bus_space_tag_t bst = bcm53xx_ioreg_bst; 713 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 714 715 mutex_spin_enter(&srab_lock); 716 717 bcm53xx_srab_busywait(bst, bsh); 718 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_WDL, val); 719 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT, 720 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_WRITE | SRA_GORDYN); 721 bcm53xx_srab_busywait(bst, bsh); 722 723 mutex_spin_exit(&srab_lock); 724 } 725 726 void 727 bcm53xx_srab_write_8(u_int pageoffset, uint64_t val) 728 { 729 bus_space_tag_t bst = bcm53xx_ioreg_bst; 730 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 731 732 mutex_spin_enter(&srab_lock); 733 734 bcm53xx_srab_busywait(bst, bsh); 735 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_WDL, val); 736 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_WDH, val >> 32); 737 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT, 738 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_WRITE | SRA_GORDYN); 739 bcm53xx_srab_busywait(bst, bsh); 740 mutex_spin_exit(&srab_lock); 741 } 742