1 /* $NetBSD: bcm2835reg.h,v 1.10 2013/01/26 11:58:43 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Nick Hudson 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Reference: BCM2835 ARM Periperhals 34 * 35 * http://dmkenr5gtnd8f.cloudfront.net/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf 36 */ 37 38 #ifndef _BCM2835REG_H_ 39 #define _BCM2835REG_H_ 40 41 #define BCM2835_PERIPHERALS_BASE 0x20000000 42 #define BCM2835_PERIPHERALS_SIZE 0x01000000 /* 16MBytes */ 43 44 #define BCM2835_STIMER_BASE (BCM2835_PERIPHERALS_BASE + 0x00003000) 45 #define BCM2835_DMA0_BASE (BCM2835_PERIPHERALS_BASE + 0x00007000) 46 #define BCM2835_ARM_BASE (BCM2835_PERIPHERALS_BASE + 0x0000B000) 47 #define BCM2835_PM_BASE (BCM2835_PERIPHERALS_BASE + 0x00100000) 48 #define BCM2835_RNG_BASE (BCM2835_PERIPHERALS_BASE + 0x00104000) 49 #define BCM2835_GPIO_BASE (BCM2835_PERIPHERALS_BASE + 0x00200000) 50 #define BCM2835_UART0_BASE (BCM2835_PERIPHERALS_BASE + 0x00201000) 51 #define BCM2835_PCM_BASE (BCM2835_PERIPHERALS_BASE + 0x00203000) 52 #define BCM2835_SPI0_BASE (BCM2835_PERIPHERALS_BASE + 0x00204000) 53 #define BCM2835_BSC0_BASE (BCM2835_PERIPHERALS_BASE + 0x00205000) 54 #define BCM2835_BSCSPISLV_BASE (BCM2835_PERIPHERALS_BASE + 0x00214000) 55 #define BCM2835_AUX_BASE (BCM2835_PERIPHERALS_BASE + 0x00215000) 56 #define BCM2835_EMMC_BASE (BCM2835_PERIPHERALS_BASE + 0x00300000) 57 #define BCM2835_BSC1_BASE (BCM2835_PERIPHERALS_BASE + 0x00804000) 58 #define BCM2835_BSC2_BASE (BCM2835_PERIPHERALS_BASE + 0x00805000) 59 #define BCM2835_USB_BASE (BCM2835_PERIPHERALS_BASE + 0x00980000) 60 #define BCM2835_DMA15_BASE (BCM2835_PERIPHERALS_BASE + 0x00E05000) 61 62 #define BCM2835_STIMER_SIZE 0x1c 63 #define BCM2835_DMA0_SIZE 0x1000 64 #define BCM2835_ARM_SIZE 0x1000 65 #define BCM2835_PM_SIZE 0x1000 66 #define BCM2835_RNG_SIZE 0x1000 67 #define BCM2835_GPIO_SIZE 0x1000 68 #define BCM2835_UART0_SIZE 0x90 69 #define BCM2835_PCM_SIZE 0x1000 70 #define BCM2835_SPI0_SIZE 0x1000 71 #define BCM2835_BSC_SIZE 0x1000 72 #define BCM2835_AUX_SIZE 0x1000 73 #define BCM2835_EMMC_SIZE 0x1000 74 #define BCM2835_USB_SIZE 0x20000 75 #define BCM2835_DMA15_SIZE 0x100 76 77 #define BCM2835_IOPHYSTOVIRT(a) \ 78 ((0xf0000000 | (((a) & 0xf0000000) >> 4)) + ((a) & ~0xf0000000)) 79 80 #define BCM2835_BUSADDR_CACHE_MASK 0xc0000000 81 #define BCM2835_BUSADDR_CACHE_COHERENT 0x40000000 82 #define BCM2835_BUSADDR_CACHE_L1L2 0x00000000 83 #define BCM2835_BUSADDR_CACHE_L2ONLY 0x80000000 84 #define BCM2835_BUSADDR_CACHE_DIRECT 0xc0000000 85 86 #define BCM2835_PERIPHERALS_VBASE \ 87 BCM2835_IOPHYSTOVIRT(BCM2835_PERIPHERALS_BASE) 88 #define BCM2835_STIMER_VBASE BCM2835_IOPHYSTOVIRT(BCM2835_ST_BASE) 89 #define BCM2835_PM_VBASE BCM2835_IOPHYSTOVIRT(BCM2835_PM_BASE) 90 #define BCM2835_UART0_VBASE BCM2835_IOPHYSTOVIRT(BCM2835_UART0_BASE) 91 #define BCM2835_EMMC_VBASE BCM2835_IOPHYSTOVIRT(BCM2835_EMMC_BASE) 92 93 #define BCM2835_ARMICU_BASE (BCM2835_ARM_BASE + 0x0200) 94 #define BCM2835_ARMICU_SIZE 0x200 95 96 #define BCM2835_VCHIQ_BASE (BCM2835_ARM_BASE + 0x0800) 97 #define BCM2835_VCHIQ_SIZE 0x50 98 99 #define BCM2835_ARMMBOX_BASE (BCM2835_ARM_BASE + 0x0880) 100 #define BCM2835_ARMMBOX_SIZE 0x40 101 102 #define BCM2835_ARMICU_VBASE BCM2835_IOPHYSTOVIRT(BCM2835_ARMICU_BASE) 103 104 #define BCM2835_INTC_BASE (0x0) /* Relative to BCM2835_ARMICU_BASE */ 105 106 /* Interrupt controller */ 107 #define BCM2835_INTC_IRQBPENDING (BCM2835_INTC_BASE + 0x00) /* IRQ Basic pending */ 108 #define BCM2835_INTC_IRQ1PENDING (BCM2835_INTC_BASE + 0x04) /* IRQ pending 1 */ 109 #define BCM2835_INTC_IRQ2PENDING (BCM2835_INTC_BASE + 0x08) /* IRQ pending 2 */ 110 #define BCM2835_INTC_FIQCTL (BCM2835_INTC_BASE + 0x0c) /* FIQ control */ 111 #define BCM2835_INTC_IRQ1ENABLE (BCM2835_INTC_BASE + 0x10) /* Enable IRQs 1 */ 112 #define BCM2835_INTC_IRQ2ENABLE (BCM2835_INTC_BASE + 0x14) /* Enable IRQs 2 */ 113 #define BCM2835_INTC_IRQBENABLE (BCM2835_INTC_BASE + 0x18) /* Enable Basic IRQs */ 114 #define BCM2835_INTC_IRQ1DISABLE (BCM2835_INTC_BASE + 0x1c) /* Disable IRQ 1 */ 115 #define BCM2835_INTC_IRQ2DISABLE (BCM2835_INTC_BASE + 0x20) /* Disable IRQ 2 */ 116 #define BCM2835_INTC_IRQBDISABLE (BCM2835_INTC_BASE + 0x24) /* Disable Basic IRQs */ 117 118 #define BCM2835_INTC_ENABLEBASE (BCM2835_INTC_BASE + 0x10) 119 #define BCM2835_INTC_DISABLEBASE (BCM2835_INTC_BASE + 0x1c) 120 121 /* Interrupt source */ 122 #define BCM2835_INT_GPU0BASE 0 123 #define BCM2835_INT_TIMER0 (BCM2835_INT_GPU0BASE + 0) 124 #define BCM2835_INT_TIMER1 (BCM2835_INT_GPU0BASE + 1) 125 #define BCM2835_INT_TIMER2 (BCM2835_INT_GPU0BASE + 2) 126 #define BCM2835_INT_TIMER3 (BCM2835_INT_GPU0BASE + 3) 127 #define BCM2835_INT_USB (BCM2835_INT_GPU0BASE + 9) 128 #define BCM2835_INT_DMA2 (BCM2835_INT_GPU0BASE + 18) 129 #define BCM2835_INT_DMA3 (BCM2835_INT_GPU0BASE + 19) 130 #define BCM2835_INT_AUX (BCM2835_INT_GPU0BASE + 29) 131 #define BCM2835_INT_ARM (BCM2835_INT_GPU0BASE + 30) 132 133 #define BCM2835_INT_GPU1BASE 32 134 #define BCM2835_INT_GPIO0 (BCM2835_INT_GPU1BASE + 17) 135 #define BCM2835_INT_GPIO1 (BCM2835_INT_GPU1BASE + 18) 136 #define BCM2835_INT_GPIO2 (BCM2835_INT_GPU1BASE + 19) 137 #define BCM2835_INT_GPIO3 (BCM2835_INT_GPU1BASE + 20) 138 #define BCM2835_INT_BSC (BCM2835_INT_GPU1BASE + 21) 139 #define BCM2835_INT_SPI0 (BCM2835_INT_GPU1BASE + 22) 140 #define BCM2835_INT_PCM (BCM2835_INT_GPU1BASE + 23) 141 #define BCM2835_INT_UART0 (BCM2835_INT_GPU1BASE + 25) 142 #define BCM2835_INT_EMMC (BCM2835_INT_GPU1BASE + 30) 143 144 #define BCM2835_INT_BASICBASE 64 145 #define BCM2835_INT_ARMTIMER (BCM2835_INT_BASICBASE + 0) 146 #define BCM2835_INT_ARMMAILBOX (BCM2835_INT_BASICBASE + 1) 147 #define BCM2835_INT_ARMDOORBELL0 (BCM2835_INT_BASICBASE + 2) 148 #define BCM2835_INT_ARMDOORBELL1 (BCM2835_INT_BASICBASE + 3) 149 #define BCM2835_INT_GPU0HALTED (BCM2835_INT_BASICBASE + 4) 150 #define BCM2835_INT_GPU1HALTED (BCM2835_INT_BASICBASE + 5) 151 #define BCM2835_INT_ILLEGALTYPE0 (BCM2835_INT_BASICBASE + 6) 152 #define BCM2835_INT_ILLEGALTYPE1 (BCM2835_INT_BASICBASE + 7) 153 154 #define BCM2835_NIRQ 64 + 8 155 156 #define BCM2835_UART0_CLK 3000000 157 158 #endif /* _BCM2835REG_H_ */ 159