1 /* $NetBSD: bcm2835_sdhost.c,v 1.5 2020/05/31 23:52:19 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: bcm2835_sdhost.c,v 1.5 2020/05/31 23:52:19 thorpej Exp $"); 31 32 #include "bcmdmac.h" 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/gpio.h> 41 42 #include <arm/broadcom/bcm2835reg.h> 43 #include <arm/broadcom/bcm2835_dmac.h> 44 45 #include <dev/sdmmc/sdmmcvar.h> 46 #include <dev/sdmmc/sdmmcchip.h> 47 #include <dev/sdmmc/sdmmc_ioreg.h> 48 49 #include <dev/fdt/fdtvar.h> 50 51 #include <arm/fdt/arm_fdtvar.h> 52 53 #define SDCMD 0x00 54 #define SDCMD_NEW __BIT(15) 55 #define SDCMD_FAIL __BIT(14) 56 #define SDCMD_BUSY __BIT(11) 57 #define SDCMD_NORESP __BIT(10) 58 #define SDCMD_LONGRESP __BIT(9) 59 #define SDCMD_WRITE __BIT(7) 60 #define SDCMD_READ __BIT(6) 61 #define SDARG 0x04 62 #define SDTOUT 0x08 63 #define SDTOUT_DEFAULT 0xf00000 64 #define SDCDIV 0x0c 65 #define SDCDIV_MASK __BITS(10,0) 66 #define SDRSP0 0x10 67 #define SDRSP1 0x14 68 #define SDRSP2 0x18 69 #define SDRSP3 0x1c 70 #define SDHSTS 0x20 71 #define SDHSTS_BUSY __BIT(10) 72 #define SDHSTS_BLOCK __BIT(9) 73 #define SDHSTS_SDIO __BIT(8) 74 #define SDHSTS_REW_TO __BIT(7) 75 #define SDHSTS_CMD_TO __BIT(6) 76 #define SDHSTS_CRC16_E __BIT(5) 77 #define SDHSTS_CRC7_E __BIT(4) 78 #define SDHSTS_FIFO_E __BIT(3) 79 #define SDHSTS_DATA __BIT(0) 80 #define SDVDD 0x30 81 #define SDVDD_POWER __BIT(0) 82 #define SDEDM 0x34 83 #define SDEDM_RD_FIFO __BITS(18,14) 84 #define SDEDM_WR_FIFO __BITS(13,9) 85 #define SDHCFG 0x38 86 #define SDHCFG_BUSY_EN __BIT(10) 87 #define SDHCFG_BLOCK_EN __BIT(8) 88 #define SDHCFG_SDIO_EN __BIT(5) 89 #define SDHCFG_DATA_EN __BIT(4) 90 #define SDHCFG_SLOW __BIT(3) 91 #define SDHCFG_WIDE_EXT __BIT(2) 92 #define SDHCFG_WIDE_INT __BIT(1) 93 #define SDHCFG_REL_CMD __BIT(0) 94 #define SDHBCT 0x3c 95 #define SDDATA 0x40 96 #define SDHBLC 0x50 97 98 struct sdhost_softc; 99 100 static int sdhost_match(device_t, cfdata_t, void *); 101 static void sdhost_attach(device_t, device_t, void *); 102 static void sdhost_attach_i(device_t); 103 104 static int sdhost_intr(void *); 105 static int sdhost_dma_setup(struct sdhost_softc *); 106 static void sdhost_dma_done(uint32_t, uint32_t, void *); 107 108 static int sdhost_host_reset(sdmmc_chipset_handle_t); 109 static uint32_t sdhost_host_ocr(sdmmc_chipset_handle_t); 110 static int sdhost_host_maxblklen(sdmmc_chipset_handle_t); 111 static int sdhost_card_detect(sdmmc_chipset_handle_t); 112 static int sdhost_write_protect(sdmmc_chipset_handle_t); 113 static int sdhost_bus_power(sdmmc_chipset_handle_t, uint32_t); 114 static int sdhost_bus_clock(sdmmc_chipset_handle_t, int, bool); 115 static int sdhost_bus_width(sdmmc_chipset_handle_t, int); 116 static int sdhost_bus_rod(sdmmc_chipset_handle_t, int); 117 static void sdhost_exec_command(sdmmc_chipset_handle_t, 118 struct sdmmc_command *); 119 static void sdhost_card_enable_intr(sdmmc_chipset_handle_t, int); 120 static void sdhost_card_intr_ack(sdmmc_chipset_handle_t); 121 122 static struct sdmmc_chip_functions sdhost_chip_functions = { 123 .host_reset = sdhost_host_reset, 124 .host_ocr = sdhost_host_ocr, 125 .host_maxblklen = sdhost_host_maxblklen, 126 .card_detect = sdhost_card_detect, 127 .write_protect = sdhost_write_protect, 128 .bus_power = sdhost_bus_power, 129 .bus_clock_ddr = sdhost_bus_clock, 130 .bus_width = sdhost_bus_width, 131 .bus_rod = sdhost_bus_rod, 132 .exec_command = sdhost_exec_command, 133 .card_enable_intr = sdhost_card_enable_intr, 134 .card_intr_ack = sdhost_card_intr_ack, 135 }; 136 137 struct sdhost_softc { 138 device_t sc_dev; 139 bus_space_tag_t sc_bst; 140 bus_space_handle_t sc_bsh; 141 bus_dma_tag_t sc_dmat; 142 143 bus_addr_t sc_addr; 144 145 void *sc_ih; 146 kmutex_t sc_intr_lock; 147 kcondvar_t sc_intr_cv; 148 kcondvar_t sc_dma_cv; 149 150 u_int sc_rate; 151 152 int sc_mmc_width; 153 int sc_mmc_present; 154 155 device_t sc_sdmmc_dev; 156 157 struct bcm_dmac_channel *sc_dmac; 158 159 bus_dmamap_t sc_dmamap; 160 bus_dma_segment_t sc_segs[1]; 161 struct bcm_dmac_conblk *sc_cblk; 162 163 uint32_t sc_intr_hsts; 164 165 uint32_t sc_dma_status; 166 uint32_t sc_dma_error; 167 }; 168 169 CFATTACH_DECL_NEW(bcmsdhost, sizeof(struct sdhost_softc), 170 sdhost_match, sdhost_attach, NULL, NULL); 171 172 #define SDHOST_WRITE(sc, reg, val) \ 173 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 174 #define SDHOST_READ(sc, reg) \ 175 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 176 177 static int 178 sdhost_match(device_t parent, cfdata_t cf, void *aux) 179 { 180 const char * const compatible[] = { 181 "brcm,bcm2835-sdhost", 182 NULL 183 }; 184 struct fdt_attach_args * const faa = aux; 185 186 return of_match_compatible(faa->faa_phandle, compatible); 187 } 188 189 static void 190 sdhost_attach(device_t parent, device_t self, void *aux) 191 { 192 struct sdhost_softc * const sc = device_private(self); 193 struct fdt_attach_args * const faa = aux; 194 195 sc->sc_dev = self; 196 sc->sc_bst = faa->faa_bst; 197 sc->sc_dmat = faa->faa_dmat; 198 199 const int phandle = faa->faa_phandle; 200 bus_addr_t addr; 201 bus_size_t size; 202 203 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 204 aprint_error(": missing 'reg' property\n"); 205 return; 206 } 207 208 sc->sc_addr = addr; 209 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO); 210 cv_init(&sc->sc_intr_cv, "sdhostintr"); 211 cv_init(&sc->sc_dma_cv, "sdhostdma"); 212 213 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 214 aprint_error(": couldn't map registers\n"); 215 return; 216 } 217 218 aprint_naive("\n"); 219 aprint_normal(": SD HOST controller\n"); 220 221 /* Enable clocks */ 222 struct clk *clk; 223 for (int i = 0; (clk = fdtbus_clock_get_index(phandle, i)); i++) { 224 if (clk_enable(clk) != 0) { 225 aprint_error(": failed to enable clock #%d\n", i); 226 return; 227 } 228 if (i == 0) 229 sc->sc_rate = clk_get_rate(clk); 230 } 231 232 aprint_debug_dev(self, "ref freq %u Hz\n", sc->sc_rate); 233 234 if (sdhost_dma_setup(sc) != 0) { 235 aprint_error_dev(self, "failed to setup DMA\n"); 236 return; 237 } 238 239 char intrstr[128]; 240 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 241 aprint_error(": failed to decode interrupt\n"); 242 return; 243 } 244 245 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_SDMMC, 246 FDT_INTR_MPSAFE, sdhost_intr, sc); 247 if (sc->sc_ih == NULL) { 248 aprint_error_dev(self, "failed to establish interrupt %s\n", 249 intrstr); 250 return; 251 } 252 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 253 254 config_interrupts(self, sdhost_attach_i); 255 } 256 257 static int 258 sdhost_dma_setup(struct sdhost_softc *sc) 259 { 260 int error, rseg; 261 262 sc->sc_dmac = bcm_dmac_alloc(BCM_DMAC_TYPE_NORMAL, IPL_SDMMC, 263 sdhost_dma_done, sc); 264 if (sc->sc_dmac == NULL) 265 return ENXIO; 266 267 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 268 PAGE_SIZE, sc->sc_segs, 1, &rseg, BUS_DMA_WAITOK); 269 if (error) 270 return error; 271 272 error = bus_dmamem_map(sc->sc_dmat, sc->sc_segs, rseg, PAGE_SIZE, 273 (void **)&sc->sc_cblk, BUS_DMA_WAITOK); 274 if (error) 275 return error; 276 277 memset(sc->sc_cblk, 0, PAGE_SIZE); 278 279 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 0, 280 BUS_DMA_WAITOK, &sc->sc_dmamap); 281 if (error) 282 return error; 283 284 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, sc->sc_cblk, 285 PAGE_SIZE, NULL, BUS_DMA_WAITOK|BUS_DMA_WRITE); 286 if (error) 287 return error; 288 289 return 0; 290 } 291 292 static void 293 sdhost_attach_i(device_t self) 294 { 295 struct sdhost_softc *sc = device_private(self); 296 struct sdmmcbus_attach_args saa; 297 298 sdhost_host_reset(sc); 299 sdhost_bus_width(sc, 1); 300 sdhost_bus_clock(sc, 400, false); 301 302 memset(&saa, 0, sizeof(saa)); 303 saa.saa_busname = "sdmmc"; 304 saa.saa_sct = &sdhost_chip_functions; 305 saa.saa_sch = sc; 306 saa.saa_dmat = sc->sc_dmat; 307 saa.saa_clkmin = 400; 308 saa.saa_clkmax = 50000; 309 saa.saa_caps = SMC_CAPS_DMA | 310 SMC_CAPS_MULTI_SEG_DMA | 311 SMC_CAPS_SD_HIGHSPEED | 312 SMC_CAPS_MMC_HIGHSPEED | 313 SMC_CAPS_4BIT_MODE; 314 315 sc->sc_sdmmc_dev = config_found(self, &saa, NULL); 316 } 317 318 static int 319 sdhost_intr(void *priv) 320 { 321 struct sdhost_softc * const sc = priv; 322 323 mutex_enter(&sc->sc_intr_lock); 324 const uint32_t hsts = SDHOST_READ(sc, SDHSTS); 325 if (!hsts) { 326 mutex_exit(&sc->sc_intr_lock); 327 return 0; 328 } 329 SDHOST_WRITE(sc, SDHSTS, hsts); 330 331 #ifdef SDHOST_DEBUG 332 device_printf(sc->sc_dev, "mmc intr hsts %#x\n", hsts); 333 #endif 334 335 if (hsts) { 336 sc->sc_intr_hsts |= hsts; 337 cv_broadcast(&sc->sc_intr_cv); 338 } 339 340 mutex_exit(&sc->sc_intr_lock); 341 342 return 1; 343 } 344 345 static int 346 sdhost_dma_transfer(struct sdhost_softc *sc, struct sdmmc_command *cmd) 347 { 348 size_t seg; 349 int error; 350 351 KASSERT(mutex_owned(&sc->sc_intr_lock)); 352 353 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 354 sc->sc_cblk[seg].cb_ti = 355 __SHIFTIN(13, DMAC_TI_PERMAP); /* SD HOST */ 356 sc->sc_cblk[seg].cb_txfr_len = 357 cmd->c_dmamap->dm_segs[seg].ds_len; 358 const bus_addr_t ad_sddata = sc->sc_addr + SDDATA; 359 360 /* 361 * All transfers are assumed to be multiples of 32-bits. 362 */ 363 KASSERTMSG((sc->sc_cblk[seg].cb_txfr_len & 0x3) == 0, 364 "seg %zu len %d", seg, sc->sc_cblk[seg].cb_txfr_len); 365 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 366 sc->sc_cblk[seg].cb_ti |= DMAC_TI_DEST_INC; 367 /* 368 * Use 128-bit mode if transfer is a multiple of 369 * 16-bytes. 370 */ 371 if ((sc->sc_cblk[seg].cb_txfr_len & 0xf) == 0) 372 sc->sc_cblk[seg].cb_ti |= DMAC_TI_DEST_WIDTH; 373 sc->sc_cblk[seg].cb_ti |= DMAC_TI_SRC_DREQ; 374 sc->sc_cblk[seg].cb_source_ad = ad_sddata; 375 sc->sc_cblk[seg].cb_dest_ad = 376 cmd->c_dmamap->dm_segs[seg].ds_addr; 377 } else { 378 sc->sc_cblk[seg].cb_ti |= DMAC_TI_SRC_INC; 379 /* 380 * Use 128-bit mode if transfer is a multiple of 381 * 16-bytes. 382 */ 383 if ((sc->sc_cblk[seg].cb_txfr_len & 0xf) == 0) 384 sc->sc_cblk[seg].cb_ti |= DMAC_TI_SRC_WIDTH; 385 sc->sc_cblk[seg].cb_ti |= DMAC_TI_DEST_DREQ; 386 sc->sc_cblk[seg].cb_ti |= DMAC_TI_WAIT_RESP; 387 sc->sc_cblk[seg].cb_source_ad = 388 cmd->c_dmamap->dm_segs[seg].ds_addr; 389 sc->sc_cblk[seg].cb_dest_ad = ad_sddata; 390 } 391 sc->sc_cblk[seg].cb_stride = 0; 392 if (seg == cmd->c_dmamap->dm_nsegs - 1) { 393 sc->sc_cblk[seg].cb_ti |= DMAC_TI_INTEN; 394 sc->sc_cblk[seg].cb_nextconbk = 0; 395 } else { 396 sc->sc_cblk[seg].cb_nextconbk = 397 sc->sc_dmamap->dm_segs[0].ds_addr + 398 sizeof(struct bcm_dmac_conblk) * (seg+1); 399 } 400 sc->sc_cblk[seg].cb_padding[0] = 0; 401 sc->sc_cblk[seg].cb_padding[1] = 0; 402 } 403 404 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, 405 sc->sc_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 406 407 error = 0; 408 409 sc->sc_dma_status = 0; 410 sc->sc_dma_error = 0; 411 412 bcm_dmac_set_conblk_addr(sc->sc_dmac, 413 sc->sc_dmamap->dm_segs[0].ds_addr); 414 error = bcm_dmac_transfer(sc->sc_dmac); 415 if (error) 416 return error; 417 418 return 0; 419 } 420 421 static int 422 sdhost_dma_wait(struct sdhost_softc *sc, struct sdmmc_command *cmd) 423 { 424 int error = 0; 425 426 while (sc->sc_dma_status == 0 && sc->sc_dma_error == 0) { 427 error = cv_timedwait(&sc->sc_dma_cv, &sc->sc_intr_lock, hz*5); 428 if (error == EWOULDBLOCK) { 429 device_printf(sc->sc_dev, "transfer timeout!\n"); 430 bcm_dmac_halt(sc->sc_dmac); 431 error = ETIMEDOUT; 432 break; 433 } 434 } 435 436 if (sc->sc_dma_status & DMAC_CS_END) { 437 cmd->c_resid = 0; 438 error = 0; 439 } else { 440 error = EIO; 441 } 442 443 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, 444 sc->sc_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 445 446 return error; 447 } 448 449 static void 450 sdhost_dma_done(uint32_t status, uint32_t error, void *arg) 451 { 452 struct sdhost_softc * const sc = arg; 453 454 if (status != (DMAC_CS_INT|DMAC_CS_END)) 455 device_printf(sc->sc_dev, "dma status %#x error %#x\n", 456 status, error); 457 458 mutex_enter(&sc->sc_intr_lock); 459 sc->sc_dma_status = status; 460 sc->sc_dma_error = error; 461 cv_broadcast(&sc->sc_dma_cv); 462 mutex_exit(&sc->sc_intr_lock); 463 } 464 465 static int 466 sdhost_wait_idle(struct sdhost_softc *sc, int timeout) 467 { 468 int retry; 469 470 KASSERT(mutex_owned(&sc->sc_intr_lock)); 471 472 retry = timeout * 1000; 473 474 while (--retry > 0) { 475 const uint32_t cmd = SDHOST_READ(sc, SDCMD); 476 if ((cmd & SDCMD_NEW) == 0) 477 return 0; 478 delay(1); 479 } 480 481 return ETIMEDOUT; 482 } 483 484 static int 485 sdhost_host_reset(sdmmc_chipset_handle_t sch) 486 { 487 struct sdhost_softc * const sc = sch; 488 uint32_t edm; 489 490 SDHOST_WRITE(sc, SDVDD, 0); 491 SDHOST_WRITE(sc, SDCMD, 0); 492 SDHOST_WRITE(sc, SDARG, 0); 493 SDHOST_WRITE(sc, SDTOUT, SDTOUT_DEFAULT); 494 SDHOST_WRITE(sc, SDCDIV, 0); 495 SDHOST_WRITE(sc, SDHSTS, SDHOST_READ(sc, SDHSTS)); 496 SDHOST_WRITE(sc, SDHCFG, 0); 497 SDHOST_WRITE(sc, SDHBCT, 0); 498 SDHOST_WRITE(sc, SDHBLC, 0); 499 500 edm = SDHOST_READ(sc, SDEDM); 501 edm &= ~(SDEDM_RD_FIFO|SDEDM_WR_FIFO); 502 edm |= __SHIFTIN(4, SDEDM_RD_FIFO); 503 edm |= __SHIFTIN(4, SDEDM_WR_FIFO); 504 SDHOST_WRITE(sc, SDEDM, edm); 505 delay(20000); 506 SDHOST_WRITE(sc, SDVDD, SDVDD_POWER); 507 delay(20000); 508 509 SDHOST_WRITE(sc, SDHCFG, 0); 510 SDHOST_WRITE(sc, SDCDIV, SDCDIV_MASK); 511 512 return 0; 513 } 514 515 static uint32_t 516 sdhost_host_ocr(sdmmc_chipset_handle_t sch) 517 { 518 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V | MMC_OCR_HCS; 519 } 520 521 static int 522 sdhost_host_maxblklen(sdmmc_chipset_handle_t sch) 523 { 524 return 8192; 525 } 526 527 static int 528 sdhost_card_detect(sdmmc_chipset_handle_t sch) 529 { 530 return 1; /* XXX */ 531 } 532 533 static int 534 sdhost_write_protect(sdmmc_chipset_handle_t sch) 535 { 536 return 0; /* no write protect pin, assume rw */ 537 } 538 539 static int 540 sdhost_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 541 { 542 return 0; 543 } 544 545 static int 546 sdhost_bus_clock(sdmmc_chipset_handle_t sch, int freq, bool ddr) 547 { 548 struct sdhost_softc * const sc = sch; 549 u_int target_rate = freq * 1000; 550 int div; 551 552 if (freq == 0) 553 div = SDCDIV_MASK; 554 else { 555 div = sc->sc_rate / target_rate; 556 if (div < 2) 557 div = 2; 558 if ((sc->sc_rate / div) > target_rate) 559 div++; 560 div -= 2; 561 if (div > SDCDIV_MASK) 562 div = SDCDIV_MASK; 563 } 564 565 SDHOST_WRITE(sc, SDCDIV, div); 566 567 return 0; 568 } 569 570 static int 571 sdhost_bus_width(sdmmc_chipset_handle_t sch, int width) 572 { 573 struct sdhost_softc * const sc = sch; 574 uint32_t hcfg; 575 576 #ifdef SDHOST_DEBUG 577 aprint_normal_dev(sc->sc_dev, "width = %d\n", width); 578 #endif 579 580 hcfg = SDHOST_READ(sc, SDHCFG); 581 if (width == 4) 582 hcfg |= SDHCFG_WIDE_EXT; 583 else 584 hcfg &= ~SDHCFG_WIDE_EXT; 585 hcfg |= (SDHCFG_WIDE_INT | SDHCFG_SLOW); 586 SDHOST_WRITE(sc, SDHCFG, hcfg); 587 588 return 0; 589 } 590 591 static int 592 sdhost_bus_rod(sdmmc_chipset_handle_t sch, int on) 593 { 594 return -1; 595 } 596 597 static void 598 sdhost_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 599 { 600 struct sdhost_softc * const sc = sch; 601 uint32_t cmdval, hcfg; 602 u_int nblks; 603 604 #ifdef SDHOST_DEBUG 605 aprint_normal_dev(sc->sc_dev, 606 "opcode %d flags 0x%x data %p datalen %d blklen %d\n", 607 cmd->c_opcode, cmd->c_flags, cmd->c_data, cmd->c_datalen, 608 cmd->c_blklen); 609 #endif 610 611 mutex_enter(&sc->sc_intr_lock); 612 613 hcfg = SDHOST_READ(sc, SDHCFG); 614 SDHOST_WRITE(sc, SDHCFG, hcfg | SDHCFG_BUSY_EN); 615 616 sc->sc_intr_hsts = 0; 617 618 cmd->c_error = sdhost_wait_idle(sc, 5000); 619 if (cmd->c_error != 0) { 620 #ifdef SDHOST_DEBUG 621 device_printf(sc->sc_dev, "device is busy\n"); 622 #endif 623 goto done; 624 } 625 626 cmdval = SDCMD_NEW; 627 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 628 cmdval |= SDCMD_NORESP; 629 if (ISSET(cmd->c_flags, SCF_RSP_136)) 630 cmdval |= SDCMD_LONGRESP; 631 if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 632 cmdval |= SDCMD_BUSY; 633 634 if (cmd->c_datalen > 0) { 635 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 636 cmdval |= SDCMD_READ; 637 else 638 cmdval |= SDCMD_WRITE; 639 640 nblks = cmd->c_datalen / cmd->c_blklen; 641 if (nblks == 0 || (cmd->c_datalen % cmd->c_blklen) != 0) 642 ++nblks; 643 644 SDHOST_WRITE(sc, SDHBCT, cmd->c_blklen); 645 SDHOST_WRITE(sc, SDHBLC, nblks); 646 647 cmd->c_resid = cmd->c_datalen; 648 cmd->c_error = sdhost_dma_transfer(sc, cmd); 649 if (cmd->c_error != 0) { 650 #ifdef SDHOST_DEBUG 651 device_printf(sc->sc_dev, "dma transfer failed: %d\n", 652 cmd->c_error); 653 #endif 654 goto done; 655 } 656 } 657 658 SDHOST_WRITE(sc, SDARG, cmd->c_arg); 659 SDHOST_WRITE(sc, SDCMD, cmdval | cmd->c_opcode); 660 661 if (cmd->c_datalen > 0) { 662 cmd->c_error = sdhost_dma_wait(sc, cmd); 663 if (cmd->c_error != 0) { 664 #ifdef SDHOST_DEBUG 665 device_printf(sc->sc_dev, 666 "wait dma failed: %d\n", cmd->c_error); 667 #endif 668 goto done; 669 } 670 } 671 672 cmd->c_error = sdhost_wait_idle(sc, 5000); 673 if (cmd->c_error != 0) { 674 #ifdef SDHOST_DEBUG 675 device_printf(sc->sc_dev, 676 "wait cmd idle (%#x) failed: %d\n", 677 SDHOST_READ(sc, SDCMD), cmd->c_error); 678 #endif 679 } 680 681 if ((SDHOST_READ(sc, SDCMD) & SDCMD_FAIL) != 0) { 682 #ifdef SDHOST_DEBUG 683 device_printf(sc->sc_dev, "SDCMD: %#x\n", 684 SDHOST_READ(sc, SDCMD)); 685 #endif 686 cmd->c_error = EIO; 687 goto done; 688 } 689 690 if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 691 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 692 cmd->c_resp[0] = SDHOST_READ(sc, SDRSP0); 693 cmd->c_resp[1] = SDHOST_READ(sc, SDRSP1); 694 cmd->c_resp[2] = SDHOST_READ(sc, SDRSP2); 695 cmd->c_resp[3] = SDHOST_READ(sc, SDRSP3); 696 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) { 697 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 698 (cmd->c_resp[1] << 24); 699 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 700 (cmd->c_resp[2] << 24); 701 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 702 (cmd->c_resp[3] << 24); 703 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 704 } 705 } else { 706 cmd->c_resp[0] = SDHOST_READ(sc, SDRSP0); 707 } 708 } 709 710 done: 711 cmd->c_flags |= SCF_ITSDONE; 712 SDHOST_WRITE(sc, SDHCFG, hcfg); 713 SDHOST_WRITE(sc, SDHSTS, SDHOST_READ(sc, SDHSTS)); 714 mutex_exit(&sc->sc_intr_lock); 715 716 #ifdef SDHOST_DEBUG 717 if (cmd->c_error != 0) 718 device_printf(sc->sc_dev, "command failed with error %d\n", 719 cmd->c_error); 720 #endif 721 } 722 723 static void 724 sdhost_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 725 { 726 } 727 728 static void 729 sdhost_card_intr_ack(sdmmc_chipset_handle_t sch) 730 { 731 } 732