1 /* $NetBSD: bcm2835_cm.c,v 1.1 2015/11/21 07:41:29 mlelstv Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Michael van Elst 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for BCM2835 Clock Manager 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: bcm2835_cm.c,v 1.1 2015/11/21 07:41:29 mlelstv Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <sys/kernel.h> 43 #include <sys/bus.h> 44 45 #include <arm/broadcom/bcm2835reg.h> 46 #include <arm/broadcom/bcm_amba.h> 47 48 #include <arm/broadcom/bcm2835_cm.h> 49 50 struct bcm2835cm_softc { 51 device_t sc_dev; 52 53 bus_space_tag_t sc_iot; 54 bus_space_handle_t sc_ioh; 55 }; 56 57 #define CM_WRITE(sc, reg, val) \ 58 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 59 #define CM_READ(sc, reg) \ 60 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 61 62 static int bcmcm_match(device_t, cfdata_t, void *); 63 static void bcmcm_attach(device_t, device_t, void *); 64 static int bcmcm_wait(struct bcm2835cm_softc *, int, int); 65 66 CFATTACH_DECL_NEW(bcmcm_amba, sizeof(struct bcm2835cm_softc), 67 bcmcm_match, bcmcm_attach, NULL, NULL); 68 69 /* ARGSUSED */ 70 static int 71 bcmcm_match(device_t parent, cfdata_t match, void *aux) 72 { 73 struct amba_attach_args *aaa = aux; 74 75 if (strcmp(aaa->aaa_name, "bcmcm") != 0) 76 return 0; 77 78 if (aaa->aaa_addr != BCM2835_CM_BASE) 79 return 0; 80 81 return 1; 82 } 83 84 static void 85 bcmcm_attach(device_t parent, device_t self, void *aux) 86 { 87 struct bcm2835cm_softc *sc = device_private(self); 88 struct amba_attach_args *aaa = aux; 89 90 aprint_naive("\n"); 91 aprint_normal(": CM\n"); 92 93 sc->sc_dev = self; 94 sc->sc_iot = aaa->aaa_iot; 95 96 if (bus_space_map(aaa->aaa_iot, aaa->aaa_addr, BCM2835_CM_SIZE, 0, 97 &sc->sc_ioh)) { 98 aprint_error_dev(sc->sc_dev, "unable to map device\n"); 99 goto fail0; 100 } 101 102 /* Success! */ 103 104 fail0: return; 105 } 106 107 static int 108 bcmcm_wait(struct bcm2835cm_softc *sc, int ctlreg, int onoff) 109 { 110 int i; 111 uint32_t r; 112 113 for (i=0; i<100; ++i) { 114 r = CM_READ(sc, ctlreg); 115 if (((r & CM_CTL_BUSY) != 0) == onoff) 116 break; 117 delay(10); 118 } 119 if (i >= 100) { 120 device_printf(sc->sc_dev, "busy (addr=%#x)\n", ctlreg); 121 return EIO; 122 } 123 124 return 0; 125 } 126 127 int 128 bcm_cm_set(enum bcm_cm_clock clk, uint32_t ctl, uint32_t div) 129 { 130 struct bcm2835cm_softc *sc; 131 device_t dev; 132 int ctlreg, divreg; 133 uint32_t r; 134 135 dev = device_find_by_driver_unit("bcmcm", 0); 136 if (dev == NULL) 137 return ENXIO; 138 sc = device_private(dev); 139 140 switch (clk) { 141 case BCM_CM_GP0: 142 ctlreg = CM_GP0CTL; 143 divreg = CM_GP0DIV; 144 break; 145 case BCM_CM_GP1: 146 ctlreg = CM_GP1CTL; 147 divreg = CM_GP1DIV; 148 break; 149 case BCM_CM_GP2: 150 ctlreg = CM_GP2CTL; 151 divreg = CM_GP2DIV; 152 break; 153 case BCM_CM_PCM: 154 ctlreg = CM_PCMCTL; 155 divreg = CM_PCMDIV; 156 break; 157 case BCM_CM_PWM: 158 ctlreg = CM_PWMCTL; 159 divreg = CM_PWMDIV; 160 break; 161 default: 162 return EINVAL; 163 } 164 165 ctl &= ~CM_CTL_PASSWD; 166 ctl |= __SHIFTIN(CM_PASSWD, CM_CTL_PASSWD); 167 div &= ~CM_DIV_PASSWD; 168 div |= __SHIFTIN(CM_PASSWD, CM_DIV_PASSWD); 169 170 /* if clock is running, turn it off and wait for 171 * the cycle to end 172 */ 173 r = CM_READ(sc, ctlreg); 174 if (r & CM_CTL_ENAB) { 175 r &= ~CM_CTL_PASSWD; 176 r |= __SHIFTIN(CM_PASSWD, CM_CTL_PASSWD); 177 r &= ~CM_CTL_ENAB; 178 CM_WRITE(sc, ctlreg, r); 179 } 180 181 bcmcm_wait(sc, ctlreg, 0); 182 183 /* configure new divider, mode, don't enable */ 184 CM_WRITE(sc, divreg, div); 185 CM_WRITE(sc, ctlreg, ctl & ~CM_CTL_ENAB); 186 187 /* enable it */ 188 if (ctl & CM_CTL_ENAB) { 189 CM_WRITE(sc, ctlreg, ctl); 190 return bcmcm_wait(sc, ctlreg, 1); 191 } 192 193 return 0; 194 } 195 196 int 197 bcm_cm_get(enum bcm_cm_clock clk, uint32_t *ctlp, uint32_t *divp) 198 { 199 struct bcm2835cm_softc *sc; 200 device_t dev; 201 int ctlreg, divreg; 202 203 dev = device_find_by_driver_unit("bcmcm", 0); 204 if (dev == NULL) 205 return ENXIO; 206 sc = device_private(dev); 207 208 switch (clk) { 209 case BCM_CM_GP0: 210 ctlreg = CM_GP0CTL; 211 divreg = CM_GP0DIV; 212 break; 213 case BCM_CM_GP1: 214 ctlreg = CM_GP1CTL; 215 divreg = CM_GP1DIV; 216 break; 217 case BCM_CM_GP2: 218 ctlreg = CM_GP2CTL; 219 divreg = CM_GP2DIV; 220 break; 221 case BCM_CM_PCM: 222 ctlreg = CM_PCMCTL; 223 divreg = CM_PCMDIV; 224 break; 225 case BCM_CM_PWM: 226 ctlreg = CM_PWMCTL; 227 divreg = CM_PWMDIV; 228 break; 229 default: 230 return EINVAL; 231 } 232 233 if (ctlp != NULL) 234 *ctlp = CM_READ(sc, ctlreg); 235 if (divp != NULL) 236 *divp = CM_READ(sc, divreg); 237 238 return 0; 239 } 240