1 /* $Id: at91twi.c,v 1.7 2016/02/14 19:54:20 chs Exp $ */ 2 /* $NetBSD: at91twi.c,v 1.7 2016/02/14 19:54:20 chs Exp $ */ 3 4 /*- 5 * Copyright (c) 2007 Embedtronics Oy. All rights reserved. 6 * 7 * Based on arch/macppc/dev/ki2c.c, 8 * Copyright (c) 2001 Tsubai Masanari. All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: at91twi.c,v 1.7 2016/02/14 19:54:20 chs Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/device.h> 38 #include <sys/systm.h> 39 40 #include <sys/bus.h> 41 #include <sys/lock.h> 42 43 #include <arm/at91/at91var.h> 44 #include <arm/at91/at91reg.h> 45 46 #include <dev/i2c/i2cvar.h> 47 #include <arm/at91/at91twivar.h> 48 #include <arm/at91/at91twireg.h> 49 50 int at91twi_match(device_t, cfdata_t, void *); 51 void at91twi_attach(device_t, device_t, void *); 52 inline u_int at91twi_readreg(struct at91twi_softc *, int); 53 inline void at91twi_writereg(struct at91twi_softc *, int, u_int); 54 int at91twi_intr(void *); 55 int at91twi_poll(struct at91twi_softc *, int, int); 56 int at91twi_start(struct at91twi_softc *, int, void *, int, int); 57 int at91twi_read(struct at91twi_softc *, int, void *, int, int); 58 int at91twi_write(struct at91twi_softc *, int, void *, int, int); 59 60 /* I2C glue */ 61 static int at91twi_i2c_acquire_bus(void *, int); 62 static void at91twi_i2c_release_bus(void *, int); 63 static int at91twi_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 64 void *, size_t, int); 65 66 67 CFATTACH_DECL_NEW(at91twi, sizeof(struct at91twi_softc), 68 at91twi_match, at91twi_attach, NULL, NULL); 69 70 int 71 at91twi_match(device_t parent, cfdata_t match, void *aux) 72 { 73 if (strcmp(match->cf_name, "at91twi") == 0) 74 return 2; 75 return 0; 76 } 77 78 void 79 at91twi_attach(device_t parent, device_t self, void *aux) 80 { 81 struct at91twi_softc *sc = device_private(self); 82 struct at91bus_attach_args *sa = aux; 83 struct i2cbus_attach_args iba; 84 unsigned ckdiv, cxdiv; 85 86 // gather attach data: 87 sc->sc_dev = self; 88 sc->sc_iot = sa->sa_iot; 89 sc->sc_pid = sa->sa_pid; 90 91 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 0, &sc->sc_ioh)) 92 panic("%s: Cannot map registers", device_xname(self)); 93 94 printf(": I2C controller\n"); 95 96 /* initialize I2C controller */ 97 at91_peripheral_clock(sc->sc_pid, 1); 98 99 at91twi_writereg(sc, TWI_CR, TWI_CR_SWRST); 100 delay(1000); 101 #if 1 102 // target to 100 kHz 103 for (ckdiv = 0; ckdiv < 8; ckdiv++) { 104 if ((cxdiv = (AT91_MSTCLK / (1U << ckdiv)) / (2 * 50000U)) < 256) { 105 goto found_ckdiv; 106 } 107 } 108 panic("%s: Cannot calculate clock divider!", __FUNCTION__); 109 110 found_ckdiv: 111 #else 112 ckdiv = 5; cxdiv = 0xFF; 113 #endif 114 at91twi_writereg(sc, TWI_CWGR, (ckdiv << 16) | (cxdiv << 8) | cxdiv); 115 at91twi_writereg(sc, TWI_CR, TWI_CR_MSEN); 116 117 //#ifdef AT91TWI_DEBUG 118 printf("%s: ckdiv=%d cxdiv=%d CWGR=0x%08X SR=0x%08X\n", device_xname(self), ckdiv, cxdiv, at91twi_readreg(sc, TWI_CWGR), at91twi_readreg(sc, TWI_SR)); 119 //#endif 120 121 /* initialize rest */ 122 mutex_init(&sc->sc_buslock, MUTEX_DEFAULT, IPL_NONE); 123 sc->sc_ih = at91_intr_establish(sc->sc_pid, IPL_SERIAL, INTR_HIGH_LEVEL, 124 at91twi_intr, sc); 125 126 /* fill in the i2c tag */ 127 sc->sc_i2c.ic_cookie = sc; 128 sc->sc_i2c.ic_acquire_bus = at91twi_i2c_acquire_bus; 129 sc->sc_i2c.ic_release_bus = at91twi_i2c_release_bus; 130 sc->sc_i2c.ic_send_start = NULL; 131 sc->sc_i2c.ic_send_stop = NULL; 132 sc->sc_i2c.ic_initiate_xfer = NULL; 133 sc->sc_i2c.ic_read_byte = NULL; 134 sc->sc_i2c.ic_write_byte = NULL; 135 sc->sc_i2c.ic_exec = at91twi_i2c_exec; 136 137 memset(&iba, 0, sizeof(iba)); 138 iba.iba_tag = &sc->sc_i2c; 139 (void) config_found_ia(sc->sc_dev, "i2cbus", &iba, iicbus_print); 140 } 141 142 u_int 143 at91twi_readreg(struct at91twi_softc *sc, int reg) 144 { 145 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg); 146 } 147 148 void 149 at91twi_writereg(struct at91twi_softc *sc, int reg, u_int val) 150 { 151 bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, val); 152 } 153 154 int 155 at91twi_intr(void *arg) 156 { 157 struct at91twi_softc *sc = arg; 158 u_int sr, isr, imr; 159 160 sr = at91twi_readreg(sc, TWI_SR); 161 imr = at91twi_readreg(sc, TWI_IMR); 162 isr = sr & imr; 163 164 if (!isr) { 165 #ifdef AT91TWI_DEBUG 166 // printf("%s(%s): interrupts are disabled (sr=%08X imr=%08X)\n", __FUNCTION__, device_xname(sc->sc_dev), sr, imr); 167 #endif 168 return 0; 169 } 170 171 if (isr & TWI_SR_TXCOMP) { 172 // transmission has completed! 173 if (sr & (TWI_SR_NACK | TWI_SR_UNRE | TWI_SR_OVRE)) { 174 // failed! 175 #ifdef AT91TWI_DEBUG 176 printf("%s(%s): FAILED (sr=%08X)\n", __FUNCTION__, 177 device_xname(sc->sc_dev), sr); 178 #endif 179 sc->sc_flags |= I2C_ERROR; 180 } else { 181 #ifdef AT91TWI_DEBUG 182 printf("%s(%s): SUCCESS (sr=%08X)\n", __FUNCTION__, 183 device_xname(sc->sc_dev), sr); 184 #endif 185 } 186 if (sc->sc_flags & I2C_READING && sr & TWI_SR_RXRDY) { 187 *sc->sc_data++ = at91twi_readreg(sc, TWI_RHR); 188 sc->sc_resid--; 189 } 190 sc->sc_flags &= ~I2C_BUSY; 191 at91twi_writereg(sc, TWI_IDR, -1); 192 goto out; 193 } 194 195 if (isr & TWI_SR_TXRDY) { 196 if (--sc->sc_resid > 0) 197 at91twi_writereg(sc, TWI_THR, *sc->sc_data++); 198 } 199 200 if (isr & TWI_SR_RXRDY) { 201 // data has been received 202 *sc->sc_data++ = at91twi_readreg(sc, TWI_RHR); 203 sc->sc_resid--; 204 } 205 206 if (isr & (TWI_SR_TXRDY | TWI_SR_RXRDY) && sc->sc_resid <= 0) { 207 // all bytes have been transmitted, send stop condition 208 at91twi_writereg(sc, TWI_IDR, TWI_SR_RXRDY | TWI_SR_TXRDY); 209 at91twi_writereg(sc, TWI_CR, TWI_CR_STOP); 210 } 211 out: 212 return 1; 213 } 214 215 int 216 at91twi_poll(struct at91twi_softc *sc, int timo, int flags) 217 { 218 219 timo = 1000000U; 220 221 while (sc->sc_flags & I2C_BUSY) { 222 if (timo < 0) { 223 printf("i2c_poll: timeout\n"); 224 return -1; 225 } 226 if (flags & I2C_F_POLL) { 227 at91_intr_poll(sc->sc_ih, 1); 228 delay(1); 229 timo--; 230 } else { 231 delay(100); // @@@ sleep!? 232 timo -= 100; 233 } 234 } 235 return 0; 236 } 237 238 int 239 at91twi_start(struct at91twi_softc *sc, int addr, void *data, int len, 240 int flags) 241 { 242 int rd = (sc->sc_flags & I2C_READING); 243 int timo, s; 244 245 KASSERT((addr & 1) == 0); 246 247 sc->sc_data = data; 248 sc->sc_resid = len; 249 sc->sc_flags |= I2C_BUSY; 250 251 timo = 1000 + len * 200; 252 253 s = splserial(); 254 // if writing, queue first byte immediately 255 if (!rd) 256 at91twi_writereg(sc, TWI_THR, *sc->sc_data++); 257 // if there's just one byte to transmit, we must set STOP-bit too 258 if (sc->sc_resid == 1) { 259 at91twi_writereg(sc, TWI_IER, TWI_SR_TXCOMP); 260 at91twi_writereg(sc, TWI_CR, TWI_CR_START | TWI_CR_STOP); 261 } else { 262 at91twi_writereg(sc, TWI_IER, TWI_SR_TXCOMP 263 | (rd ? TWI_SR_RXRDY : TWI_SR_TXRDY)); 264 at91twi_writereg(sc, TWI_CR, TWI_CR_START); 265 } 266 splx(s); 267 268 if (at91twi_poll(sc, timo, flags)) 269 return -1; 270 if (sc->sc_flags & I2C_ERROR) { 271 printf("I2C_ERROR\n"); 272 return -1; 273 } 274 return 0; 275 } 276 277 int 278 at91twi_read(struct at91twi_softc *sc, int addr, void *data, int len, int flags) 279 { 280 sc->sc_flags = I2C_READING; 281 #ifdef AT91TWI_DEBUG 282 printf("at91twi_read: %02x %d\n", addr, len); 283 #endif 284 return at91twi_start(sc, addr, data, len, flags); 285 } 286 287 int 288 at91twi_write(struct at91twi_softc *sc, int addr, void *data, int len, int flags) 289 { 290 sc->sc_flags = 0; 291 #ifdef AT91TWI_DEBUG 292 printf("at91twi_write: %02x %d\n", addr, len); 293 #endif 294 return at91twi_start(sc, addr, data, len, flags); 295 } 296 297 static int 298 at91twi_i2c_acquire_bus(void *cookie, int flags) 299 { 300 struct at91twi_softc *sc = cookie; 301 302 if (flags & I2C_F_POLL) 303 return 0; 304 305 mutex_enter(&sc->sc_buslock); 306 return 0; 307 } 308 309 static void 310 at91twi_i2c_release_bus(void *cookie, int flags) 311 { 312 struct at91twi_softc *sc = cookie; 313 314 if (flags & I2C_F_POLL) 315 return; 316 317 mutex_exit(&sc->sc_buslock); 318 } 319 320 int 321 at91twi_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *vcmd, 322 size_t cmdlen, void *vbuf, size_t buflen, int flags) 323 { 324 struct at91twi_softc *sc = cookie; 325 326 if (I2C_OP_READ_P(op)) 327 { 328 u_int iadr = 0; 329 if (vcmd) { 330 const uint8_t *cmd = (const uint8_t *)vcmd; 331 if (cmdlen > 3) { 332 // we're in trouble.. 333 return -1; 334 } 335 iadr = cmd[0]; 336 if (cmdlen > 1) { 337 iadr <<= 8; 338 iadr |= cmd[1]; 339 } 340 if (cmdlen > 2) { 341 iadr <<= 8; 342 iadr |= cmd[2]; 343 } 344 } 345 at91twi_writereg(sc, TWI_MMR, (addr << 16) | TWI_MMR_MREAD | (cmdlen << 8)); 346 if (cmdlen > 0) { 347 #ifdef AT91TWI_DEBUG 348 printf("at91twi_read: %02x iadr=%08X mmr=%08X\n", 349 addr, iadr, at91twi_readreg(sc, TWI_MMR)); 350 #endif 351 at91twi_writereg(sc, TWI_IADR, iadr); 352 } 353 if (at91twi_read(sc, addr, vbuf, buflen, flags) != 0) 354 return -1; 355 } else if (vcmd) { 356 at91twi_writereg(sc, TWI_MMR, addr << 16); 357 if (at91twi_write(sc, addr, __UNCONST(vcmd), cmdlen, flags) !=0) 358 return -1; 359 } 360 return 0; 361 } 362