1 /*$NetBSD: at91tctmr.c,v 1.4 2010/06/19 19:47:34 matt Exp $*/ 2 3 /* 4 * AT91 Timer Counter (TC) based clock functions 5 * Copyright (c) 2007, Embedtronics Oy 6 * All rights reserved. 7 * 8 * Based on vx115_clk.c, 9 * Copyright (c) 2006, Jon Sevy <jsevy@cs.drexel.edu> 10 * 11 * Based on epclk.c 12 * Copyright (c) 2004 Jesse Off 13 * All rights reserved. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Driver for the AT91RM9200 clock tick. 39 * We use Timer 1 for the system clock 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: at91tctmr.c,v 1.4 2010/06/19 19:47:34 matt Exp $"); 44 45 #include <sys/types.h> 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/time.h> 50 #include <sys/timetc.h> 51 #include <sys/device.h> 52 53 #include <dev/clock_subr.h> 54 55 #include <machine/bus.h> 56 #include <machine/intr.h> 57 58 #include <arm/cpufunc.h> 59 #include <arm/at91/at91reg.h> 60 #include <arm/at91/at91var.h> 61 #include <arm/at91/at91tcreg.h> 62 63 #include <opt_hz.h> /* for HZ */ 64 65 66 #define DEBUG_CLK 67 #ifdef DEBUG_CLK 68 #define DPRINTF(fmt...) printf(fmt) 69 #else 70 #define DPRINTF(fmt...) 71 #endif 72 73 74 static int at91tctmr_match(device_t, cfdata_t, void *); 75 static void at91tctmr_attach(device_t, device_t, void *); 76 77 void rtcinit(void); 78 79 /* callback functions for intr_functions */ 80 static int at91tctmr_intr(void* arg); 81 82 struct at91tctmr_softc { 83 device_t sc_dev; 84 u_char *sc_addr; 85 int sc_pid; 86 int sc_initialized; 87 uint32_t sc_timerclock; 88 uint32_t sc_divider; 89 uint32_t sc_usec_per_tick; 90 }; 91 92 static struct at91tctmr_softc *at91tctmr_sc = NULL; 93 static struct timeval lasttv; 94 95 96 97 /* Match value for clock timer; running at master clock, want HZ ticks per second */ 98 /* NOTE: don't change there without visiting the functions below which */ 99 /* convert between timer counts and microseconds */ 100 101 static inline uint32_t 102 at91tctmr_count_to_usec(struct at91tctmr_softc *sc, uint32_t count) 103 { 104 uint64_t tmp; 105 106 tmp = count; 107 tmp *= 1000000U; 108 109 return (tmp / sc->sc_timerclock); 110 } 111 112 #if 0 113 /* This may only be called when overflow is avoided; typically, */ 114 /* it will be used when usec < USEC_PER_TICK */ 115 static uint32_t 116 usec_to_timer_count(uint32_t usec) 117 { 118 uint32_t result; 119 120 /* convert specified number of usec to timer ticks, and round up */ 121 result = (AT91_SCLK * usec) / 1000000; 122 123 if ((result * 1000000) != (usec * AT91_SCLK)) 124 { 125 /* round up */ 126 result += 1; 127 } 128 129 return result; 130 131 } 132 #endif 133 134 /* macros to simplify writing to the timer controller */ 135 static inline u_int32_t 136 READ_TC(struct at91tctmr_softc *sc, uint offset) 137 { 138 volatile u_int32_t *addr = (void*)(sc->sc_addr + offset); 139 return *addr; 140 } 141 142 //bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset) 143 static inline void 144 WRITE_TC(struct at91tctmr_softc *sc, uint offset, u_int32_t value) 145 { 146 volatile u_int32_t *addr = (void*)(sc->sc_addr + offset); 147 *addr = value; 148 } 149 150 151 CFATTACH_DECL_NEW(at91tctmr, sizeof(struct at91tctmr_softc), 152 at91tctmr_match, at91tctmr_attach, NULL, NULL); 153 154 static u_int at91tctmr_get_timecount(struct timecounter *); 155 156 static struct timecounter at91tctmr_timecounter = { 157 at91tctmr_get_timecount,/* get_timecount */ 158 0, /* no poll_pps */ 159 0xffffffff, /* counter_mask */ 160 COUNTS_PER_SEC, /* frequency */ 161 "at91tctmr", /* name */ 162 100, /* quality */ 163 NULL, /* prev */ 164 NULL, /* next */ 165 }; 166 167 static int 168 at91tctmr_match(device_t parent, cfdata_t match, void *aux) 169 { 170 if (strcmp(match->cf_name, "at91tctmr") == 0) 171 return 2; 172 return 0; 173 } 174 175 static void 176 at91tctmr_attach(device_t parent, device_t self, void *aux) 177 { 178 struct at91tctmr_softc *sc = device_private(self); 179 struct at91bus_attach_args *sa = aux; 180 181 aprint_normal("\n"); 182 183 sc->sc_dev = self; 184 sc->sc_addr = (void*)sa->sa_addr; 185 sc->sc_pid = sa->sa_pid; 186 187 if (at91tctmr_sc == NULL) 188 at91tctmr_sc = sc; 189 190 at91_peripheral_clock(sc->sc_pid, 1); 191 192 WRITE_TC(sc, TC_CCR, TC_CCR_CLKDIS); 193 WRITE_TC(sc, TC_IDR, -1); /* make sure interrupts are disabled */ 194 195 /* find divider */ 196 u_int32_t cmr = 0; 197 if (AT91_MSTCLK / 2U / HZ <= 65536) { 198 sc->sc_timerclock = AT91_MSTCLK / 2U; 199 cmr = TC_CMR_TCCLKS_MCK_DIV_2; 200 } else if (AT91_MSTCLK / 8U / HZ <= 65536) { 201 sc->sc_timerclock = AT91_MSTCLK / 8U; 202 cmr = TC_CMR_TCCLKS_MCK_DIV_8; 203 } else if (AT91_MSTCLK / 32U / HZ <= 65536) { 204 sc->sc_timerclock = AT91_MSTCLK / 32U; 205 cmr = TC_CMR_TCCLKS_MCK_DIV_32; 206 } else if (AT91_MSTCLK / 128U / HZ <= 65536) { 207 sc->sc_timerclock = AT91_MSTCLK / 128U; 208 cmr = TC_CMR_TCCLKS_MCK_DIV_128; 209 } else 210 panic("%s: cannot setup timer to reach HZ", device_xname(sc->sc_dev)); 211 212 sc->sc_divider = (sc->sc_timerclock + HZ - 1) / HZ; /* round up */ 213 sc->sc_usec_per_tick = 1000000UL / (sc->sc_timerclock / sc->sc_divider); 214 215 WRITE_TC(sc, TC_CMR, TC_CMR_WAVE | cmr | TC_CMR_WAVSEL_UP_RC); 216 WRITE_TC(sc, TC_CCR, TC_CCR_CLKEN); 217 WRITE_TC(sc, TC_RC, sc->sc_divider - 1); 218 WRITE_TC(sc, TC_CCR, TC_CCR_SWTRG); 219 220 sc->sc_initialized = 1; 221 222 DPRINTF("%s: done, tclock=%"PRIu32" div=%"PRIu32" uspertick=%"PRIu32"\n", __FUNCTION__, sc->sc_timerclock, sc->sc_divider, sc->sc_usec_per_tick); 223 224 } 225 226 /* 227 * at91tctmr_intr: 228 * 229 *Handle the hardclock interrupt. 230 */ 231 static int 232 at91tctmr_intr(void *arg) 233 { 234 struct at91tctmr_softc *sc = arg; 235 236 /* make sure it's the kernel timer that generated the interrupt */ 237 /* need to do this since the interrupt line is shared by the */ 238 /* other interval and PWM timers */ 239 if (READ_TC(sc, TC_SR) & TC_SR_CPCS) { 240 /* call the kernel timer handler */ 241 hardclock((struct clockframe*) arg); 242 return 1; 243 } else { 244 /* it's one of the other timers; just pass it on */ 245 return 0; 246 } 247 } 248 249 /* 250 * setstatclockrate: 251 * 252 *Set the rate of the statistics clock. 253 * 254 *We assume that hz is either stathz or profhz, and that neither 255 *will change after being set by cpu_initclocks(). We could 256 *recalculate the intervals here, but that would be a pain. 257 */ 258 void 259 setstatclockrate(int hzz) 260 { 261 /* use hardclock */ 262 (void)hzz; 263 } 264 265 /* 266 * cpu_initclocks: 267 * 268 *Initialize the clock and get it going. 269 */ 270 static void udelay(unsigned int usec); 271 272 void 273 cpu_initclocks(void) 274 { 275 struct at91tctmr_softc *sc = at91tctmr_sc; 276 277 if (!sc || !sc->sc_initialized) 278 panic("%s: driver has not been initialized! (sc=%p)", __FUNCTION__, sc); 279 280 hz = sc->sc_timerclock / sc->sc_divider; 281 stathz = profhz = 0; 282 283 /* set up and enable interval timer 1 as kernel timer, */ 284 /* using 32kHz clock source */ 285 286 /* register interrupt handler */ 287 at91_intr_establish(sc->sc_pid, IPL_CLOCK, INTR_HIGH_LEVEL, at91tctmr_intr, sc); 288 289 /* enable interrupts from timer */ 290 WRITE_TC(sc, TC_IER, TC_SR_CPCS); 291 } 292 293 294 295 296 static void udelay(unsigned int usec) 297 { 298 struct at91tctmr_softc *sc = at91tctmr_sc; 299 u_int32_t prev_cvr, cvr, divi = READ_TC(sc, TC_RC), diff; 300 int prev_ticks, ticks, ticks2; 301 unsigned footick = (sc->sc_timerclock * 64ULL / 1000000UL); 302 303 if (usec > 0) { 304 prev_ticks = hardclock_ticks; 305 __insn_barrier(); 306 prev_cvr = READ_TC(sc, TC_CV); 307 ticks = hardclock_ticks; 308 __insn_barrier(); 309 if (ticks != prev_ticks) { 310 prev_cvr = READ_TC(sc, TC_CV); 311 prev_ticks = ticks; 312 } 313 for (;;) { 314 ticks = hardclock_ticks; 315 __insn_barrier(); 316 cvr = READ_TC(sc, TC_CV); 317 ticks2 = hardclock_ticks; 318 __insn_barrier(); 319 if (ticks2 != ticks) { 320 cvr = READ_TC(sc, TC_CV); 321 } 322 diff = (ticks2 - prev_ticks) * divi; 323 if (cvr < prev_cvr) { 324 if (!diff) 325 diff = divi; 326 diff -= prev_cvr - cvr; 327 } else 328 diff += cvr - prev_cvr; 329 diff = diff * 64 / footick; 330 if (diff) { 331 if (usec <= diff) 332 break; 333 prev_ticks = ticks2; 334 prev_cvr = (prev_cvr + footick * diff / 64) % divi; 335 usec -= diff; 336 } 337 } 338 } 339 } 340 341 342 343 /* 344 * delay: 345 * 346 *Delay for at least N microseconds. Note that due to our coarse clock, 347 * our resolution is 61 us. But we round up so we'll wait at least as 348 * long as requested. 349 */ 350 void 351 delay(unsigned int usec) 352 { 353 struct at91tctmr_softc *sc = at91tctmr_sc; 354 355 #ifdef DEBUG 356 if (sc == NULL) { 357 printf("delay: called before start at91tc\n"); 358 return; 359 } 360 #endif 361 362 if (usec >= sc->sc_usec_per_tick) { 363 /* have more than 1 tick; just do in ticks */ 364 unsigned int ticks = (usec + sc->sc_usec_per_tick - 1) / sc->sc_usec_per_tick; 365 while (ticks-- > 0) { 366 udelay(sc->sc_usec_per_tick); 367 } 368 } else { 369 /* less than 1 tick; can do as usec */ 370 udelay(usec); 371 } 372 373 } 374 375