xref: /netbsd-src/sys/arch/arm/at91/at91pio.c (revision 6a493d6bc668897c91594964a732d38505b70cbb) 
1 /*	$Id: at91pio.c,v 1.6 2012/11/12 18:00:36 skrll Exp $	*/
2 /*	$NetBSD: at91pio.c,v 1.6 2012/11/12 18:00:36 skrll Exp $	*/
3 
4 /*
5  * Copyright (c) 2007 Embedtronics Oy. All rights reserved.
6  *
7  * Based on arch/arm/ep93xx/epgpio.c,
8  * Copyright (c) 2005 HAMAJIMA Katsuomi. All rights reserved.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29  * SUCH DAMAGE.
30  */
31 
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: at91pio.c,v 1.6 2012/11/12 18:00:36 skrll Exp $");
34 
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/device.h>
39 #include <sys/gpio.h>
40 #include <sys/bus.h>
41 #include <machine/intr.h>
42 #include <dev/gpio/gpiovar.h>
43 #include <arm/at91/at91var.h>
44 #include <arm/at91/at91reg.h>
45 #include <arm/at91/at91pioreg.h>
46 #include <arm/at91/at91piovar.h>
47 #include "gpio.h"
48 #if NGPIO > 0
49 #include <sys/gpio.h>
50 #endif
51 #include "locators.h"
52 
53 #ifdef AT91PIO_DEBUG
54 int at91pio_debug = AT91PIO_DEBUG;
55 #define DPRINTFN(n,x)	if (at91pio_debug>(n)) printf x;
56 #else
57 #define DPRINTFN(n,x)
58 #endif
59 
60 #define	AT91PIO_NMAXPORTS	4
61 #define	AT91PIO_NPINS		32
62 
63 struct intr_req {
64 	int			(*ireq_func)(void *);
65 	void			*ireq_arg;
66 	int			ireq_ipl;
67 };
68 
69 #define	PIO_READ(_sc, _reg)		bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_reg))
70 #define	PIO_WRITE(_sc, _reg, _val)	bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_reg), (_val))
71 
72 struct at91pio_softc {
73 	bus_space_tag_t		sc_iot;
74 	bus_space_handle_t	sc_ioh;
75 	int			sc_pid;
76 #if NGPIO > 0
77 	struct gpio_chipset_tag	gpio_chipset;
78 	gpio_pin_t		pins[AT91PIO_NPINS];
79 #endif
80 	int			irq;
81 	void			*ih;
82 	struct intr_req		ireq[AT91PIO_NPINS];
83 };
84 
85 static int at91pio_match(device_t, cfdata_t, void *);
86 static void at91pio_attach(device_t, device_t, void *);
87 
88 #if NGPIO > 0
89 static int at91piobus_print(void *, const char *);
90 static int at91pio_pin_read(void *, int);
91 static void at91pio_pin_write(void *, int, int);
92 static void at91pio_pin_ctl(void *, int, int);
93 #endif
94 
95 static int at91pio_search(device_t, cfdata_t, const int *, void *);
96 static int at91pio_print(void *, const char *);
97 
98 static int at91pio_intr(void* arg);
99 
100 CFATTACH_DECL_NEW(at91pio, sizeof(struct at91pio_softc),
101 	      at91pio_match, at91pio_attach, NULL, NULL);
102 
103 static struct at91pio_softc *at91pio_softc[AT91_PIO_COUNT];
104 
105 struct at91pio_softc *at91pio_sc(at91pio_port port)
106 {
107 	if (port < AT91_PIO_COUNT)
108 		return at91pio_softc[port];
109 	return NULL;
110 }
111 
112 
113 static int
114 at91pio_match(device_t parent, cfdata_t match, void *aux)
115 {
116 	if (strcmp(match->cf_name, "at91pio") == 0)
117 		return 2;
118 	return 0;
119 }
120 
121 static void
122 at91pio_attach(device_t parent, device_t self, void *aux)
123 {
124 	struct at91pio_softc *sc = device_private(self);
125 	struct at91bus_attach_args *sa = aux;
126 #if NGPIO > 0
127 	struct gpiobus_attach_args gba;
128 	uint32_t psr, osr, pin;
129 	int j, n;
130 #endif
131 	printf("\n");
132 	sc->sc_iot = sa->sa_iot;
133 	sc->sc_pid = sa->sa_pid;
134 
135 	if (bus_space_map(sa->sa_iot, sa->sa_addr,
136 			  sa->sa_size, 0, &sc->sc_ioh)){
137 		printf("%s: Cannot map registers", device_xname(self));
138 		return;
139 	}
140 
141 	/* save descriptor: */
142 	at91pio_port p = at91_pio_port(sa->sa_pid);
143 	if (p < AT91_PIO_COUNT && !at91pio_softc[p])
144 		at91pio_softc[p] = sc;
145 
146 	/* make sure peripheral is enabled: */
147 	at91_peripheral_clock(sc->sc_pid, 1);
148 
149 	/* initialize ports (disable interrupts) */
150 	PIO_WRITE(sc, PIO_IDR, -1);
151 
152 #if NGPIO > 0
153 	/* initialize and attach gpio(4) */
154 	psr = PIO_READ(sc, PIO_PSR);	// only ports
155 	osr = PIO_READ(sc, PIO_OSR);
156 	pin = PIO_READ(sc, PIO_PDSR);
157 	psr &= ~at91_gpio_mask(sc->sc_pid);
158 	for (j = n = 0; j < AT91PIO_NPINS; j++) {
159 		sc->pins[n].pin_num = j;
160 		if (psr & (1 << j))
161 			sc->pins[n].pin_caps = (GPIO_PIN_INPUT
162 						| GPIO_PIN_OUTPUT
163 						| GPIO_PIN_OPENDRAIN // @@@ not all pins
164 						| GPIO_PIN_PUSHPULL
165 						| GPIO_PIN_PULLUP);
166 		else
167 			sc->pins[n].pin_caps = 0;
168 
169 		if (osr & (1 << j))
170 			sc->pins[n].pin_flags = GPIO_PIN_OUTPUT;
171 		else
172 			sc->pins[n].pin_flags = GPIO_PIN_INPUT;
173 		if (pin & (1 << j))
174 			sc->pins[n].pin_state = GPIO_PIN_HIGH;
175 		else
176 			sc->pins[n].pin_state = GPIO_PIN_LOW;
177 		n++;
178 	}
179 	sc->gpio_chipset.gp_cookie = sc;
180 	sc->gpio_chipset.gp_pin_read = at91pio_pin_read;
181 	sc->gpio_chipset.gp_pin_write = at91pio_pin_write;
182 	sc->gpio_chipset.gp_pin_ctl = at91pio_pin_ctl;
183 	gba.gba_gc = &sc->gpio_chipset;
184 	gba.gba_pins = sc->pins;
185 	gba.gba_npins = n;
186 	config_found_ia(self, "gpiobus", &gba, at91piobus_print);
187 #endif
188 
189 	/* attach device */
190 	config_search_ia(at91pio_search, self, "at91pio", at91pio_print);
191 }
192 
193 #if NGPIO > 0
194 static int
195 at91piobus_print(void *aux, const char *name)
196 {
197 	struct gpiobus_attach_args *gba = aux;
198 	struct at91pio_softc *sc = (struct at91pio_softc *)gba->gba_gc->gp_cookie;
199 
200 	gpiobus_print(aux, name);
201 	aprint_normal(": port %s (mask %08"PRIX32")",
202 		      at91_peripheral_name(sc->sc_pid),
203 		      at91_gpio_mask(sc->sc_pid));
204 
205 	return (UNCONF);
206 }
207 #endif
208 
209 
210 static int
211 at91pio_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
212 {
213 	struct at91pio_softc *sc = device_private(parent);
214 	struct at91pio_attach_args paa;
215 
216 	paa.paa_sc = sc;
217 	paa.paa_iot = sc->sc_iot;
218 	paa.paa_pid = cf->cf_loc[AT91PIOCF_PID];
219 	paa.paa_bit = cf->cf_loc[AT91PIOCF_BIT];
220 
221 	if (config_match(parent, cf, &paa) > 0)
222 		config_attach(parent, cf, &paa, at91pio_print);
223 
224 	return 0;
225 }
226 
227 static int
228 at91pio_print(void *aux, const char *name)
229 {
230 	struct at91pio_attach_args *paa = aux;
231 
232 	aprint_normal(":");
233 	if (paa->paa_pid > -1)
234 		aprint_normal(" port %s", at91_peripheral_name(paa->paa_pid));
235 	if (paa->paa_bit > -1)
236 		aprint_normal(" bit %d", paa->paa_bit);
237 
238 	return (UNCONF);
239 }
240 
241 int
242 at91pio_read(struct at91pio_softc *sc, int bit)
243 {
244 #if NGPIO > 0
245 	sc->pins[bit].pin_caps = 0;
246 #endif
247 	return (PIO_READ(sc, PIO_PDSR) >> bit) & 1;
248 }
249 
250 void
251 at91pio_set(struct at91pio_softc *sc, int bit)
252 {
253 #if NGPIO > 0
254 	sc->pins[bit].pin_caps = 0;
255 #endif
256 	PIO_WRITE(sc, PIO_SODR, (1U << bit));
257 }
258 
259 void
260 at91pio_clear(struct at91pio_softc *sc, int bit)
261 {
262 #if NGPIO > 0
263 	sc->pins[bit].pin_caps = 0;
264 #endif
265 	PIO_WRITE(sc, PIO_CODR, (1U << bit));
266 }
267 
268 void
269 at91pio_in(struct at91pio_softc *sc, int bit)
270 {
271 #if NGPIO > 0
272 	sc->pins[bit].pin_caps = 0;
273 #endif
274 	PIO_WRITE(sc, PIO_ODR, (1U << bit));
275 }
276 
277 void
278 at91pio_out(struct at91pio_softc *sc, int bit)
279 {
280 #if NGPIO > 0
281 	sc->pins[bit].pin_caps = 0;
282 #endif
283 	PIO_WRITE(sc, PIO_OER, (1U << bit));
284 }
285 
286 void at91pio_per(struct at91pio_softc *sc, int bit, int perab)
287 {
288 #if NGPIO > 0
289 	sc->pins[bit].pin_caps = 0;
290 #endif
291 	switch (perab) {
292 	case -1:
293 		PIO_WRITE(sc, PIO_PER, (1U << bit));
294 		break;
295 	case 0:
296 		PIO_WRITE(sc, PIO_ASR, (1U << bit));
297 		PIO_WRITE(sc, PIO_PDR, (1U << bit));
298 		break;
299 	case 1:
300 		PIO_WRITE(sc, PIO_BSR, (1U << bit));
301 		PIO_WRITE(sc, PIO_PDR, (1U << bit));
302 		break;
303 	default:
304 		panic("%s: perab is invalid: %i", __FUNCTION__, perab);
305 		break;
306 	}
307 }
308 
309 void *
310 at91pio_intr_establish(struct at91pio_softc *sc, int bit,
311 			 int ipl, int (*ireq_func)(void *), void *arg)
312 {
313 	struct intr_req *ireq;
314 
315 	DPRINTFN(1, ("at91pio_intr_establish: port=%s, bit=%d\n", at91_peripheral_name(sc->sc_pid), bit));
316 
317 	if (bit < 0 || bit >= AT91PIO_NPINS)
318 		return 0;
319 
320 	ireq = &sc->ireq[bit];
321 
322 	if (ireq->ireq_func)	/* already used */
323 		return 0;
324 
325 	ireq->ireq_func = ireq_func;
326 	ireq->ireq_arg = arg;
327 	ireq->ireq_ipl = ipl;
328 
329 	PIO_WRITE(sc, PIO_IDR, (1U << bit));	/* disable interrupt for now */
330 	at91pio_in(sc, bit);			/* make sure pin is input */
331 #if NGPIO > 0
332 	sc->pins[bit].pin_caps = 0;
333 #endif
334 #if 0
335 	if (flag & EDGE_TRIGGER)
336 		at91pio_bit_set(sc, sc->xinttype1, bit);
337 	else	/* LEVEL_SENSE */
338 		at91pio_bit_clear(sc, sc->xinttype1, bit);
339 	if (flag & RISING_EDGE)	/* or HIGH_LEVEL */
340 		at91pio_bit_set(sc, sc->xinttype2, bit);
341 	else	/* FALLING_EDGE or LOW_LEVEL */
342 		at91pio_bit_clear(sc, sc->xinttype2, bit);
343 	if (flag & DEBOUNCE)
344 		PIO_WRITE(sc, PIO_IFER, (1U << bit));
345 	else
346 		PIO_WRITE(sc, PIO_IFDR, (1U << bit));
347 #endif
348 
349 	if (!sc->ih) {
350 		// use IPL_BIO because we want lowest possible priority as
351 		// we really don't know what priority is going to be used by
352 		// the caller.. this is not really optimal but tell me a
353 		// better way
354 		sc->ih = at91_intr_establish(sc->sc_pid, IPL_BIO, INTR_HIGH_LEVEL,
355 					      at91pio_intr, sc);
356 	}
357 
358 	//(void)PIO_READ(sc, PIO_ISR);	// clear interrupts
359 	PIO_WRITE(sc, PIO_IER, (1U << bit));	// enable interrupt
360 
361 	return sc->ih;
362 }
363 
364 void
365 at91pio_intr_disestablish(struct at91pio_softc *sc, int bit, void *cookie)
366 {
367 	struct intr_req *ireq;
368 	int i;
369 
370 	DPRINTFN(1, ("at91pio_intr_disestablish: port=%s, bit=%d\n", at91_peripheral_name(sc->sc_pid), bit));
371 
372 	if (bit < 0 || bit >= AT91PIO_NPINS)
373 		return;
374 
375 if (cookie != sc->ih)
376 		return;
377 
378 	ireq = &sc->ireq[bit];
379 
380 	if (!ireq->ireq_func)
381 		return;
382 
383 	PIO_WRITE(sc, PIO_IDR, (1U << bit));
384 	ireq->ireq_func = 0;
385 	ireq->ireq_arg = 0;
386 
387 	for (i = 0; i < AT91PIO_NPINS; i++) {
388 		if (sc->ireq[i].ireq_func)
389 			break;
390 	}
391 
392 	if (i >= AT91PIO_NPINS) {
393 		at91_intr_disestablish(sc->ih);
394 		sc->ih = 0;
395 	}
396 }
397 
398 static int
399 at91pio_intr(void *arg)
400 {
401 	struct at91pio_softc *sc = arg;
402 	int bit;
403 	uint32_t isr;
404 
405 	isr = (PIO_READ(sc, PIO_ISR) & PIO_READ(sc, PIO_IMR));
406 	if (!isr)
407 		return 0;
408 
409 	do {
410 		bit = ffs(isr) - 1;
411 		isr &= ~(1U << bit);
412 #ifdef	DIAGNOSTIC
413 		if (bit < 0)
414 			panic("%s: isr is zero (0x%X)", __FUNCTION__, isr);
415 #endif
416 		if (sc->ireq[bit].ireq_func) {
417 			int s = _splraise(sc->ireq[bit].ireq_ipl);
418 			(*sc->ireq[bit].ireq_func)(sc->ireq[bit].ireq_arg);
419 			splx(s);
420 		}
421 	} while (isr);
422 
423 	return 1;
424 }
425 
426 
427 #if NGPIO > 0
428 static int
429 at91pio_pin_read(void *arg, int pin)
430 {
431 	struct at91pio_softc *sc = arg;
432 
433 	pin %= AT91PIO_NPINS;
434 	if (!sc->pins[pin].pin_caps)
435 		return 0; /* EBUSY? */
436 
437 	return (PIO_READ(sc, PIO_PDSR) >> pin) & 1;
438 }
439 
440 static void
441 at91pio_pin_write(void *arg, int pin, int val)
442 {
443 	struct at91pio_softc *sc = arg;
444 
445 	pin %= AT91PIO_NPINS;
446 	if (!sc->pins[pin].pin_caps)
447 		return;
448 
449 	if (val)
450 		PIO_WRITE(sc, PIO_SODR, (1U << pin));
451 	else
452 		PIO_WRITE(sc, PIO_CODR, (1U << pin));
453 }
454 
455 static void
456 at91pio_pin_ctl(void *arg, int pin, int flags)
457 {
458 	struct at91pio_softc *sc = arg;
459 
460 	pin %= AT91PIO_NPINS;
461 	if (!sc->pins[pin].pin_caps)
462 		return;
463 
464 	if (flags & GPIO_PIN_INPUT)
465 		PIO_WRITE(sc, PIO_ODR, (1U << pin));
466 	else if (flags & GPIO_PIN_OUTPUT)
467 		PIO_WRITE(sc, PIO_OER, (1U << pin));
468 
469 	if (flags & GPIO_PIN_OPENDRAIN)
470 		PIO_WRITE(sc, PIO_MDER, (1U << pin));
471 	else if (flags & GPIO_PIN_PUSHPULL)
472 		PIO_WRITE(sc, PIO_MDDR, (1U << pin));
473 
474 	if (flags & GPIO_PIN_PULLUP)
475 		PIO_WRITE(sc, PIO_PUER, (1U << pin));
476 	else
477 		PIO_WRITE(sc, PIO_PUDR, (1U << pin));
478 }
479 #endif
480 
481