1 /* $NetBSD: pmap.c,v 1.137 2003/06/23 11:01:07 martin Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 3. All advertising materials mentioning features or use of this software 82 * must display the following acknowledgement: 83 * This product includes software developed by the NetBSD 84 * Foundation, Inc. and its contributors. 85 * 4. Neither the name of The NetBSD Foundation nor the names of its 86 * contributors may be used to endorse or promote products derived 87 * from this software without specific prior written permission. 88 * 89 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 90 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 91 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 92 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 93 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 94 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 95 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 96 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 97 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 98 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 99 * POSSIBILITY OF SUCH DAMAGE. 100 */ 101 102 /* 103 * Copyright (c) 1994-1998 Mark Brinicombe. 104 * Copyright (c) 1994 Brini. 105 * All rights reserved. 106 * 107 * This code is derived from software written for Brini by Mark Brinicombe 108 * 109 * Redistribution and use in source and binary forms, with or without 110 * modification, are permitted provided that the following conditions 111 * are met: 112 * 1. Redistributions of source code must retain the above copyright 113 * notice, this list of conditions and the following disclaimer. 114 * 2. Redistributions in binary form must reproduce the above copyright 115 * notice, this list of conditions and the following disclaimer in the 116 * documentation and/or other materials provided with the distribution. 117 * 3. All advertising materials mentioning features or use of this software 118 * must display the following acknowledgement: 119 * This product includes software developed by Mark Brinicombe. 120 * 4. The name of the author may not be used to endorse or promote products 121 * derived from this software without specific prior written permission. 122 * 123 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 124 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 125 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 126 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 127 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 128 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 129 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 130 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 131 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 132 * 133 * RiscBSD kernel project 134 * 135 * pmap.c 136 * 137 * Machine dependant vm stuff 138 * 139 * Created : 20/09/94 140 */ 141 142 /* 143 * Performance improvements, UVM changes, overhauls and part-rewrites 144 * were contributed by Neil A. Carson <neil@causality.com>. 145 */ 146 147 /* 148 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 149 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 150 * Systems, Inc. 151 * 152 * There are still a few things outstanding at this time: 153 * 154 * - There are some unresolved issues for MP systems: 155 * 156 * o The L1 metadata needs a lock, or more specifically, some places 157 * need to acquire an exclusive lock when modifying L1 translation 158 * table entries. 159 * 160 * o When one cpu modifies an L1 entry, and that L1 table is also 161 * being used by another cpu, then the latter will need to be told 162 * that a tlb invalidation may be necessary. (But only if the old 163 * domain number in the L1 entry being over-written is currently 164 * the active domain on that cpu). I guess there are lots more tlb 165 * shootdown issues too... 166 * 167 * o If the vector_page is at 0x00000000 instead of 0xffff0000, then 168 * MP systems will lose big-time because of the MMU domain hack. 169 * The only way this can be solved (apart from moving the vector 170 * page to 0xffff0000) is to reserve the first 1MB of user address 171 * space for kernel use only. This would require re-linking all 172 * applications so that the text section starts above this 1MB 173 * boundary. 174 * 175 * o Tracking which VM space is resident in the cache/tlb has not yet 176 * been implemented for MP systems. 177 * 178 * o Finally, there is a pathological condition where two cpus running 179 * two separate processes (not lwps) which happen to share an L1 180 * can get into a fight over one or more L1 entries. This will result 181 * in a significant slow-down if both processes are in tight loops. 182 */ 183 184 /* 185 * Special compilation symbols 186 * PMAP_DEBUG - Build in pmap_debug_level code 187 */ 188 189 /* Include header files */ 190 191 #include "opt_cpuoptions.h" 192 #include "opt_pmap_debug.h" 193 #include "opt_ddb.h" 194 #include "opt_lockdebug.h" 195 #include "opt_multiprocessor.h" 196 197 #include <sys/types.h> 198 #include <sys/param.h> 199 #include <sys/kernel.h> 200 #include <sys/systm.h> 201 #include <sys/proc.h> 202 #include <sys/malloc.h> 203 #include <sys/user.h> 204 #include <sys/pool.h> 205 #include <sys/cdefs.h> 206 207 #include <uvm/uvm.h> 208 209 #include <machine/bus.h> 210 #include <machine/pmap.h> 211 #include <machine/pcb.h> 212 #include <machine/param.h> 213 #include <arm/arm32/katelib.h> 214 215 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.137 2003/06/23 11:01:07 martin Exp $"); 216 217 #ifdef PMAP_DEBUG 218 #define PDEBUG(_lev_,_stat_) \ 219 if (pmap_debug_level >= (_lev_)) \ 220 ((_stat_)) 221 int pmap_debug_level = 0; 222 223 /* 224 * for switching to potentially finer grained debugging 225 */ 226 #define PDB_FOLLOW 0x0001 227 #define PDB_INIT 0x0002 228 #define PDB_ENTER 0x0004 229 #define PDB_REMOVE 0x0008 230 #define PDB_CREATE 0x0010 231 #define PDB_PTPAGE 0x0020 232 #define PDB_GROWKERN 0x0040 233 #define PDB_BITS 0x0080 234 #define PDB_COLLECT 0x0100 235 #define PDB_PROTECT 0x0200 236 #define PDB_MAP_L1 0x0400 237 #define PDB_BOOTSTRAP 0x1000 238 #define PDB_PARANOIA 0x2000 239 #define PDB_WIRING 0x4000 240 #define PDB_PVDUMP 0x8000 241 #define PDB_VAC 0x10000 242 #define PDB_KENTER 0x20000 243 #define PDB_KREMOVE 0x40000 244 245 int debugmap = 1; 246 int pmapdebug = 0; 247 #define NPDEBUG(_lev_,_stat_) \ 248 if (pmapdebug & (_lev_)) \ 249 ((_stat_)) 250 251 #else /* PMAP_DEBUG */ 252 #define PDEBUG(_lev_,_stat_) /* Nothing */ 253 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 254 #endif /* PMAP_DEBUG */ 255 256 /* 257 * pmap_kernel() points here 258 */ 259 struct pmap kernel_pmap_store; 260 261 /* 262 * Which pmap is currently 'live' in the cache 263 * 264 * XXXSCW: Fix for SMP ... 265 */ 266 union pmap_cache_state *pmap_cache_state; 267 268 /* 269 * Pool and cache that pmap structures are allocated from. 270 * We use a cache to avoid clearing the pm_l2[] array (1KB) 271 * in pmap_create(). 272 */ 273 static struct pool pmap_pmap_pool; 274 static struct pool_cache pmap_pmap_cache; 275 static LIST_HEAD(, pmap) pmap_pmaps; 276 277 /* 278 * Pool of PV structures 279 */ 280 static struct pool pmap_pv_pool; 281 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 282 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 283 static struct pool_allocator pmap_bootstrap_pv_allocator = { 284 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 285 }; 286 287 /* 288 * Pool and cache of l2_dtable structures. 289 * We use a cache to avoid clearing the structures when they're 290 * allocated. (196 bytes) 291 */ 292 static struct pool pmap_l2dtable_pool; 293 static struct pool_cache pmap_l2dtable_cache; 294 static vaddr_t pmap_kernel_l2dtable_kva; 295 296 /* 297 * Pool and cache of L2 page descriptors. 298 * We use a cache to avoid clearing the descriptor table 299 * when they're allocated. (1KB) 300 */ 301 static struct pool pmap_l2ptp_pool; 302 static struct pool_cache pmap_l2ptp_cache; 303 static vaddr_t pmap_kernel_l2ptp_kva; 304 static paddr_t pmap_kernel_l2ptp_phys; 305 306 /* 307 * pmap copy/zero page, and mem(5) hook point 308 */ 309 static pt_entry_t *csrc_pte, *cdst_pte; 310 static vaddr_t csrcp, cdstp; 311 char *memhook; 312 extern caddr_t msgbufaddr; 313 314 /* 315 * Flag to indicate if pmap_init() has done its thing 316 */ 317 boolean_t pmap_initialized; 318 319 /* 320 * Misc. locking data structures 321 */ 322 323 #if defined(MULTIPROCESSOR) || defined(LOCKDEBUG) 324 static struct lock pmap_main_lock; 325 326 #define PMAP_MAP_TO_HEAD_LOCK() \ 327 (void) spinlockmgr(&pmap_main_lock, LK_SHARED, NULL) 328 #define PMAP_MAP_TO_HEAD_UNLOCK() \ 329 (void) spinlockmgr(&pmap_main_lock, LK_RELEASE, NULL) 330 #define PMAP_HEAD_TO_MAP_LOCK() \ 331 (void) spinlockmgr(&pmap_main_lock, LK_EXCLUSIVE, NULL) 332 #define PMAP_HEAD_TO_MAP_UNLOCK() \ 333 spinlockmgr(&pmap_main_lock, LK_RELEASE, (void *) 0) 334 #else 335 #define PMAP_MAP_TO_HEAD_LOCK() /* null */ 336 #define PMAP_MAP_TO_HEAD_UNLOCK() /* null */ 337 #define PMAP_HEAD_TO_MAP_LOCK() /* null */ 338 #define PMAP_HEAD_TO_MAP_UNLOCK() /* null */ 339 #endif 340 341 #define pmap_acquire_pmap_lock(pm) \ 342 do { \ 343 if ((pm) != pmap_kernel()) \ 344 simple_lock(&(pm)->pm_lock); \ 345 } while (/*CONSTCOND*/0) 346 347 #define pmap_release_pmap_lock(pm) \ 348 do { \ 349 if ((pm) != pmap_kernel()) \ 350 simple_unlock(&(pm)->pm_lock); \ 351 } while (/*CONSTCOND*/0) 352 353 354 /* 355 * Metadata for L1 translation tables. 356 */ 357 struct l1_ttable { 358 /* Entry on the L1 Table list */ 359 SLIST_ENTRY(l1_ttable) l1_link; 360 361 /* Entry on the L1 Least Recently Used list */ 362 TAILQ_ENTRY(l1_ttable) l1_lru; 363 364 /* Track how many domains are allocated from this L1 */ 365 volatile u_int l1_domain_use_count; 366 367 /* 368 * A free-list of domain numbers for this L1. 369 * We avoid using ffs() and a bitmap to track domains since ffs() 370 * is slow on ARM. 371 */ 372 u_int8_t l1_domain_first; 373 u_int8_t l1_domain_free[PMAP_DOMAINS]; 374 375 /* Physical address of this L1 page table */ 376 paddr_t l1_physaddr; 377 378 /* KVA of this L1 page table */ 379 pd_entry_t *l1_kva; 380 }; 381 382 /* 383 * Convert a virtual address into its L1 table index. That is, the 384 * index used to locate the L2 descriptor table pointer in an L1 table. 385 * This is basically used to index l1->l1_kva[]. 386 * 387 * Each L2 descriptor table represents 1MB of VA space. 388 */ 389 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 390 391 /* 392 * L1 Page Tables are tracked using a Least Recently Used list. 393 * - New L1s are allocated from the HEAD. 394 * - Freed L1s are added to the TAIl. 395 * - Recently accessed L1s (where an 'access' is some change to one of 396 * the userland pmaps which owns this L1) are moved to the TAIL. 397 */ 398 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 399 static struct simplelock l1_lru_lock; 400 401 /* 402 * A list of all L1 tables 403 */ 404 static SLIST_HEAD(, l1_ttable) l1_list; 405 406 /* 407 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 408 * 409 * This is normally 16MB worth L2 page descriptors for any given pmap. 410 * Reference counts are maintained for L2 descriptors so they can be 411 * freed when empty. 412 */ 413 struct l2_dtable { 414 /* The number of L2 page descriptors allocated to this l2_dtable */ 415 u_int l2_occupancy; 416 417 /* List of L2 page descriptors */ 418 struct l2_bucket { 419 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 420 paddr_t l2b_phys; /* Physical address of same */ 421 u_short l2b_l1idx; /* This L2 table's L1 index */ 422 u_short l2b_occupancy; /* How many active descriptors */ 423 } l2_bucket[L2_BUCKET_SIZE]; 424 }; 425 426 /* 427 * Given an L1 table index, calculate the corresponding l2_dtable index 428 * and bucket index within the l2_dtable. 429 */ 430 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 431 (L2_SIZE - 1)) 432 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 433 434 /* 435 * Given a virtual address, this macro returns the 436 * virtual address required to drop into the next L2 bucket. 437 */ 438 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 439 440 /* 441 * L2 allocation. 442 */ 443 #define pmap_alloc_l2_dtable() \ 444 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 445 #define pmap_free_l2_dtable(l2) \ 446 pool_cache_put(&pmap_l2dtable_cache, (l2)) 447 #define pmap_alloc_l2_ptp(pap) \ 448 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 449 PR_NOWAIT, (pap))) 450 451 /* 452 * We try to map the page tables write-through, if possible. However, not 453 * all CPUs have a write-through cache mode, so on those we have to sync 454 * the cache when we frob page tables. 455 * 456 * We try to evaluate this at compile time, if possible. However, it's 457 * not always possible to do that, hence this run-time var. 458 */ 459 int pmap_needs_pte_sync; 460 461 /* 462 * Real definition of pv_entry. 463 */ 464 struct pv_entry { 465 struct pv_entry *pv_next; /* next pv_entry */ 466 pmap_t pv_pmap; /* pmap where mapping lies */ 467 vaddr_t pv_va; /* virtual address for mapping */ 468 u_int pv_flags; /* flags */ 469 }; 470 471 /* 472 * Macro to determine if a mapping might be resident in the 473 * instruction cache and/or TLB 474 */ 475 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 476 477 /* 478 * Macro to determine if a mapping might be resident in the 479 * data cache and/or TLB 480 */ 481 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 482 483 /* 484 * Local prototypes 485 */ 486 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 487 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 488 pt_entry_t **); 489 static boolean_t pmap_is_current(pmap_t); 490 static boolean_t pmap_is_cached(pmap_t); 491 static void pmap_enter_pv(struct vm_page *, struct pv_entry *, 492 pmap_t, vaddr_t, u_int); 493 static struct pv_entry *pmap_find_pv(struct vm_page *, pmap_t, vaddr_t); 494 static struct pv_entry *pmap_remove_pv(struct vm_page *, pmap_t, vaddr_t); 495 static u_int pmap_modify_pv(struct vm_page *, pmap_t, vaddr_t, 496 u_int, u_int); 497 498 static void pmap_pinit(pmap_t); 499 static int pmap_pmap_ctor(void *, void *, int); 500 501 static void pmap_alloc_l1(pmap_t); 502 static void pmap_free_l1(pmap_t); 503 static void pmap_use_l1(pmap_t); 504 505 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 506 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 507 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 508 static int pmap_l2ptp_ctor(void *, void *, int); 509 static int pmap_l2dtable_ctor(void *, void *, int); 510 511 static void pmap_vac_me_harder(struct vm_page *, pmap_t, vaddr_t); 512 static void pmap_vac_me_kpmap(struct vm_page *, pmap_t, vaddr_t); 513 static void pmap_vac_me_user(struct vm_page *, pmap_t, vaddr_t); 514 515 static void pmap_clearbit(struct vm_page *, u_int); 516 static int pmap_clean_page(struct pv_entry *, boolean_t); 517 static void pmap_page_remove(struct vm_page *); 518 519 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 520 static vaddr_t kernel_pt_lookup(paddr_t); 521 522 523 /* 524 * External function prototypes 525 */ 526 extern void bzero_page(vaddr_t); 527 extern void bcopy_page(vaddr_t, vaddr_t); 528 529 /* 530 * Misc variables 531 */ 532 vaddr_t virtual_avail; 533 vaddr_t virtual_end; 534 vaddr_t pmap_curmaxkvaddr; 535 536 vaddr_t avail_start; 537 vaddr_t avail_end; 538 539 extern pv_addr_t systempage; 540 541 /* Function to set the debug level of the pmap code */ 542 543 #ifdef PMAP_DEBUG 544 void 545 pmap_debug(int level) 546 { 547 pmap_debug_level = level; 548 printf("pmap_debug: level=%d\n", pmap_debug_level); 549 } 550 #endif /* PMAP_DEBUG */ 551 552 /* 553 * A bunch of routines to conditionally flush the caches/TLB depending 554 * on whether the specified pmap actually needs to be flushed at any 555 * given time. 556 */ 557 static __inline void 558 pmap_tlb_flushID_SE(pmap_t pm, vaddr_t va) 559 { 560 561 if (pm->pm_cstate.cs_tlb_id) 562 cpu_tlb_flushID_SE(va); 563 } 564 565 static __inline void 566 pmap_tlb_flushD_SE(pmap_t pm, vaddr_t va) 567 { 568 569 if (pm->pm_cstate.cs_tlb_d) 570 cpu_tlb_flushD_SE(va); 571 } 572 573 static __inline void 574 pmap_tlb_flushID(pmap_t pm) 575 { 576 577 if (pm->pm_cstate.cs_tlb_id) { 578 cpu_tlb_flushID(); 579 pm->pm_cstate.cs_tlb = 0; 580 } 581 } 582 583 static __inline void 584 pmap_tlb_flushD(pmap_t pm) 585 { 586 587 if (pm->pm_cstate.cs_tlb_d) { 588 cpu_tlb_flushD(); 589 pm->pm_cstate.cs_tlb_d = 0; 590 } 591 } 592 593 static __inline void 594 pmap_idcache_wbinv_range(pmap_t pm, vaddr_t va, vsize_t len) 595 { 596 597 if (pm->pm_cstate.cs_cache_id) 598 cpu_idcache_wbinv_range(va, len); 599 } 600 601 static __inline void 602 pmap_dcache_wb_range(pmap_t pm, vaddr_t va, vsize_t len, 603 boolean_t do_inv, boolean_t rd_only) 604 { 605 606 if (pm->pm_cstate.cs_cache_d) { 607 if (do_inv) { 608 if (rd_only) 609 cpu_dcache_inv_range(va, len); 610 else 611 cpu_dcache_wbinv_range(va, len); 612 } else 613 if (!rd_only) 614 cpu_dcache_wb_range(va, len); 615 } 616 } 617 618 static __inline void 619 pmap_idcache_wbinv_all(pmap_t pm) 620 { 621 622 if (pm->pm_cstate.cs_cache_id) { 623 cpu_idcache_wbinv_all(); 624 pm->pm_cstate.cs_cache = 0; 625 } 626 } 627 628 static __inline void 629 pmap_dcache_wbinv_all(pmap_t pm) 630 { 631 632 if (pm->pm_cstate.cs_cache_d) { 633 cpu_dcache_wbinv_all(); 634 pm->pm_cstate.cs_cache_d = 0; 635 } 636 } 637 638 static __inline boolean_t 639 pmap_is_current(pmap_t pm) 640 { 641 642 if (pm == pmap_kernel() || 643 (curproc && curproc->p_vmspace->vm_map.pmap == pm)) 644 return (TRUE); 645 646 return (FALSE); 647 } 648 649 static __inline boolean_t 650 pmap_is_cached(pmap_t pm) 651 { 652 653 if (pm == pmap_kernel() || pmap_cache_state == NULL || 654 pmap_cache_state == &pm->pm_cstate) 655 return (TRUE); 656 657 return (FALSE); 658 } 659 660 /* 661 * PTE_SYNC_CURRENT: 662 * 663 * Make sure the pte is written out to RAM. 664 * We need to do this for one of two cases: 665 * - We're dealing with the kernel pmap 666 * - There is no pmap active in the cache/tlb. 667 * - The specified pmap is 'active' in the cache/tlb. 668 */ 669 #ifdef PMAP_INCLUDE_PTE_SYNC 670 #define PTE_SYNC_CURRENT(pm, ptep) \ 671 do { \ 672 if (PMAP_NEEDS_PTE_SYNC && \ 673 pmap_is_cached(pm)) \ 674 PTE_SYNC(ptep); \ 675 } while (/*CONSTCOND*/0) 676 #else 677 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 678 #endif 679 680 /* 681 * main pv_entry manipulation functions: 682 * pmap_enter_pv: enter a mapping onto a vm_page list 683 * pmap_remove_pv: remove a mappiing from a vm_page list 684 * 685 * NOTE: pmap_enter_pv expects to lock the pvh itself 686 * pmap_remove_pv expects te caller to lock the pvh before calling 687 */ 688 689 /* 690 * pmap_enter_pv: enter a mapping onto a vm_page lst 691 * 692 * => caller should hold the proper lock on pmap_main_lock 693 * => caller should have pmap locked 694 * => we will gain the lock on the vm_page and allocate the new pv_entry 695 * => caller should adjust ptp's wire_count before calling 696 * => caller should not adjust pmap's wire_count 697 */ 698 static void 699 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm, 700 vaddr_t va, u_int flags) 701 { 702 703 NPDEBUG(PDB_PVDUMP, 704 printf("pmap_enter_pv: pm %p, pg %p, flags 0x%x\n", pm, pg, flags)); 705 706 pve->pv_pmap = pm; 707 pve->pv_va = va; 708 pve->pv_flags = flags; 709 710 simple_lock(&pg->mdpage.pvh_slock); /* lock vm_page */ 711 pve->pv_next = pg->mdpage.pvh_list; /* add to ... */ 712 pg->mdpage.pvh_list = pve; /* ... locked list */ 713 pg->mdpage.pvh_attrs |= flags & (PVF_REF | PVF_MOD); 714 if (pm == pmap_kernel()) { 715 if (flags & PVF_WRITE) 716 pg->mdpage.krw_mappings++; 717 else 718 pg->mdpage.kro_mappings++; 719 } else 720 if (flags & PVF_WRITE) 721 pg->mdpage.urw_mappings++; 722 else 723 pg->mdpage.uro_mappings++; 724 simple_unlock(&pg->mdpage.pvh_slock); /* unlock, done! */ 725 726 if (pve->pv_flags & PVF_WIRED) 727 ++pm->pm_stats.wired_count; 728 } 729 730 /* 731 * 732 * pmap_find_pv: Find a pv entry 733 * 734 * => caller should hold lock on vm_page 735 */ 736 static __inline struct pv_entry * 737 pmap_find_pv(struct vm_page *pg, pmap_t pm, vaddr_t va) 738 { 739 struct pv_entry *pv; 740 741 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 742 if (pm == pv->pv_pmap && va == pv->pv_va) 743 break; 744 } 745 746 return (pv); 747 } 748 749 /* 750 * pmap_remove_pv: try to remove a mapping from a pv_list 751 * 752 * => caller should hold proper lock on pmap_main_lock 753 * => pmap should be locked 754 * => caller should hold lock on vm_page [so that attrs can be adjusted] 755 * => caller should adjust ptp's wire_count and free PTP if needed 756 * => caller should NOT adjust pmap's wire_count 757 * => we return the removed pve 758 */ 759 static struct pv_entry * 760 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vaddr_t va) 761 { 762 struct pv_entry *pve, **prevptr; 763 764 NPDEBUG(PDB_PVDUMP, 765 printf("pmap_remove_pv: pm %p, pg %p, va 0x%08lx\n", pm, pg, va)); 766 767 prevptr = &pg->mdpage.pvh_list; /* previous pv_entry pointer */ 768 pve = *prevptr; 769 770 while (pve) { 771 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */ 772 NPDEBUG(PDB_PVDUMP, 773 printf("pmap_remove_pv: pm %p, pg %p, flags 0x%x\n", pm, pg, pve->pv_flags)); 774 *prevptr = pve->pv_next; /* remove it! */ 775 if (pve->pv_flags & PVF_WIRED) 776 --pm->pm_stats.wired_count; 777 if (pm == pmap_kernel()) { 778 if (pve->pv_flags & PVF_WRITE) 779 pg->mdpage.krw_mappings--; 780 else 781 pg->mdpage.kro_mappings--; 782 } else 783 if (pve->pv_flags & PVF_WRITE) 784 pg->mdpage.urw_mappings--; 785 else 786 pg->mdpage.uro_mappings--; 787 break; 788 } 789 prevptr = &pve->pv_next; /* previous pointer */ 790 pve = pve->pv_next; /* advance */ 791 } 792 793 return(pve); /* return removed pve */ 794 } 795 796 /* 797 * 798 * pmap_modify_pv: Update pv flags 799 * 800 * => caller should hold lock on vm_page [so that attrs can be adjusted] 801 * => caller should NOT adjust pmap's wire_count 802 * => caller must call pmap_vac_me_harder() if writable status of a page 803 * may have changed. 804 * => we return the old flags 805 * 806 * Modify a physical-virtual mapping in the pv table 807 */ 808 static u_int 809 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vaddr_t va, 810 u_int clr_mask, u_int set_mask) 811 { 812 struct pv_entry *npv; 813 u_int flags, oflags; 814 815 if ((npv = pmap_find_pv(pg, pm, va)) == NULL) 816 return (0); 817 818 NPDEBUG(PDB_PVDUMP, 819 printf("pmap_modify_pv: pm %p, pg %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, pg, clr_mask, set_mask, npv->pv_flags)); 820 821 /* 822 * There is at least one VA mapping this page. 823 */ 824 825 if (clr_mask & (PVF_REF | PVF_MOD)) 826 pg->mdpage.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 827 828 oflags = npv->pv_flags; 829 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 830 831 if ((flags ^ oflags) & PVF_WIRED) { 832 if (flags & PVF_WIRED) 833 ++pm->pm_stats.wired_count; 834 else 835 --pm->pm_stats.wired_count; 836 } 837 838 if ((flags ^ oflags) & PVF_WRITE) { 839 if (pm == pmap_kernel()) { 840 if (flags & PVF_WRITE) { 841 pg->mdpage.krw_mappings++; 842 pg->mdpage.kro_mappings--; 843 } else { 844 pg->mdpage.kro_mappings++; 845 pg->mdpage.krw_mappings--; 846 } 847 } else 848 if (flags & PVF_WRITE) { 849 pg->mdpage.urw_mappings++; 850 pg->mdpage.uro_mappings--; 851 } else { 852 pg->mdpage.uro_mappings++; 853 pg->mdpage.urw_mappings--; 854 } 855 } 856 857 return (oflags); 858 } 859 860 static void 861 pmap_pinit(pmap_t pm) 862 { 863 864 if (vector_page < KERNEL_BASE) { 865 /* 866 * Map the vector page. 867 */ 868 pmap_enter(pm, vector_page, systempage.pv_pa, 869 VM_PROT_READ, VM_PROT_READ | PMAP_WIRED); 870 pmap_update(pm); 871 } 872 } 873 874 /* 875 * Allocate an L1 translation table for the specified pmap. 876 * This is called at pmap creation time. 877 */ 878 static void 879 pmap_alloc_l1(pmap_t pm) 880 { 881 struct l1_ttable *l1; 882 u_int8_t domain; 883 884 /* 885 * Remove the L1 at the head of the LRU list 886 */ 887 simple_lock(&l1_lru_lock); 888 l1 = TAILQ_FIRST(&l1_lru_list); 889 KDASSERT(l1 != NULL); 890 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 891 892 /* 893 * Pick the first available domain number, and update 894 * the link to the next number. 895 */ 896 domain = l1->l1_domain_first; 897 l1->l1_domain_first = l1->l1_domain_free[domain]; 898 899 /* 900 * If there are still free domain numbers in this L1, 901 * put it back on the TAIL of the LRU list. 902 */ 903 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 904 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 905 906 simple_unlock(&l1_lru_lock); 907 908 /* 909 * Fix up the relevant bits in the pmap structure 910 */ 911 pm->pm_l1 = l1; 912 pm->pm_domain = domain; 913 } 914 915 /* 916 * Free an L1 translation table. 917 * This is called at pmap destruction time. 918 */ 919 static void 920 pmap_free_l1(pmap_t pm) 921 { 922 struct l1_ttable *l1 = pm->pm_l1; 923 924 simple_lock(&l1_lru_lock); 925 926 /* 927 * If this L1 is currently on the LRU list, remove it. 928 */ 929 if (l1->l1_domain_use_count < PMAP_DOMAINS) 930 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 931 932 /* 933 * Free up the domain number which was allocated to the pmap 934 */ 935 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 936 l1->l1_domain_first = pm->pm_domain; 937 l1->l1_domain_use_count--; 938 939 /* 940 * The L1 now must have at least 1 free domain, so add 941 * it back to the LRU list. If the use count is zero, 942 * put it at the head of the list, otherwise it goes 943 * to the tail. 944 */ 945 if (l1->l1_domain_use_count == 0) 946 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 947 else 948 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 949 950 simple_unlock(&l1_lru_lock); 951 } 952 953 static __inline void 954 pmap_use_l1(pmap_t pm) 955 { 956 struct l1_ttable *l1; 957 958 /* 959 * Do nothing if we're in interrupt context. 960 * Access to an L1 by the kernel pmap must not affect 961 * the LRU list. 962 */ 963 if (current_intr_depth || pm == pmap_kernel()) 964 return; 965 966 l1 = pm->pm_l1; 967 968 /* 969 * If the L1 is not currently on the LRU list, just return 970 */ 971 if (l1->l1_domain_use_count == PMAP_DOMAINS) 972 return; 973 974 simple_lock(&l1_lru_lock); 975 976 /* 977 * Check the use count again, now that we've acquired the lock 978 */ 979 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 980 simple_unlock(&l1_lru_lock); 981 return; 982 } 983 984 /* 985 * Move the L1 to the back of the LRU list 986 */ 987 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 988 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 989 990 simple_unlock(&l1_lru_lock); 991 } 992 993 /* 994 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 995 * 996 * Free an L2 descriptor table. 997 */ 998 static __inline void 999 #ifndef PMAP_INCLUDE_PTE_SYNC 1000 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1001 #else 1002 pmap_free_l2_ptp(boolean_t need_sync, pt_entry_t *l2, paddr_t pa) 1003 #endif 1004 { 1005 #ifdef PMAP_INCLUDE_PTE_SYNC 1006 /* 1007 * Note: With a write-back cache, we may need to sync this 1008 * L2 table before re-using it. 1009 * This is because it may have belonged to a non-current 1010 * pmap, in which case the cache syncs would have been 1011 * skipped when the pages were being unmapped. If the 1012 * L2 table were then to be immediately re-allocated to 1013 * the *current* pmap, it may well contain stale mappings 1014 * which have not yet been cleared by a cache write-back 1015 * and so would still be visible to the mmu. 1016 */ 1017 if (need_sync) 1018 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1019 #endif 1020 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1021 } 1022 1023 /* 1024 * Returns a pointer to the L2 bucket associated with the specified pmap 1025 * and VA, or NULL if no L2 bucket exists for the address. 1026 */ 1027 static __inline struct l2_bucket * 1028 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1029 { 1030 struct l2_dtable *l2; 1031 struct l2_bucket *l2b; 1032 u_short l1idx; 1033 1034 l1idx = L1_IDX(va); 1035 1036 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1037 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1038 return (NULL); 1039 1040 return (l2b); 1041 } 1042 1043 /* 1044 * Returns a pointer to the L2 bucket associated with the specified pmap 1045 * and VA. 1046 * 1047 * If no L2 bucket exists, perform the necessary allocations to put an L2 1048 * bucket/page table in place. 1049 * 1050 * Note that if a new L2 bucket/page was allocated, the caller *must* 1051 * increment the bucket occupancy counter appropriately *before* 1052 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1053 * the bucket/page in the meantime. 1054 */ 1055 static struct l2_bucket * 1056 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1057 { 1058 struct l2_dtable *l2; 1059 struct l2_bucket *l2b; 1060 u_short l1idx; 1061 1062 l1idx = L1_IDX(va); 1063 1064 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1065 /* 1066 * No mapping at this address, as there is 1067 * no entry in the L1 table. 1068 * Need to allocate a new l2_dtable. 1069 */ 1070 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1071 return (NULL); 1072 1073 /* 1074 * Link it into the parent pmap 1075 */ 1076 pm->pm_l2[L2_IDX(l1idx)] = l2; 1077 } 1078 1079 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1080 1081 /* 1082 * Fetch pointer to the L2 page table associated with the address. 1083 */ 1084 if (l2b->l2b_kva == NULL) { 1085 pt_entry_t *ptep; 1086 1087 /* 1088 * No L2 page table has been allocated. Chances are, this 1089 * is because we just allocated the l2_dtable, above. 1090 */ 1091 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1092 /* 1093 * Oops, no more L2 page tables available at this 1094 * time. We may need to deallocate the l2_dtable 1095 * if we allocated a new one above. 1096 */ 1097 if (l2->l2_occupancy == 0) { 1098 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1099 pmap_free_l2_dtable(l2); 1100 } 1101 return (NULL); 1102 } 1103 1104 l2->l2_occupancy++; 1105 l2b->l2b_kva = ptep; 1106 l2b->l2b_l1idx = l1idx; 1107 } 1108 1109 return (l2b); 1110 } 1111 1112 /* 1113 * One or more mappings in the specified L2 descriptor table have just been 1114 * invalidated. 1115 * 1116 * Garbage collect the metadata and descriptor table itself if necessary. 1117 * 1118 * The pmap lock must be acquired when this is called (not necessary 1119 * for the kernel pmap). 1120 */ 1121 static void 1122 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1123 { 1124 struct l2_dtable *l2; 1125 pd_entry_t *pl1pd, l1pd; 1126 pt_entry_t *ptep; 1127 u_short l1idx; 1128 1129 KDASSERT(count <= l2b->l2b_occupancy); 1130 1131 /* 1132 * Update the bucket's reference count according to how many 1133 * PTEs the caller has just invalidated. 1134 */ 1135 l2b->l2b_occupancy -= count; 1136 1137 /* 1138 * Note: 1139 * 1140 * Level 2 page tables allocated to the kernel pmap are never freed 1141 * as that would require checking all Level 1 page tables and 1142 * removing any references to the Level 2 page table. See also the 1143 * comment elsewhere about never freeing bootstrap L2 descriptors. 1144 * 1145 * We make do with just invalidating the mapping in the L2 table. 1146 * 1147 * This isn't really a big deal in practice and, in fact, leads 1148 * to a performance win over time as we don't need to continually 1149 * alloc/free. 1150 */ 1151 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1152 return; 1153 1154 /* 1155 * There are no more valid mappings in this level 2 page table. 1156 * Go ahead and NULL-out the pointer in the bucket, then 1157 * free the page table. 1158 */ 1159 l1idx = l2b->l2b_l1idx; 1160 ptep = l2b->l2b_kva; 1161 l2b->l2b_kva = NULL; 1162 1163 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1164 1165 /* 1166 * If the L1 slot matches the pmap's domain 1167 * number, then invalidate it. 1168 */ 1169 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1170 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1171 *pl1pd = 0; 1172 PTE_SYNC(pl1pd); 1173 } 1174 1175 /* 1176 * Release the L2 descriptor table back to the pool cache. 1177 */ 1178 #ifndef PMAP_INCLUDE_PTE_SYNC 1179 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1180 #else 1181 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1182 #endif 1183 1184 /* 1185 * Update the reference count in the associated l2_dtable 1186 */ 1187 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1188 if (--l2->l2_occupancy > 0) 1189 return; 1190 1191 /* 1192 * There are no more valid mappings in any of the Level 1 1193 * slots managed by this l2_dtable. Go ahead and NULL-out 1194 * the pointer in the parent pmap and free the l2_dtable. 1195 */ 1196 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1197 pmap_free_l2_dtable(l2); 1198 } 1199 1200 /* 1201 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1202 * structures. 1203 */ 1204 static int 1205 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1206 { 1207 #ifndef PMAP_INCLUDE_PTE_SYNC 1208 struct l2_bucket *l2b; 1209 pt_entry_t *ptep, pte; 1210 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1211 1212 /* 1213 * The mappings for these page tables were initially made using 1214 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1215 * mode will not be right for page table mappings. To avoid 1216 * polluting the pmap_kenter_pa() code with a special case for 1217 * page tables, we simply fix up the cache-mode here if it's not 1218 * correct. 1219 */ 1220 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1221 KDASSERT(l2b != NULL); 1222 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1223 pte = *ptep; 1224 1225 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1226 /* 1227 * Page tables must have the cache-mode set to Write-Thru. 1228 */ 1229 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1230 PTE_SYNC(ptep); 1231 cpu_tlb_flushD_SE(va); 1232 cpu_cpwait(); 1233 } 1234 #endif 1235 1236 memset(v, 0, L2_TABLE_SIZE_REAL); 1237 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1238 return (0); 1239 } 1240 1241 static int 1242 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1243 { 1244 1245 memset(v, 0, sizeof(struct l2_dtable)); 1246 return (0); 1247 } 1248 1249 static int 1250 pmap_pmap_ctor(void *arg, void *v, int flags) 1251 { 1252 1253 memset(v, 0, sizeof(struct pmap)); 1254 return (0); 1255 } 1256 1257 /* 1258 * Since we have a virtually indexed cache, we may need to inhibit caching if 1259 * there is more than one mapping and at least one of them is writable. 1260 * Since we purge the cache on every context switch, we only need to check for 1261 * other mappings within the same pmap, or kernel_pmap. 1262 * This function is also called when a page is unmapped, to possibly reenable 1263 * caching on any remaining mappings. 1264 * 1265 * The code implements the following logic, where: 1266 * 1267 * KW = # of kernel read/write pages 1268 * KR = # of kernel read only pages 1269 * UW = # of user read/write pages 1270 * UR = # of user read only pages 1271 * 1272 * KC = kernel mapping is cacheable 1273 * UC = user mapping is cacheable 1274 * 1275 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1276 * +--------------------------------------------- 1277 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1278 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1279 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1280 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1281 */ 1282 1283 static const int pmap_vac_flags[4][4] = { 1284 {-1, 0, 0, PVF_KNC}, 1285 {0, 0, PVF_NC, PVF_NC}, 1286 {0, PVF_NC, PVF_NC, PVF_NC}, 1287 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1288 }; 1289 1290 static __inline int 1291 pmap_get_vac_flags(const struct vm_page *pg) 1292 { 1293 int kidx, uidx; 1294 1295 kidx = 0; 1296 if (pg->mdpage.kro_mappings || pg->mdpage.krw_mappings > 1) 1297 kidx |= 1; 1298 if (pg->mdpage.krw_mappings) 1299 kidx |= 2; 1300 1301 uidx = 0; 1302 if (pg->mdpage.uro_mappings || pg->mdpage.urw_mappings > 1) 1303 uidx |= 1; 1304 if (pg->mdpage.urw_mappings) 1305 uidx |= 2; 1306 1307 return (pmap_vac_flags[uidx][kidx]); 1308 } 1309 1310 static __inline void 1311 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vaddr_t va) 1312 { 1313 int nattr; 1314 1315 nattr = pmap_get_vac_flags(pg); 1316 1317 if (nattr < 0) { 1318 pg->mdpage.pvh_attrs &= ~PVF_NC; 1319 return; 1320 } 1321 1322 if (nattr == 0 && (pg->mdpage.pvh_attrs & PVF_NC) == 0) 1323 return; 1324 1325 if (pm == pmap_kernel()) 1326 pmap_vac_me_kpmap(pg, pm, va); 1327 else 1328 pmap_vac_me_user(pg, pm, va); 1329 1330 pg->mdpage.pvh_attrs = (pg->mdpage.pvh_attrs & ~PVF_NC) | nattr; 1331 } 1332 1333 static void 1334 pmap_vac_me_kpmap(struct vm_page *pg, pmap_t pm, vaddr_t va) 1335 { 1336 u_int u_cacheable, u_entries; 1337 struct pv_entry *pv; 1338 pmap_t last_pmap = pm; 1339 1340 /* 1341 * Pass one, see if there are both kernel and user pmaps for 1342 * this page. Calculate whether there are user-writable or 1343 * kernel-writable pages. 1344 */ 1345 u_cacheable = 0; 1346 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 1347 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1348 u_cacheable++; 1349 } 1350 1351 u_entries = pg->mdpage.urw_mappings + pg->mdpage.uro_mappings; 1352 1353 /* 1354 * We know we have just been updating a kernel entry, so if 1355 * all user pages are already cacheable, then there is nothing 1356 * further to do. 1357 */ 1358 if (pg->mdpage.k_mappings == 0 && u_cacheable == u_entries) 1359 return; 1360 1361 if (u_entries) { 1362 /* 1363 * Scan over the list again, for each entry, if it 1364 * might not be set correctly, call pmap_vac_me_user 1365 * to recalculate the settings. 1366 */ 1367 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 1368 /* 1369 * We know kernel mappings will get set 1370 * correctly in other calls. We also know 1371 * that if the pmap is the same as last_pmap 1372 * then we've just handled this entry. 1373 */ 1374 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1375 continue; 1376 1377 /* 1378 * If there are kernel entries and this page 1379 * is writable but non-cacheable, then we can 1380 * skip this entry also. 1381 */ 1382 if (pg->mdpage.k_mappings && 1383 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1384 (PVF_NC | PVF_WRITE)) 1385 continue; 1386 1387 /* 1388 * Similarly if there are no kernel-writable 1389 * entries and the page is already 1390 * read-only/cacheable. 1391 */ 1392 if (pg->mdpage.krw_mappings == 0 && 1393 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1394 continue; 1395 1396 /* 1397 * For some of the remaining cases, we know 1398 * that we must recalculate, but for others we 1399 * can't tell if they are correct or not, so 1400 * we recalculate anyway. 1401 */ 1402 pmap_vac_me_user(pg, (last_pmap = pv->pv_pmap), 0); 1403 } 1404 1405 if (pg->mdpage.k_mappings == 0) 1406 return; 1407 } 1408 1409 pmap_vac_me_user(pg, pm, va); 1410 } 1411 1412 static void 1413 pmap_vac_me_user(struct vm_page *pg, pmap_t pm, vaddr_t va) 1414 { 1415 pmap_t kpmap = pmap_kernel(); 1416 struct pv_entry *pv, *npv; 1417 struct l2_bucket *l2b; 1418 pt_entry_t *ptep, pte; 1419 u_int entries = 0; 1420 u_int writable = 0; 1421 u_int cacheable_entries = 0; 1422 u_int kern_cacheable = 0; 1423 u_int other_writable = 0; 1424 1425 /* 1426 * Count mappings and writable mappings in this pmap. 1427 * Include kernel mappings as part of our own. 1428 * Keep a pointer to the first one. 1429 */ 1430 for (pv = npv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 1431 /* Count mappings in the same pmap */ 1432 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1433 if (entries++ == 0) 1434 npv = pv; 1435 1436 /* Cacheable mappings */ 1437 if ((pv->pv_flags & PVF_NC) == 0) { 1438 cacheable_entries++; 1439 if (kpmap == pv->pv_pmap) 1440 kern_cacheable++; 1441 } 1442 1443 /* Writable mappings */ 1444 if (pv->pv_flags & PVF_WRITE) 1445 ++writable; 1446 } else 1447 if (pv->pv_flags & PVF_WRITE) 1448 other_writable = 1; 1449 } 1450 1451 /* 1452 * Enable or disable caching as necessary. 1453 * Note: the first entry might be part of the kernel pmap, 1454 * so we can't assume this is indicative of the state of the 1455 * other (maybe non-kpmap) entries. 1456 */ 1457 if ((entries > 1 && writable) || 1458 (entries > 0 && pm == kpmap && other_writable)) { 1459 if (cacheable_entries == 0) 1460 return; 1461 1462 for (pv = npv; pv; pv = pv->pv_next) { 1463 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1464 (pv->pv_flags & PVF_NC)) 1465 continue; 1466 1467 pv->pv_flags |= PVF_NC; 1468 1469 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1470 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1471 pte = *ptep & ~L2_S_CACHE_MASK; 1472 1473 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1474 l2pte_valid(pte)) { 1475 if (PV_BEEN_EXECD(pv->pv_flags)) { 1476 pmap_idcache_wbinv_range(pv->pv_pmap, 1477 pv->pv_va, PAGE_SIZE); 1478 pmap_tlb_flushID_SE(pv->pv_pmap, 1479 pv->pv_va); 1480 } else 1481 if (PV_BEEN_REFD(pv->pv_flags)) { 1482 pmap_dcache_wb_range(pv->pv_pmap, 1483 pv->pv_va, PAGE_SIZE, TRUE, 1484 (pv->pv_flags & PVF_WRITE) == 0); 1485 pmap_tlb_flushD_SE(pv->pv_pmap, 1486 pv->pv_va); 1487 } 1488 } 1489 1490 *ptep = pte; 1491 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1492 } 1493 cpu_cpwait(); 1494 } else 1495 if (entries > cacheable_entries) { 1496 /* 1497 * Turn cacheing back on for some pages. If it is a kernel 1498 * page, only do so if there are no other writable pages. 1499 */ 1500 for (pv = npv; pv; pv = pv->pv_next) { 1501 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1502 (kpmap != pv->pv_pmap || other_writable))) 1503 continue; 1504 1505 pv->pv_flags &= ~PVF_NC; 1506 1507 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1508 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1509 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1510 1511 if (l2pte_valid(pte)) { 1512 if (PV_BEEN_EXECD(pv->pv_flags)) { 1513 pmap_tlb_flushID_SE(pv->pv_pmap, 1514 pv->pv_va); 1515 } else 1516 if (PV_BEEN_REFD(pv->pv_flags)) { 1517 pmap_tlb_flushD_SE(pv->pv_pmap, 1518 pv->pv_va); 1519 } 1520 } 1521 1522 *ptep = pte; 1523 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1524 } 1525 } 1526 } 1527 1528 /* 1529 * Modify pte bits for all ptes corresponding to the given physical address. 1530 * We use `maskbits' rather than `clearbits' because we're always passing 1531 * constants and the latter would require an extra inversion at run-time. 1532 */ 1533 static void 1534 pmap_clearbit(struct vm_page *pg, u_int maskbits) 1535 { 1536 struct l2_bucket *l2b; 1537 struct pv_entry *pv; 1538 pt_entry_t *ptep, npte, opte; 1539 pmap_t pm; 1540 vaddr_t va; 1541 u_int oflags; 1542 1543 NPDEBUG(PDB_BITS, 1544 printf("pmap_clearbit: pg %p (0x%08lx) mask 0x%x\n", 1545 pg, pg->phys_addr, maskbits)); 1546 1547 PMAP_HEAD_TO_MAP_LOCK(); 1548 simple_lock(&pg->mdpage.pvh_slock); 1549 1550 /* 1551 * Clear saved attributes (modify, reference) 1552 */ 1553 pg->mdpage.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 1554 1555 if (pg->mdpage.pvh_list == NULL) { 1556 simple_unlock(&pg->mdpage.pvh_slock); 1557 PMAP_HEAD_TO_MAP_UNLOCK(); 1558 return; 1559 } 1560 1561 /* 1562 * Loop over all current mappings setting/clearing as appropos 1563 */ 1564 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 1565 va = pv->pv_va; 1566 pm = pv->pv_pmap; 1567 oflags = pv->pv_flags; 1568 pv->pv_flags &= ~maskbits; 1569 1570 pmap_acquire_pmap_lock(pm); 1571 1572 l2b = pmap_get_l2_bucket(pm, va); 1573 KDASSERT(l2b != NULL); 1574 1575 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1576 npte = opte = *ptep; 1577 1578 NPDEBUG(PDB_BITS, 1579 printf( 1580 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 1581 pv, pv->pv_pmap, pv->pv_va, oflags)); 1582 1583 if (maskbits & (PVF_WRITE|PVF_MOD)) { 1584 if ((pv->pv_flags & PVF_NC)) { 1585 /* 1586 * Entry is not cacheable: 1587 * 1588 * Don't turn caching on again if this is a 1589 * modified emulation. This would be 1590 * inconsitent with the settings created by 1591 * pmap_vac_me_harder(). Otherwise, it's safe 1592 * to re-enable cacheing. 1593 * 1594 * There's no need to call pmap_vac_me_harder() 1595 * here: all pages are losing their write 1596 * permission. 1597 */ 1598 if (maskbits & PVF_WRITE) { 1599 npte |= pte_l2_s_cache_mode; 1600 pv->pv_flags &= ~PVF_NC; 1601 } 1602 } else 1603 if (opte & L2_S_PROT_W) { 1604 /* 1605 * Entry is writable/cacheable: check if pmap 1606 * is current if it is flush it, otherwise it 1607 * won't be in the cache 1608 */ 1609 if (PV_BEEN_EXECD(oflags)) 1610 pmap_idcache_wbinv_range(pm, pv->pv_va, 1611 PAGE_SIZE); 1612 else 1613 if (PV_BEEN_REFD(oflags)) 1614 pmap_dcache_wb_range(pm, pv->pv_va, 1615 PAGE_SIZE, 1616 (maskbits & PVF_REF) ? TRUE : FALSE, 1617 FALSE); 1618 } 1619 1620 /* make the pte read only */ 1621 npte &= ~L2_S_PROT_W; 1622 1623 if (maskbits & PVF_WRITE) { 1624 /* 1625 * Keep alias accounting up to date 1626 */ 1627 if (pv->pv_pmap == pmap_kernel()) { 1628 if (oflags & PVF_WRITE) { 1629 pg->mdpage.krw_mappings--; 1630 pg->mdpage.kro_mappings++; 1631 } 1632 } else 1633 if (oflags & PVF_WRITE) { 1634 pg->mdpage.urw_mappings--; 1635 pg->mdpage.uro_mappings++; 1636 } 1637 } 1638 } 1639 1640 if (maskbits & PVF_REF) { 1641 if ((pv->pv_flags & PVF_NC) == 0 && 1642 (maskbits & (PVF_WRITE|PVF_MOD)) == 0) { 1643 /* 1644 * Check npte here; we may have already 1645 * done the wbinv above, and the validity 1646 * of the PTE is the same for opte and 1647 * npte. 1648 */ 1649 if (npte & L2_S_PROT_W) { 1650 if (PV_BEEN_EXECD(oflags)) 1651 pmap_idcache_wbinv_range(pm, 1652 pv->pv_va, PAGE_SIZE); 1653 else 1654 if (PV_BEEN_REFD(oflags)) 1655 pmap_dcache_wb_range(pm, 1656 pv->pv_va, PAGE_SIZE, 1657 TRUE, FALSE); 1658 } else 1659 if ((npte & L2_TYPE_MASK) != L2_TYPE_INV) { 1660 /* XXXJRT need idcache_inv_range */ 1661 if (PV_BEEN_EXECD(oflags)) 1662 pmap_idcache_wbinv_range(pm, 1663 pv->pv_va, PAGE_SIZE); 1664 else 1665 if (PV_BEEN_REFD(oflags)) 1666 pmap_dcache_wb_range(pm, 1667 pv->pv_va, PAGE_SIZE, 1668 TRUE, TRUE); 1669 } 1670 } 1671 1672 /* 1673 * Make the PTE invalid so that we will take a 1674 * page fault the next time the mapping is 1675 * referenced. 1676 */ 1677 npte &= ~L2_TYPE_MASK; 1678 npte |= L2_TYPE_INV; 1679 } 1680 1681 if (npte != opte) { 1682 *ptep = npte; 1683 PTE_SYNC(ptep); 1684 /* Flush the TLB entry if a current pmap. */ 1685 if (PV_BEEN_EXECD(oflags)) 1686 pmap_tlb_flushID_SE(pm, pv->pv_va); 1687 else 1688 if (PV_BEEN_REFD(oflags)) 1689 pmap_tlb_flushD_SE(pm, pv->pv_va); 1690 } 1691 1692 pmap_release_pmap_lock(pm); 1693 1694 NPDEBUG(PDB_BITS, 1695 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 1696 pm, va, opte, npte)); 1697 } 1698 1699 simple_unlock(&pg->mdpage.pvh_slock); 1700 PMAP_HEAD_TO_MAP_UNLOCK(); 1701 } 1702 1703 /* 1704 * pmap_clean_page() 1705 * 1706 * This is a local function used to work out the best strategy to clean 1707 * a single page referenced by its entry in the PV table. It's used by 1708 * pmap_copy_page, pmap_zero page and maybe some others later on. 1709 * 1710 * Its policy is effectively: 1711 * o If there are no mappings, we don't bother doing anything with the cache. 1712 * o If there is one mapping, we clean just that page. 1713 * o If there are multiple mappings, we clean the entire cache. 1714 * 1715 * So that some functions can be further optimised, it returns 0 if it didn't 1716 * clean the entire cache, or 1 if it did. 1717 * 1718 * XXX One bug in this routine is that if the pv_entry has a single page 1719 * mapped at 0x00000000 a whole cache clean will be performed rather than 1720 * just the 1 page. Since this should not occur in everyday use and if it does 1721 * it will just result in not the most efficient clean for the page. 1722 */ 1723 static int 1724 pmap_clean_page(struct pv_entry *pv, boolean_t is_src) 1725 { 1726 pmap_t pm, pm_to_clean = NULL; 1727 struct pv_entry *npv; 1728 u_int cache_needs_cleaning = 0; 1729 u_int flags = 0; 1730 vaddr_t page_to_clean = 0; 1731 1732 if (pv == NULL) { 1733 /* nothing mapped in so nothing to flush */ 1734 return (0); 1735 } 1736 1737 /* 1738 * Since we flush the cache each time we change to a different 1739 * user vmspace, we only need to flush the page if it is in the 1740 * current pmap. 1741 */ 1742 if (curproc) 1743 pm = curproc->p_vmspace->vm_map.pmap; 1744 else 1745 pm = pmap_kernel(); 1746 1747 for (npv = pv; npv; npv = npv->pv_next) { 1748 if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) { 1749 flags |= npv->pv_flags; 1750 /* 1751 * The page is mapped non-cacheable in 1752 * this map. No need to flush the cache. 1753 */ 1754 if (npv->pv_flags & PVF_NC) { 1755 #ifdef DIAGNOSTIC 1756 if (cache_needs_cleaning) 1757 panic("pmap_clean_page: " 1758 "cache inconsistency"); 1759 #endif 1760 break; 1761 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 1762 continue; 1763 if (cache_needs_cleaning) { 1764 page_to_clean = 0; 1765 break; 1766 } else { 1767 page_to_clean = npv->pv_va; 1768 pm_to_clean = npv->pv_pmap; 1769 } 1770 cache_needs_cleaning = 1; 1771 } 1772 } 1773 1774 if (page_to_clean) { 1775 if (PV_BEEN_EXECD(flags)) 1776 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 1777 PAGE_SIZE); 1778 else 1779 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 1780 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 1781 } else if (cache_needs_cleaning) { 1782 if (PV_BEEN_EXECD(flags)) 1783 pmap_idcache_wbinv_all(pm); 1784 else 1785 pmap_dcache_wbinv_all(pm); 1786 return (1); 1787 } 1788 return (0); 1789 } 1790 1791 /* 1792 * Routine: pmap_page_remove 1793 * Function: 1794 * Removes this physical page from 1795 * all physical maps in which it resides. 1796 * Reflects back modify bits to the pager. 1797 */ 1798 static void 1799 pmap_page_remove(struct vm_page *pg) 1800 { 1801 struct l2_bucket *l2b; 1802 struct pv_entry *pv, *npv; 1803 pmap_t pm, curpm; 1804 pt_entry_t *ptep, pte; 1805 boolean_t flush; 1806 u_int flags; 1807 1808 NPDEBUG(PDB_FOLLOW, 1809 printf("pmap_page_remove: pg %p (0x%08lx)\n", pg, pg->phys_addr)); 1810 1811 PMAP_HEAD_TO_MAP_LOCK(); 1812 simple_lock(&pg->mdpage.pvh_slock); 1813 1814 pv = pg->mdpage.pvh_list; 1815 if (pv == NULL) { 1816 simple_unlock(&pg->mdpage.pvh_slock); 1817 PMAP_HEAD_TO_MAP_UNLOCK(); 1818 return; 1819 } 1820 1821 /* 1822 * Clear alias counts 1823 */ 1824 pg->mdpage.k_mappings = 0; 1825 pg->mdpage.urw_mappings = pg->mdpage.uro_mappings = 0; 1826 1827 flush = FALSE; 1828 flags = 0; 1829 if (curproc) 1830 curpm = curproc->p_vmspace->vm_map.pmap; 1831 else 1832 curpm = pmap_kernel(); 1833 1834 pmap_clean_page(pv, FALSE); 1835 1836 while (pv) { 1837 pm = pv->pv_pmap; 1838 if (flush == FALSE && (pm == curpm || pm == pmap_kernel())) 1839 flush = TRUE; 1840 1841 pmap_acquire_pmap_lock(pm); 1842 1843 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 1844 KDASSERT(l2b != NULL); 1845 1846 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1847 pte = *ptep; 1848 1849 /* 1850 * Update statistics 1851 */ 1852 --pm->pm_stats.resident_count; 1853 1854 /* Wired bit */ 1855 if (pv->pv_flags & PVF_WIRED) 1856 --pm->pm_stats.wired_count; 1857 1858 flags |= pv->pv_flags; 1859 1860 /* 1861 * Invalidate the PTEs. 1862 */ 1863 *ptep = 0; 1864 PTE_SYNC_CURRENT(pm, ptep); 1865 pmap_free_l2_bucket(pm, l2b, 1); 1866 1867 npv = pv->pv_next; 1868 pool_put(&pmap_pv_pool, pv); 1869 pv = npv; 1870 pmap_release_pmap_lock(pm); 1871 } 1872 pg->mdpage.pvh_list = NULL; 1873 simple_unlock(&pg->mdpage.pvh_slock); 1874 PMAP_HEAD_TO_MAP_UNLOCK(); 1875 1876 if (flush) { 1877 if (PV_BEEN_EXECD(flags)) 1878 pmap_tlb_flushID(curpm); 1879 else 1880 pmap_tlb_flushD(curpm); 1881 } 1882 cpu_cpwait(); 1883 } 1884 1885 /* 1886 * pmap_t pmap_create(void) 1887 * 1888 * Create a new pmap structure from scratch. 1889 */ 1890 pmap_t 1891 pmap_create(void) 1892 { 1893 pmap_t pm; 1894 1895 pm = pool_cache_get(&pmap_pmap_cache, PR_WAITOK); 1896 1897 simple_lock_init(&pm->pm_lock); 1898 pm->pm_obj.pgops = NULL; /* currently not a mappable object */ 1899 TAILQ_INIT(&pm->pm_obj.memq); 1900 pm->pm_obj.uo_npages = 0; 1901 pm->pm_obj.uo_refs = 1; 1902 pm->pm_stats.wired_count = 0; 1903 pm->pm_stats.resident_count = 1; 1904 pm->pm_cstate.cs_all = 0; 1905 pmap_alloc_l1(pm); 1906 1907 /* 1908 * Note: The pool cache ensures that the pm_l2[] array is already 1909 * initialised to zero. 1910 */ 1911 1912 pmap_pinit(pm); 1913 1914 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 1915 1916 return (pm); 1917 } 1918 1919 /* 1920 * void pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 1921 * int flags) 1922 * 1923 * Insert the given physical page (p) at 1924 * the specified virtual address (v) in the 1925 * target physical map with the protection requested. 1926 * 1927 * NB: This is the only routine which MAY NOT lazy-evaluate 1928 * or lose information. That is, this routine must actually 1929 * insert this page into the given map NOW. 1930 */ 1931 int 1932 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, int flags) 1933 { 1934 struct l2_bucket *l2b; 1935 struct vm_page *pg, *opg; 1936 struct pv_entry *pve; 1937 pt_entry_t *ptep, npte, opte; 1938 u_int nflags; 1939 u_int oflags; 1940 1941 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 1942 1943 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 1944 KDASSERT(((va | pa) & PGOFSET) == 0); 1945 1946 /* 1947 * Get a pointer to the page. Later on in this function, we 1948 * test for a managed page by checking pg != NULL. 1949 */ 1950 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 1951 1952 nflags = 0; 1953 if (prot & VM_PROT_WRITE) 1954 nflags |= PVF_WRITE; 1955 if (prot & VM_PROT_EXECUTE) 1956 nflags |= PVF_EXEC; 1957 if (flags & PMAP_WIRED) 1958 nflags |= PVF_WIRED; 1959 1960 PMAP_MAP_TO_HEAD_LOCK(); 1961 pmap_acquire_pmap_lock(pm); 1962 1963 /* 1964 * Fetch the L2 bucket which maps this page, allocating one if 1965 * necessary for user pmaps. 1966 */ 1967 if (pm == pmap_kernel()) 1968 l2b = pmap_get_l2_bucket(pm, va); 1969 else 1970 l2b = pmap_alloc_l2_bucket(pm, va); 1971 if (l2b == NULL) { 1972 if (flags & PMAP_CANFAIL) { 1973 pmap_release_pmap_lock(pm); 1974 PMAP_MAP_TO_HEAD_UNLOCK(); 1975 return (ENOMEM); 1976 } 1977 panic("pmap_enter: failed to allocate L2 bucket"); 1978 } 1979 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1980 opte = *ptep; 1981 npte = pa; 1982 oflags = 0; 1983 1984 if (opte) { 1985 /* 1986 * There is already a mapping at this address. 1987 * If the physical address is different, lookup the 1988 * vm_page. 1989 */ 1990 if (l2pte_pa(opte) != pa) 1991 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 1992 else 1993 opg = pg; 1994 } else 1995 opg = NULL; 1996 1997 if (pg) { 1998 /* 1999 * This is to be a managed mapping. 2000 */ 2001 if ((flags & VM_PROT_ALL) || 2002 (pg->mdpage.pvh_attrs & PVF_REF)) { 2003 /* 2004 * - The access type indicates that we don't need 2005 * to do referenced emulation. 2006 * OR 2007 * - The physical page has already been referenced 2008 * so no need to re-do referenced emulation here. 2009 */ 2010 npte |= L2_S_PROTO; 2011 2012 nflags |= PVF_REF; 2013 2014 if ((prot & VM_PROT_WRITE) != 0 && 2015 ((flags & VM_PROT_WRITE) != 0 || 2016 (pg->mdpage.pvh_attrs & PVF_MOD) != 0)) { 2017 /* 2018 * This is a writable mapping, and the 2019 * page's mod state indicates it has 2020 * already been modified. Make it 2021 * writable from the outset. 2022 */ 2023 npte |= L2_S_PROT_W; 2024 nflags |= PVF_MOD; 2025 } 2026 } else { 2027 /* 2028 * Need to do page referenced emulation. 2029 */ 2030 npte |= L2_TYPE_INV; 2031 } 2032 2033 npte |= pte_l2_s_cache_mode; 2034 2035 if (pg == opg) { 2036 /* 2037 * We're changing the attrs of an existing mapping. 2038 */ 2039 simple_lock(&pg->mdpage.pvh_slock); 2040 oflags = pmap_modify_pv(pg, pm, va, 2041 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2042 PVF_MOD | PVF_REF, nflags); 2043 simple_unlock(&pg->mdpage.pvh_slock); 2044 2045 /* 2046 * We may need to flush the cache if we're 2047 * doing rw-ro... 2048 */ 2049 if (pm->pm_cstate.cs_cache_d && 2050 (oflags & PVF_NC) == 0 && 2051 (opte & L2_S_PROT_W) != 0 && 2052 (prot & VM_PROT_WRITE) == 0) 2053 cpu_dcache_wb_range(va, PAGE_SIZE); 2054 } else { 2055 /* 2056 * New mapping, or changing the backing page 2057 * of an existing mapping. 2058 */ 2059 if (opg) { 2060 /* 2061 * Replacing an existing mapping with a new one. 2062 * It is part of our managed memory so we 2063 * must remove it from the PV list 2064 */ 2065 simple_lock(&opg->mdpage.pvh_slock); 2066 pve = pmap_remove_pv(opg, pm, va); 2067 pmap_vac_me_harder(opg, pm, 0); 2068 simple_unlock(&opg->mdpage.pvh_slock); 2069 oflags = pve->pv_flags; 2070 2071 /* 2072 * If the old mapping was valid (ref/mod 2073 * emulation creates 'invalid' mappings 2074 * initially) then make sure to frob 2075 * the cache. 2076 */ 2077 if ((oflags & PVF_NC) == 0 && 2078 l2pte_valid(opte)) { 2079 if (PV_BEEN_EXECD(oflags)) { 2080 pmap_idcache_wbinv_range(pm, va, 2081 PAGE_SIZE); 2082 } else 2083 if (PV_BEEN_REFD(oflags)) { 2084 pmap_dcache_wb_range(pm, va, 2085 PAGE_SIZE, TRUE, 2086 (oflags & PVF_WRITE) == 0); 2087 } 2088 } 2089 } else 2090 if ((pve = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2091 if ((flags & PMAP_CANFAIL) == 0) 2092 panic("pmap_enter: no pv entries"); 2093 2094 if (pm != pmap_kernel()) 2095 pmap_free_l2_bucket(pm, l2b, 0); 2096 pmap_release_pmap_lock(pm); 2097 PMAP_MAP_TO_HEAD_UNLOCK(); 2098 NPDEBUG(PDB_ENTER, 2099 printf("pmap_enter: ENOMEM\n")); 2100 return (ENOMEM); 2101 } 2102 2103 pmap_enter_pv(pg, pve, pm, va, nflags); 2104 } 2105 } else { 2106 /* 2107 * We're mapping an unmanaged page. 2108 * These are always readable, and possibly writable, from 2109 * the get go as we don't need to track ref/mod status. 2110 */ 2111 npte |= L2_S_PROTO; 2112 if (prot & VM_PROT_WRITE) 2113 npte |= L2_S_PROT_W; 2114 2115 /* 2116 * Make sure the vector table is mapped cacheable 2117 */ 2118 if (pm != pmap_kernel() && va == vector_page) 2119 npte |= pte_l2_s_cache_mode; 2120 2121 if (opg) { 2122 /* 2123 * Looks like there's an existing 'managed' mapping 2124 * at this address. 2125 */ 2126 simple_lock(&opg->mdpage.pvh_slock); 2127 pve = pmap_remove_pv(opg, pm, va); 2128 pmap_vac_me_harder(opg, pm, 0); 2129 simple_unlock(&opg->mdpage.pvh_slock); 2130 oflags = pve->pv_flags; 2131 2132 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 2133 if (PV_BEEN_EXECD(oflags)) 2134 pmap_idcache_wbinv_range(pm, va, 2135 PAGE_SIZE); 2136 else 2137 if (PV_BEEN_REFD(oflags)) 2138 pmap_dcache_wb_range(pm, va, PAGE_SIZE, 2139 TRUE, (oflags & PVF_WRITE) == 0); 2140 } 2141 pool_put(&pmap_pv_pool, pve); 2142 } 2143 } 2144 2145 /* 2146 * Make sure userland mappings get the right permissions 2147 */ 2148 if (pm != pmap_kernel() && va != vector_page) 2149 npte |= L2_S_PROT_U; 2150 2151 /* 2152 * Keep the stats up to date 2153 */ 2154 if (opte == 0) { 2155 l2b->l2b_occupancy++; 2156 pm->pm_stats.resident_count++; 2157 } 2158 2159 NPDEBUG(PDB_ENTER, 2160 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 2161 2162 /* 2163 * If this is just a wiring change, the two PTEs will be 2164 * identical, so there's no need to update the page table. 2165 */ 2166 if (npte != opte) { 2167 boolean_t is_cached = pmap_is_cached(pm); 2168 2169 *ptep = npte; 2170 if (is_cached) { 2171 /* 2172 * We only need to frob the cache/tlb if this pmap 2173 * is current 2174 */ 2175 PTE_SYNC(ptep); 2176 if (va != vector_page && l2pte_valid(npte)) { 2177 /* 2178 * This mapping is likely to be accessed as 2179 * soon as we return to userland. Fix up the 2180 * L1 entry to avoid taking another 2181 * page/domain fault. 2182 */ 2183 pd_entry_t *pl1pd, l1pd; 2184 2185 pl1pd = &pm->pm_l1->l1_kva[L1_IDX(va)]; 2186 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | 2187 L1_C_PROTO; 2188 if (*pl1pd != l1pd) { 2189 *pl1pd = l1pd; 2190 PTE_SYNC(pl1pd); 2191 } 2192 } 2193 } 2194 2195 if (PV_BEEN_EXECD(oflags)) 2196 pmap_tlb_flushID_SE(pm, va); 2197 else 2198 if (PV_BEEN_REFD(oflags)) 2199 pmap_tlb_flushD_SE(pm, va); 2200 2201 NPDEBUG(PDB_ENTER, 2202 printf("pmap_enter: is_cached %d cs 0x%08x\n", 2203 is_cached, pm->pm_cstate.cs_all)); 2204 2205 if (pg != NULL) { 2206 simple_lock(&pg->mdpage.pvh_slock); 2207 pmap_vac_me_harder(pg, pm, va); 2208 simple_unlock(&pg->mdpage.pvh_slock); 2209 } 2210 } 2211 2212 pmap_release_pmap_lock(pm); 2213 PMAP_MAP_TO_HEAD_UNLOCK(); 2214 2215 return (0); 2216 } 2217 2218 /* 2219 * pmap_remove() 2220 * 2221 * pmap_remove is responsible for nuking a number of mappings for a range 2222 * of virtual address space in the current pmap. To do this efficiently 2223 * is interesting, because in a number of cases a wide virtual address 2224 * range may be supplied that contains few actual mappings. So, the 2225 * optimisations are: 2226 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 2227 * 2. Build up a list of pages we've hit, up to a maximum, so we can 2228 * maybe do just a partial cache clean. This path of execution is 2229 * complicated by the fact that the cache must be flushed _before_ 2230 * the PTE is nuked, being a VAC :-) 2231 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 2232 * all invalidations until pmap_update(), since pmap_remove_all() has 2233 * already flushed the cache. 2234 * 4. Maybe later fast-case a single page, but I don't think this is 2235 * going to make _that_ much difference overall. 2236 */ 2237 2238 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 2239 2240 void 2241 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 2242 { 2243 struct l2_bucket *l2b; 2244 vaddr_t next_bucket; 2245 pt_entry_t *ptep; 2246 u_int cleanlist_idx, total, cnt; 2247 struct { 2248 vaddr_t va; 2249 pt_entry_t *pte; 2250 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 2251 u_int mappings, is_exec, is_refd; 2252 2253 NPDEBUG(PDB_REMOVE, printf("pmap_remove: pmap=%p sva=%08lx eva=%08lx\n", 2254 pm, sva, eva)); 2255 2256 /* 2257 * we lock in the pmap => pv_head direction 2258 */ 2259 PMAP_MAP_TO_HEAD_LOCK(); 2260 pmap_acquire_pmap_lock(pm); 2261 2262 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 2263 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 2264 if (pm->pm_cstate.cs_tlb == 0) 2265 pm->pm_remove_all = TRUE; 2266 } else 2267 cleanlist_idx = 0; 2268 2269 total = 0; 2270 2271 while (sva < eva) { 2272 /* 2273 * Do one L2 bucket's worth at a time. 2274 */ 2275 next_bucket = L2_NEXT_BUCKET(sva); 2276 if (next_bucket > eva) 2277 next_bucket = eva; 2278 2279 l2b = pmap_get_l2_bucket(pm, sva); 2280 if (l2b == NULL) { 2281 sva = next_bucket; 2282 continue; 2283 } 2284 2285 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 2286 mappings = 0; 2287 2288 while (sva < next_bucket) { 2289 struct vm_page *pg; 2290 pt_entry_t pte; 2291 paddr_t pa; 2292 2293 pte = *ptep; 2294 2295 if (pte == 0) { 2296 /* 2297 * Nothing here, move along 2298 */ 2299 sva += PAGE_SIZE; 2300 ptep++; 2301 continue; 2302 } 2303 2304 pm->pm_stats.resident_count--; 2305 pa = l2pte_pa(pte); 2306 is_exec = 0; 2307 is_refd = 1; 2308 2309 /* 2310 * Update flags. In a number of circumstances, 2311 * we could cluster a lot of these and do a 2312 * number of sequential pages in one go. 2313 */ 2314 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 2315 struct pv_entry *pve; 2316 simple_lock(&pg->mdpage.pvh_slock); 2317 pve = pmap_remove_pv(pg, pm, sva); 2318 pmap_vac_me_harder(pg, pm, 0); 2319 simple_unlock(&pg->mdpage.pvh_slock); 2320 if (pve != NULL) { 2321 if (pm->pm_remove_all == FALSE) { 2322 is_exec = 2323 PV_BEEN_EXECD(pve->pv_flags); 2324 is_refd = 2325 PV_BEEN_REFD(pve->pv_flags); 2326 } 2327 pool_put(&pmap_pv_pool, pve); 2328 } 2329 } 2330 2331 if (!l2pte_valid(pte)) { 2332 *ptep = 0; 2333 PTE_SYNC_CURRENT(pm, ptep); 2334 sva += PAGE_SIZE; 2335 ptep++; 2336 mappings++; 2337 continue; 2338 } 2339 2340 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 2341 /* Add to the clean list. */ 2342 cleanlist[cleanlist_idx].pte = ptep; 2343 cleanlist[cleanlist_idx].va = 2344 sva | (is_exec & 1); 2345 cleanlist_idx++; 2346 } else 2347 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 2348 /* Nuke everything if needed. */ 2349 pmap_idcache_wbinv_all(pm); 2350 pmap_tlb_flushID(pm); 2351 2352 /* 2353 * Roll back the previous PTE list, 2354 * and zero out the current PTE. 2355 */ 2356 for (cnt = 0; 2357 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 2358 *cleanlist[cnt].pte = 0; 2359 } 2360 *ptep = 0; 2361 PTE_SYNC(ptep); 2362 cleanlist_idx++; 2363 pm->pm_remove_all = TRUE; 2364 } else { 2365 *ptep = 0; 2366 PTE_SYNC(ptep); 2367 if (pm->pm_remove_all == FALSE) { 2368 if (is_exec) 2369 pmap_tlb_flushID_SE(pm, sva); 2370 else 2371 if (is_refd) 2372 pmap_tlb_flushD_SE(pm, sva); 2373 } 2374 } 2375 2376 sva += PAGE_SIZE; 2377 ptep++; 2378 mappings++; 2379 } 2380 2381 /* 2382 * Deal with any left overs 2383 */ 2384 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 2385 total += cleanlist_idx; 2386 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 2387 if (pm->pm_cstate.cs_all != 0) { 2388 vaddr_t clva = cleanlist[cnt].va & ~1; 2389 if (cleanlist[cnt].va & 1) { 2390 pmap_idcache_wbinv_range(pm, 2391 clva, PAGE_SIZE); 2392 pmap_tlb_flushID_SE(pm, clva); 2393 } else { 2394 pmap_dcache_wb_range(pm, 2395 clva, PAGE_SIZE, TRUE, 2396 FALSE); 2397 pmap_tlb_flushD_SE(pm, clva); 2398 } 2399 } 2400 *cleanlist[cnt].pte = 0; 2401 PTE_SYNC_CURRENT(pm, cleanlist[cnt].pte); 2402 } 2403 2404 /* 2405 * If it looks like we're removing a whole bunch 2406 * of mappings, it's faster to just write-back 2407 * the whole cache now and defer TLB flushes until 2408 * pmap_update() is called. 2409 */ 2410 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 2411 cleanlist_idx = 0; 2412 else { 2413 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 2414 pmap_idcache_wbinv_all(pm); 2415 pm->pm_remove_all = TRUE; 2416 } 2417 } 2418 2419 pmap_free_l2_bucket(pm, l2b, mappings); 2420 } 2421 2422 pmap_release_pmap_lock(pm); 2423 PMAP_MAP_TO_HEAD_UNLOCK(); 2424 } 2425 2426 /* 2427 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 2428 * 2429 * We assume there is already sufficient KVM space available 2430 * to do this, as we can't allocate L2 descriptor tables/metadata 2431 * from here. 2432 */ 2433 void 2434 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot) 2435 { 2436 struct l2_bucket *l2b; 2437 pt_entry_t *ptep, opte; 2438 2439 NPDEBUG(PDB_KENTER, 2440 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 2441 va, pa, prot)); 2442 2443 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2444 KDASSERT(l2b != NULL); 2445 2446 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2447 opte = *ptep; 2448 2449 if (l2pte_valid(opte)) { 2450 cpu_dcache_wbinv_range(va, PAGE_SIZE); 2451 cpu_tlb_flushD_SE(va); 2452 cpu_cpwait(); 2453 } else 2454 if (opte == 0) 2455 l2b->l2b_occupancy++; 2456 2457 *ptep = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | 2458 pte_l2_s_cache_mode; 2459 PTE_SYNC(ptep); 2460 } 2461 2462 void 2463 pmap_kremove(vaddr_t va, vsize_t len) 2464 { 2465 struct l2_bucket *l2b; 2466 pt_entry_t *ptep, *sptep, opte; 2467 vaddr_t next_bucket, eva; 2468 u_int mappings; 2469 2470 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 2471 va, len)); 2472 2473 eva = va + len; 2474 2475 while (va < eva) { 2476 next_bucket = L2_NEXT_BUCKET(va); 2477 if (next_bucket > eva) 2478 next_bucket = eva; 2479 2480 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2481 KDASSERT(l2b != NULL); 2482 2483 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 2484 mappings = 0; 2485 2486 while (va < next_bucket) { 2487 opte = *ptep; 2488 if (l2pte_valid(opte)) { 2489 cpu_dcache_wbinv_range(va, PAGE_SIZE); 2490 cpu_tlb_flushD_SE(va); 2491 } 2492 if (opte) { 2493 *ptep = 0; 2494 mappings++; 2495 } 2496 va += PAGE_SIZE; 2497 ptep++; 2498 } 2499 KDASSERT(mappings <= l2b->l2b_occupancy); 2500 l2b->l2b_occupancy -= mappings; 2501 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 2502 } 2503 cpu_cpwait(); 2504 } 2505 2506 boolean_t 2507 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 2508 { 2509 struct l2_dtable *l2; 2510 pd_entry_t *pl1pd, l1pd; 2511 pt_entry_t *ptep, pte; 2512 paddr_t pa; 2513 u_int l1idx; 2514 2515 pmap_acquire_pmap_lock(pm); 2516 2517 l1idx = L1_IDX(va); 2518 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 2519 l1pd = *pl1pd; 2520 2521 if (l1pte_section_p(l1pd)) { 2522 /* 2523 * These should only happen for pmap_kernel() 2524 */ 2525 KDASSERT(pm == pmap_kernel()); 2526 pmap_release_pmap_lock(pm); 2527 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 2528 } else { 2529 /* 2530 * Note that we can't rely on the validity of the L1 2531 * descriptor as an indication that a mapping exists. 2532 * We have to look it up in the L2 dtable. 2533 */ 2534 l2 = pm->pm_l2[L2_IDX(l1idx)]; 2535 2536 if (l2 == NULL || 2537 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 2538 pmap_release_pmap_lock(pm); 2539 return (FALSE); 2540 } 2541 2542 ptep = &ptep[l2pte_index(va)]; 2543 pte = *ptep; 2544 pmap_release_pmap_lock(pm); 2545 2546 if (pte == 0) 2547 return (FALSE); 2548 2549 switch (pte & L2_TYPE_MASK) { 2550 case L2_TYPE_L: 2551 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 2552 break; 2553 2554 default: 2555 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 2556 break; 2557 } 2558 } 2559 2560 if (pap != NULL) 2561 *pap = pa; 2562 2563 return (TRUE); 2564 } 2565 2566 void 2567 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 2568 { 2569 struct l2_bucket *l2b; 2570 pt_entry_t *ptep, pte; 2571 vaddr_t next_bucket; 2572 u_int flags; 2573 int flush; 2574 2575 NPDEBUG(PDB_PROTECT, 2576 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 2577 pm, sva, eva, prot)); 2578 2579 if ((prot & VM_PROT_READ) == 0) { 2580 pmap_remove(pm, sva, eva); 2581 return; 2582 } 2583 2584 if (prot & VM_PROT_WRITE) { 2585 /* 2586 * If this is a read->write transition, just ignore it and let 2587 * uvm_fault() take care of it later. 2588 */ 2589 return; 2590 } 2591 2592 PMAP_MAP_TO_HEAD_LOCK(); 2593 pmap_acquire_pmap_lock(pm); 2594 2595 /* 2596 * OK, at this point, we know we're doing write-protect operation. 2597 * If the pmap is active, write-back the range. 2598 */ 2599 pmap_dcache_wb_range(pm, sva, eva - sva, FALSE, FALSE); 2600 2601 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 2602 flags = 0; 2603 2604 while (sva < eva) { 2605 next_bucket = L2_NEXT_BUCKET(sva); 2606 if (next_bucket > eva) 2607 next_bucket = eva; 2608 2609 l2b = pmap_get_l2_bucket(pm, sva); 2610 if (l2b == NULL) { 2611 sva = next_bucket; 2612 continue; 2613 } 2614 2615 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 2616 2617 while (sva < next_bucket) { 2618 if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) { 2619 struct vm_page *pg; 2620 u_int f; 2621 2622 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 2623 pte &= ~L2_S_PROT_W; 2624 *ptep = pte; 2625 PTE_SYNC(ptep); 2626 2627 if (pg != NULL) { 2628 simple_lock(&pg->mdpage.pvh_slock); 2629 f = pmap_modify_pv(pg, pm, sva, 2630 PVF_WRITE, 0); 2631 pmap_vac_me_harder(pg, pm, sva); 2632 simple_unlock(&pg->mdpage.pvh_slock); 2633 } else 2634 f = PVF_REF | PVF_EXEC; 2635 2636 if (flush >= 0) { 2637 flush++; 2638 flags |= f; 2639 } else 2640 if (PV_BEEN_EXECD(f)) 2641 pmap_tlb_flushID_SE(pm, sva); 2642 else 2643 if (PV_BEEN_REFD(f)) 2644 pmap_tlb_flushD_SE(pm, sva); 2645 } 2646 2647 sva += PAGE_SIZE; 2648 ptep++; 2649 } 2650 } 2651 2652 pmap_release_pmap_lock(pm); 2653 PMAP_MAP_TO_HEAD_UNLOCK(); 2654 2655 if (flush) { 2656 if (PV_BEEN_EXECD(flags)) 2657 pmap_tlb_flushID(pm); 2658 else 2659 if (PV_BEEN_REFD(flags)) 2660 pmap_tlb_flushD(pm); 2661 } 2662 } 2663 2664 void 2665 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 2666 { 2667 2668 NPDEBUG(PDB_PROTECT, 2669 printf("pmap_page_protect: pg %p (0x%08lx), prot 0x%x\n", 2670 pg, pg->phys_addr, prot)); 2671 2672 switch(prot) { 2673 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 2674 case VM_PROT_READ|VM_PROT_WRITE: 2675 return; 2676 2677 case VM_PROT_READ: 2678 case VM_PROT_READ|VM_PROT_EXECUTE: 2679 pmap_clearbit(pg, PVF_WRITE); 2680 break; 2681 2682 default: 2683 pmap_page_remove(pg); 2684 break; 2685 } 2686 } 2687 2688 /* 2689 * pmap_clear_modify: 2690 * 2691 * Clear the "modified" attribute for a page. 2692 */ 2693 boolean_t 2694 pmap_clear_modify(struct vm_page *pg) 2695 { 2696 boolean_t rv; 2697 2698 if (pg->mdpage.pvh_attrs & PVF_MOD) { 2699 rv = TRUE; 2700 pmap_clearbit(pg, PVF_MOD); 2701 } else 2702 rv = FALSE; 2703 2704 return (rv); 2705 } 2706 2707 /* 2708 * pmap_clear_reference: 2709 * 2710 * Clear the "referenced" attribute for a page. 2711 */ 2712 boolean_t 2713 pmap_clear_reference(struct vm_page *pg) 2714 { 2715 boolean_t rv; 2716 2717 if (pg->mdpage.pvh_attrs & PVF_REF) { 2718 rv = TRUE; 2719 pmap_clearbit(pg, PVF_REF); 2720 } else 2721 rv = FALSE; 2722 2723 return (rv); 2724 } 2725 2726 /* 2727 * pmap_is_modified: 2728 * 2729 * Test if a page has the "modified" attribute. 2730 */ 2731 /* See <arm/arm32/pmap.h> */ 2732 2733 /* 2734 * pmap_is_referenced: 2735 * 2736 * Test if a page has the "referenced" attribute. 2737 */ 2738 /* See <arm/arm32/pmap.h> */ 2739 2740 int 2741 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 2742 { 2743 struct l2_dtable *l2; 2744 struct l2_bucket *l2b; 2745 pd_entry_t *pl1pd, l1pd; 2746 pt_entry_t *ptep, pte; 2747 paddr_t pa; 2748 u_int l1idx; 2749 int rv = 0; 2750 2751 PMAP_MAP_TO_HEAD_LOCK(); 2752 pmap_acquire_pmap_lock(pm); 2753 2754 l1idx = L1_IDX(va); 2755 2756 /* 2757 * If there is no l2_dtable for this address, then the process 2758 * has no business accessing it. 2759 * 2760 * Note: This will catch userland processes trying to access 2761 * kernel addresses. 2762 */ 2763 l2 = pm->pm_l2[L2_IDX(l1idx)]; 2764 if (l2 == NULL) 2765 goto out; 2766 2767 /* 2768 * Likewise if there is no L2 descriptor table 2769 */ 2770 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2771 if (l2b->l2b_kva == NULL) 2772 goto out; 2773 2774 /* 2775 * Check the PTE itself. 2776 */ 2777 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2778 pte = *ptep; 2779 if (pte == 0) 2780 goto out; 2781 2782 /* 2783 * Catch a userland access to the vector page mapped at 0x0 2784 */ 2785 if (user && (pte & L2_S_PROT_U) == 0) 2786 goto out; 2787 2788 pa = l2pte_pa(pte); 2789 2790 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { 2791 /* 2792 * This looks like a good candidate for "page modified" 2793 * emulation... 2794 */ 2795 struct pv_entry *pv; 2796 struct vm_page *pg; 2797 2798 /* Extract the physical address of the page */ 2799 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 2800 goto out; 2801 2802 /* Get the current flags for this page. */ 2803 simple_lock(&pg->mdpage.pvh_slock); 2804 2805 pv = pmap_find_pv(pg, pm, va); 2806 if (pv == NULL) { 2807 simple_unlock(&pg->mdpage.pvh_slock); 2808 goto out; 2809 } 2810 2811 /* 2812 * Do the flags say this page is writable? If not then it 2813 * is a genuine write fault. If yes then the write fault is 2814 * our fault as we did not reflect the write access in the 2815 * PTE. Now we know a write has occurred we can correct this 2816 * and also set the modified bit 2817 */ 2818 if ((pv->pv_flags & PVF_WRITE) == 0) { 2819 simple_unlock(&pg->mdpage.pvh_slock); 2820 goto out; 2821 } 2822 2823 NPDEBUG(PDB_FOLLOW, 2824 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 2825 pm, va, pg->phys_addr)); 2826 2827 pg->mdpage.pvh_attrs |= PVF_REF | PVF_MOD; 2828 pv->pv_flags |= PVF_REF | PVF_MOD; 2829 simple_unlock(&pg->mdpage.pvh_slock); 2830 2831 /* 2832 * Re-enable write permissions for the page. No need to call 2833 * pmap_vac_me_harder(), since this is just a 2834 * modified-emulation fault, and the PVF_WRITE bit isn't 2835 * changing. We've already set the cacheable bits based on 2836 * the assumption that we can write to this page. 2837 */ 2838 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W; 2839 PTE_SYNC(ptep); 2840 rv = 1; 2841 } else 2842 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 2843 /* 2844 * This looks like a good candidate for "page referenced" 2845 * emulation. 2846 */ 2847 struct pv_entry *pv; 2848 struct vm_page *pg; 2849 2850 /* Extract the physical address of the page */ 2851 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 2852 goto out; 2853 2854 /* Get the current flags for this page. */ 2855 simple_lock(&pg->mdpage.pvh_slock); 2856 2857 pv = pmap_find_pv(pg, pm, va); 2858 if (pv == NULL) { 2859 simple_unlock(&pg->mdpage.pvh_slock); 2860 goto out; 2861 } 2862 2863 pg->mdpage.pvh_attrs |= PVF_REF; 2864 pv->pv_flags |= PVF_REF; 2865 simple_unlock(&pg->mdpage.pvh_slock); 2866 2867 NPDEBUG(PDB_FOLLOW, 2868 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 2869 pm, va, pg->phys_addr)); 2870 2871 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; 2872 PTE_SYNC(ptep); 2873 rv = 1; 2874 } 2875 2876 /* 2877 * We know there is a valid mapping here, so simply 2878 * fix up the L1 if necessary. 2879 */ 2880 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 2881 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 2882 if (*pl1pd != l1pd) { 2883 *pl1pd = l1pd; 2884 PTE_SYNC(pl1pd); 2885 rv = 1; 2886 } 2887 2888 #ifdef CPU_SA110 2889 /* 2890 * There are bugs in the rev K SA110. This is a check for one 2891 * of them. 2892 */ 2893 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 2894 curcpu()->ci_arm_cpurev < 3) { 2895 /* Always current pmap */ 2896 if (l2pte_valid(pte)) { 2897 extern int kernel_debug; 2898 if (kernel_debug & 1) { 2899 struct proc *p = curlwp->l_proc; 2900 printf("prefetch_abort: page is already " 2901 "mapped - pte=%p *pte=%08x\n", ptep, pte); 2902 printf("prefetch_abort: pc=%08lx proc=%p " 2903 "process=%s\n", va, p, p->p_comm); 2904 printf("prefetch_abort: far=%08x fs=%x\n", 2905 cpu_faultaddress(), cpu_faultstatus()); 2906 } 2907 #ifdef DDB 2908 if (kernel_debug & 2) 2909 Debugger(); 2910 #endif 2911 rv = 1; 2912 } 2913 } 2914 #endif /* CPU_SA110 */ 2915 2916 #ifdef DEBUG 2917 /* 2918 * If 'rv == 0' at this point, it generally indicates that there is a 2919 * stale TLB entry for the faulting address. This happens when two or 2920 * more processes are sharing an L1. Since we don't flush the TLB on 2921 * a context switch between such processes, we can take domain faults 2922 * for mappings which exist at the same VA in both processes. EVEN IF 2923 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 2924 * example. 2925 * 2926 * This is extremely likely to happen if pmap_enter() updated the L1 2927 * entry for a recently entered mapping. In this case, the TLB is 2928 * flushed for the new mapping, but there may still be TLB entries for 2929 * other mappings belonging to other processes in the 1MB range 2930 * covered by the L1 entry. 2931 * 2932 * Since 'rv == 0', we know that the L1 already contains the correct 2933 * value, so the fault must be due to a stale TLB entry. 2934 * 2935 * Since we always need to flush the TLB anyway in the case where we 2936 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 2937 * stale TLB entries dynamically. 2938 * 2939 * However, the above condition can ONLY happen if the current L1 is 2940 * being shared. If it happens when the L1 is unshared, it indicates 2941 * that other parts of the pmap are not doing their job WRT managing 2942 * the TLB. 2943 */ 2944 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 2945 extern int last_fault_code; 2946 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 2947 pm, va, ftype); 2948 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 2949 l2, l2b, ptep, pl1pd); 2950 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 2951 pte, l1pd, last_fault_code); 2952 #ifdef DDB 2953 Debugger(); 2954 #endif 2955 } 2956 #endif 2957 2958 cpu_tlb_flushID_SE(va); 2959 cpu_cpwait(); 2960 2961 rv = 1; 2962 2963 out: 2964 pmap_release_pmap_lock(pm); 2965 PMAP_MAP_TO_HEAD_UNLOCK(); 2966 2967 return (rv); 2968 } 2969 2970 /* 2971 * pmap_collect: free resources held by a pmap 2972 * 2973 * => optional function. 2974 * => called when a process is swapped out to free memory. 2975 */ 2976 void 2977 pmap_collect(pmap_t pm) 2978 { 2979 /* 2980 * Nothing to do. 2981 * We don't even need to free-up the process' L1. 2982 */ 2983 } 2984 2985 /* 2986 * Routine: pmap_procwr 2987 * 2988 * Function: 2989 * Synchronize caches corresponding to [addr, addr+len) in p. 2990 * 2991 */ 2992 void 2993 pmap_procwr(struct proc *p, vaddr_t va, int len) 2994 { 2995 /* We only need to do anything if it is the current process. */ 2996 if (p == curproc) 2997 cpu_icache_sync_range(va, len); 2998 } 2999 3000 /* 3001 * Routine: pmap_unwire 3002 * Function: Clear the wired attribute for a map/virtual-address pair. 3003 * 3004 * In/out conditions: 3005 * The mapping must already exist in the pmap. 3006 */ 3007 void 3008 pmap_unwire(pmap_t pm, vaddr_t va) 3009 { 3010 struct l2_bucket *l2b; 3011 pt_entry_t *ptep, pte; 3012 struct vm_page *pg; 3013 paddr_t pa; 3014 3015 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 3016 3017 PMAP_MAP_TO_HEAD_LOCK(); 3018 pmap_acquire_pmap_lock(pm); 3019 3020 l2b = pmap_get_l2_bucket(pm, va); 3021 KDASSERT(l2b != NULL); 3022 3023 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3024 pte = *ptep; 3025 3026 /* Extract the physical address of the page */ 3027 pa = l2pte_pa(pte); 3028 3029 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3030 /* Update the wired bit in the pv entry for this page. */ 3031 simple_lock(&pg->mdpage.pvh_slock); 3032 (void) pmap_modify_pv(pg, pm, va, PVF_WIRED, 0); 3033 simple_unlock(&pg->mdpage.pvh_slock); 3034 } 3035 3036 pmap_release_pmap_lock(pm); 3037 PMAP_MAP_TO_HEAD_UNLOCK(); 3038 } 3039 3040 void 3041 pmap_activate(struct lwp *l) 3042 { 3043 pmap_t pm; 3044 struct pcb *pcb; 3045 int s; 3046 3047 pm = l->l_proc->p_vmspace->vm_map.pmap; 3048 pcb = &l->l_addr->u_pcb; 3049 3050 pmap_set_pcb_pagedir(pm, pcb); 3051 3052 if (l == curlwp) { 3053 u_int cur_dacr, cur_ttb; 3054 3055 __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb)); 3056 __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr)); 3057 3058 cur_ttb &= ~(L1_TABLE_SIZE - 1); 3059 3060 if (cur_ttb == (u_int)pcb->pcb_pagedir && 3061 cur_dacr == pcb->pcb_dacr) { 3062 /* 3063 * No need to switch address spaces. 3064 */ 3065 return; 3066 } 3067 3068 s = splhigh(); 3069 pmap_acquire_pmap_lock(pm); 3070 disable_interrupts(I32_bit | F32_bit); 3071 3072 /* 3073 * We MUST, I repeat, MUST fix up the L1 entry corresponding 3074 * to 'vector_page' in the incoming L1 table before switching 3075 * to it otherwise subsequent interrupts/exceptions (including 3076 * domain faults!) will jump into hyperspace. 3077 */ 3078 if (pcb->pcb_pl1vec) { 3079 *pcb->pcb_pl1vec = pcb->pcb_l1vec; 3080 /* 3081 * Don't need to PTE_SYNC() at this point since 3082 * cpu_setttb() is about to flush both the cache 3083 * and the TLB. 3084 */ 3085 } 3086 3087 cpu_domains(pcb->pcb_dacr); 3088 cpu_setttb(pcb->pcb_pagedir); 3089 3090 enable_interrupts(I32_bit | F32_bit); 3091 3092 /* 3093 * Flag any previous userland pmap as being NOT 3094 * resident in the cache/tlb. 3095 */ 3096 if (pmap_cache_state && pmap_cache_state != &pm->pm_cstate) 3097 pmap_cache_state->cs_all = 0; 3098 3099 /* 3100 * The new pmap, however, IS resident. 3101 */ 3102 pmap_cache_state = &pm->pm_cstate; 3103 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 3104 pmap_release_pmap_lock(pm); 3105 splx(s); 3106 } 3107 } 3108 3109 void 3110 pmap_deactivate(struct lwp *l) 3111 { 3112 } 3113 3114 void 3115 pmap_update(pmap_t pm) 3116 { 3117 3118 if (pm->pm_remove_all) { 3119 /* 3120 * Finish up the pmap_remove_all() optimisation by flushing 3121 * the TLB. 3122 */ 3123 pmap_tlb_flushID(pm); 3124 pm->pm_remove_all = FALSE; 3125 } 3126 3127 if (pmap_is_current(pm)) { 3128 /* 3129 * If we're dealing with a current userland pmap, move its L1 3130 * to the end of the LRU. 3131 */ 3132 if (pm != pmap_kernel()) 3133 pmap_use_l1(pm); 3134 3135 /* 3136 * We can assume we're done with frobbing the cache/tlb for 3137 * now. Make sure any future pmap ops don't skip cache/tlb 3138 * flushes. 3139 */ 3140 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 3141 } 3142 3143 /* 3144 * make sure TLB/cache operations have completed. 3145 */ 3146 cpu_cpwait(); 3147 } 3148 3149 void 3150 pmap_remove_all(pmap_t pm) 3151 { 3152 3153 /* 3154 * The vmspace described by this pmap is about to be torn down. 3155 * Until pmap_update() is called, UVM will only make calls 3156 * to pmap_remove(). We can make life much simpler by flushing 3157 * the cache now, and deferring TLB invalidation to pmap_update(). 3158 */ 3159 pmap_idcache_wbinv_all(pm); 3160 pm->pm_remove_all = TRUE; 3161 } 3162 3163 /* 3164 * Retire the given physical map from service. 3165 * Should only be called if the map contains no valid mappings. 3166 */ 3167 void 3168 pmap_destroy(pmap_t pm) 3169 { 3170 u_int count; 3171 3172 if (pm == NULL) 3173 return; 3174 3175 if (pm->pm_remove_all) { 3176 pmap_tlb_flushID(pm); 3177 pm->pm_remove_all = FALSE; 3178 } 3179 3180 /* 3181 * Drop reference count 3182 */ 3183 simple_lock(&pm->pm_lock); 3184 count = --pm->pm_obj.uo_refs; 3185 simple_unlock(&pm->pm_lock); 3186 if (count > 0) { 3187 if (pmap_is_current(pm)) { 3188 if (pm != pmap_kernel()) 3189 pmap_use_l1(pm); 3190 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 3191 } 3192 return; 3193 } 3194 3195 /* 3196 * reference count is zero, free pmap resources and then free pmap. 3197 */ 3198 3199 if (vector_page < KERNEL_BASE) { 3200 /* Remove the vector page mapping */ 3201 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 3202 pmap_update(pm); 3203 } 3204 3205 LIST_REMOVE(pm, pm_list); 3206 3207 pmap_free_l1(pm); 3208 3209 /* return the pmap to the pool */ 3210 pool_cache_put(&pmap_pmap_cache, pm); 3211 } 3212 3213 3214 /* 3215 * void pmap_reference(pmap_t pm) 3216 * 3217 * Add a reference to the specified pmap. 3218 */ 3219 void 3220 pmap_reference(pmap_t pm) 3221 { 3222 3223 if (pm == NULL) 3224 return; 3225 3226 pmap_use_l1(pm); 3227 3228 simple_lock(&pm->pm_lock); 3229 pm->pm_obj.uo_refs++; 3230 simple_unlock(&pm->pm_lock); 3231 } 3232 3233 /* 3234 * pmap_zero_page() 3235 * 3236 * Zero a given physical page by mapping it at a page hook point. 3237 * In doing the zero page op, the page we zero is mapped cachable, as with 3238 * StrongARM accesses to non-cached pages are non-burst making writing 3239 * _any_ bulk data very slow. 3240 */ 3241 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 3242 void 3243 pmap_zero_page_generic(paddr_t phys) 3244 { 3245 #ifdef DEBUG 3246 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 3247 3248 if (pg->mdpage.pvh_list != NULL) 3249 panic("pmap_zero_page: page has mappings"); 3250 #endif 3251 3252 KDASSERT((phys & PGOFSET) == 0); 3253 3254 /* 3255 * Hook in the page, zero it, and purge the cache for that 3256 * zeroed page. Invalidate the TLB as needed. 3257 */ 3258 *cdst_pte = L2_S_PROTO | phys | 3259 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 3260 PTE_SYNC(cdst_pte); 3261 cpu_tlb_flushD_SE(cdstp); 3262 cpu_cpwait(); 3263 bzero_page(cdstp); 3264 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 3265 } 3266 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 3267 3268 #if ARM_MMU_XSCALE == 1 3269 void 3270 pmap_zero_page_xscale(paddr_t phys) 3271 { 3272 #ifdef DEBUG 3273 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 3274 3275 if (pg->mdpage.pvh_list != NULL) 3276 panic("pmap_zero_page: page has mappings"); 3277 #endif 3278 3279 KDASSERT((phys & PGOFSET) == 0); 3280 3281 /* 3282 * Hook in the page, zero it, and purge the cache for that 3283 * zeroed page. Invalidate the TLB as needed. 3284 */ 3285 *cdst_pte = L2_S_PROTO | phys | 3286 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 3287 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 3288 PTE_SYNC(cdst_pte); 3289 cpu_tlb_flushD_SE(cdstp); 3290 cpu_cpwait(); 3291 bzero_page(cdstp); 3292 xscale_cache_clean_minidata(); 3293 } 3294 #endif /* ARM_MMU_XSCALE == 1 */ 3295 3296 /* pmap_pageidlezero() 3297 * 3298 * The same as above, except that we assume that the page is not 3299 * mapped. This means we never have to flush the cache first. Called 3300 * from the idle loop. 3301 */ 3302 boolean_t 3303 pmap_pageidlezero(paddr_t phys) 3304 { 3305 unsigned int i; 3306 int *ptr; 3307 boolean_t rv = TRUE; 3308 #ifdef DEBUG 3309 struct vm_page *pg; 3310 3311 pg = PHYS_TO_VM_PAGE(phys); 3312 if (pg->mdpage.pvh_list != NULL) 3313 panic("pmap_pageidlezero: page has mappings"); 3314 #endif 3315 3316 KDASSERT((phys & PGOFSET) == 0); 3317 3318 /* 3319 * Hook in the page, zero it, and purge the cache for that 3320 * zeroed page. Invalidate the TLB as needed. 3321 */ 3322 *cdst_pte = L2_S_PROTO | phys | 3323 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 3324 PTE_SYNC(cdst_pte); 3325 cpu_tlb_flushD_SE(cdstp); 3326 cpu_cpwait(); 3327 3328 for (i = 0, ptr = (int *)cdstp; 3329 i < (PAGE_SIZE / sizeof(int)); i++) { 3330 if (sched_whichqs != 0) { 3331 /* 3332 * A process has become ready. Abort now, 3333 * so we don't keep it waiting while we 3334 * do slow memory access to finish this 3335 * page. 3336 */ 3337 rv = FALSE; 3338 break; 3339 } 3340 *ptr++ = 0; 3341 } 3342 3343 if (rv) 3344 /* 3345 * if we aborted we'll rezero this page again later so don't 3346 * purge it unless we finished it 3347 */ 3348 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 3349 3350 return (rv); 3351 } 3352 3353 /* 3354 * pmap_copy_page() 3355 * 3356 * Copy one physical page into another, by mapping the pages into 3357 * hook points. The same comment regarding cachability as in 3358 * pmap_zero_page also applies here. 3359 */ 3360 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 3361 void 3362 pmap_copy_page_generic(paddr_t src, paddr_t dst) 3363 { 3364 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 3365 #ifdef DEBUG 3366 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 3367 3368 if (dst_pg->mdpage.pvh_list != NULL) 3369 panic("pmap_copy_page: dst page has mappings"); 3370 #endif 3371 3372 KDASSERT((src & PGOFSET) == 0); 3373 KDASSERT((dst & PGOFSET) == 0); 3374 3375 /* 3376 * Clean the source page. Hold the source page's lock for 3377 * the duration of the copy so that no other mappings can 3378 * be created while we have a potentially aliased mapping. 3379 */ 3380 simple_lock(&src_pg->mdpage.pvh_slock); 3381 (void) pmap_clean_page(src_pg->mdpage.pvh_list, TRUE); 3382 3383 /* 3384 * Map the pages into the page hook points, copy them, and purge 3385 * the cache for the appropriate page. Invalidate the TLB 3386 * as required. 3387 */ 3388 *csrc_pte = L2_S_PROTO | src | 3389 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode; 3390 PTE_SYNC(csrc_pte); 3391 *cdst_pte = L2_S_PROTO | dst | 3392 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 3393 PTE_SYNC(cdst_pte); 3394 cpu_tlb_flushD_SE(csrcp); 3395 cpu_tlb_flushD_SE(cdstp); 3396 cpu_cpwait(); 3397 bcopy_page(csrcp, cdstp); 3398 cpu_dcache_inv_range(csrcp, PAGE_SIZE); 3399 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 3400 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 3401 } 3402 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 3403 3404 #if ARM_MMU_XSCALE == 1 3405 void 3406 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 3407 { 3408 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 3409 #ifdef DEBUG 3410 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 3411 3412 if (dst_pg->mdpage.pvh_list != NULL) 3413 panic("pmap_copy_page: dst page has mappings"); 3414 #endif 3415 3416 KDASSERT((src & PGOFSET) == 0); 3417 KDASSERT((dst & PGOFSET) == 0); 3418 3419 /* 3420 * Clean the source page. Hold the source page's lock for 3421 * the duration of the copy so that no other mappings can 3422 * be created while we have a potentially aliased mapping. 3423 */ 3424 simple_lock(&src_pg->mdpage.pvh_slock); 3425 (void) pmap_clean_page(src_pg->mdpage.pvh_list, TRUE); 3426 3427 /* 3428 * Map the pages into the page hook points, copy them, and purge 3429 * the cache for the appropriate page. Invalidate the TLB 3430 * as required. 3431 */ 3432 *csrc_pte = L2_S_PROTO | src | 3433 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 3434 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 3435 PTE_SYNC(csrc_pte); 3436 *cdst_pte = L2_S_PROTO | dst | 3437 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 3438 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 3439 PTE_SYNC(cdst_pte); 3440 cpu_tlb_flushD_SE(csrcp); 3441 cpu_tlb_flushD_SE(cdstp); 3442 cpu_cpwait(); 3443 bcopy_page(csrcp, cdstp); 3444 simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */ 3445 xscale_cache_clean_minidata(); 3446 } 3447 #endif /* ARM_MMU_XSCALE == 1 */ 3448 3449 /* 3450 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 3451 * 3452 * Return the start and end addresses of the kernel's virtual space. 3453 * These values are setup in pmap_bootstrap and are updated as pages 3454 * are allocated. 3455 */ 3456 void 3457 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 3458 { 3459 *start = virtual_avail; 3460 *end = virtual_end; 3461 } 3462 3463 /* 3464 * Helper function for pmap_grow_l2_bucket() 3465 */ 3466 static __inline int 3467 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 3468 { 3469 struct l2_bucket *l2b; 3470 pt_entry_t *ptep; 3471 paddr_t pa; 3472 3473 if (uvm.page_init_done == FALSE) { 3474 if (uvm_page_physget(&pa) == FALSE) 3475 return (1); 3476 } else { 3477 struct vm_page *pg; 3478 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 3479 if (pg == NULL) 3480 return (1); 3481 pa = VM_PAGE_TO_PHYS(pg); 3482 } 3483 3484 if (pap) 3485 *pap = pa; 3486 3487 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3488 KDASSERT(l2b != NULL); 3489 3490 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3491 *ptep = L2_S_PROTO | pa | cache_mode | 3492 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 3493 PTE_SYNC(ptep); 3494 memset((void *)va, 0, PAGE_SIZE); 3495 return (0); 3496 } 3497 3498 /* 3499 * This is the same as pmap_alloc_l2_bucket(), except that it is only 3500 * used by pmap_growkernel(). 3501 */ 3502 static __inline struct l2_bucket * 3503 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 3504 { 3505 struct l2_dtable *l2; 3506 struct l2_bucket *l2b; 3507 u_short l1idx; 3508 vaddr_t nva; 3509 3510 l1idx = L1_IDX(va); 3511 3512 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 3513 /* 3514 * No mapping at this address, as there is 3515 * no entry in the L1 table. 3516 * Need to allocate a new l2_dtable. 3517 */ 3518 nva = pmap_kernel_l2dtable_kva; 3519 if ((nva & PGOFSET) == 0) { 3520 /* 3521 * Need to allocate a backing page 3522 */ 3523 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 3524 return (NULL); 3525 } 3526 3527 l2 = (struct l2_dtable *)nva; 3528 nva += sizeof(struct l2_dtable); 3529 3530 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 3531 /* 3532 * The new l2_dtable straddles a page boundary. 3533 * Map in another page to cover it. 3534 */ 3535 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 3536 return (NULL); 3537 } 3538 3539 pmap_kernel_l2dtable_kva = nva; 3540 3541 /* 3542 * Link it into the parent pmap 3543 */ 3544 pm->pm_l2[L2_IDX(l1idx)] = l2; 3545 } 3546 3547 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3548 3549 /* 3550 * Fetch pointer to the L2 page table associated with the address. 3551 */ 3552 if (l2b->l2b_kva == NULL) { 3553 pt_entry_t *ptep; 3554 3555 /* 3556 * No L2 page table has been allocated. Chances are, this 3557 * is because we just allocated the l2_dtable, above. 3558 */ 3559 nva = pmap_kernel_l2ptp_kva; 3560 ptep = (pt_entry_t *)nva; 3561 if ((nva & PGOFSET) == 0) { 3562 /* 3563 * Need to allocate a backing page 3564 */ 3565 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 3566 &pmap_kernel_l2ptp_phys)) 3567 return (NULL); 3568 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 3569 } 3570 3571 l2->l2_occupancy++; 3572 l2b->l2b_kva = ptep; 3573 l2b->l2b_l1idx = l1idx; 3574 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 3575 3576 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 3577 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 3578 } 3579 3580 return (l2b); 3581 } 3582 3583 vaddr_t 3584 pmap_growkernel(vaddr_t maxkvaddr) 3585 { 3586 pmap_t kpm = pmap_kernel(); 3587 struct l1_ttable *l1; 3588 struct l2_bucket *l2b; 3589 pd_entry_t *pl1pd; 3590 int s; 3591 3592 if (maxkvaddr <= pmap_curmaxkvaddr) 3593 goto out; /* we are OK */ 3594 3595 NPDEBUG(PDB_GROWKERN, 3596 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 3597 pmap_curmaxkvaddr, maxkvaddr)); 3598 3599 KDASSERT(maxkvaddr <= virtual_end); 3600 3601 /* 3602 * whoops! we need to add kernel PTPs 3603 */ 3604 3605 s = splhigh(); /* to be safe */ 3606 simple_lock(&kpm->pm_lock); 3607 3608 /* Map 1MB at a time */ 3609 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 3610 3611 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 3612 KDASSERT(l2b != NULL); 3613 3614 /* Distribute new L1 entry to all other L1s */ 3615 SLIST_FOREACH(l1, &l1_list, l1_link) { 3616 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 3617 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 3618 L1_C_PROTO; 3619 PTE_SYNC(pl1pd); 3620 } 3621 } 3622 3623 /* 3624 * flush out the cache, expensive but growkernel will happen so 3625 * rarely 3626 */ 3627 cpu_dcache_wbinv_all(); 3628 cpu_tlb_flushD(); 3629 cpu_cpwait(); 3630 3631 simple_unlock(&kpm->pm_lock); 3632 splx(s); 3633 3634 out: 3635 return (pmap_curmaxkvaddr); 3636 } 3637 3638 /************************ Utility routines ****************************/ 3639 3640 /* 3641 * vector_page_setprot: 3642 * 3643 * Manipulate the protection of the vector page. 3644 */ 3645 void 3646 vector_page_setprot(int prot) 3647 { 3648 struct l2_bucket *l2b; 3649 pt_entry_t *ptep; 3650 3651 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 3652 KDASSERT(l2b != NULL); 3653 3654 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 3655 3656 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 3657 PTE_SYNC(ptep); 3658 cpu_tlb_flushD_SE(vector_page); 3659 cpu_cpwait(); 3660 } 3661 3662 /* 3663 * This is used to stuff certain critical values into the PCB where they 3664 * can be accessed quickly from cpu_switch() et al. 3665 */ 3666 void 3667 pmap_set_pcb_pagedir(pmap_t pm, struct pcb *pcb) 3668 { 3669 struct l2_bucket *l2b; 3670 3671 KDASSERT(pm->pm_l1); 3672 3673 pcb->pcb_pagedir = pm->pm_l1->l1_physaddr; 3674 pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 3675 (DOMAIN_CLIENT << (pm->pm_domain * 2)); 3676 pcb->pcb_cstate = (void *)&pm->pm_cstate; 3677 3678 if (vector_page < KERNEL_BASE) { 3679 pcb->pcb_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 3680 l2b = pmap_get_l2_bucket(pm, vector_page); 3681 pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO | 3682 L1_C_DOM(pm->pm_domain); 3683 } else 3684 pcb->pcb_pl1vec = NULL; 3685 } 3686 3687 /* 3688 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 3689 * Returns TRUE if the mapping exists, else FALSE. 3690 * 3691 * NOTE: This function is only used by a couple of arm-specific modules. 3692 * It is not safe to take any pmap locks here, since we could be right 3693 * in the middle of debugging the pmap anyway... 3694 * 3695 * It is possible for this routine to return FALSE even though a valid 3696 * mapping does exist. This is because we don't lock, so the metadata 3697 * state may be inconsistent. 3698 * 3699 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 3700 * a "section" mapping. 3701 */ 3702 boolean_t 3703 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 3704 { 3705 struct l2_dtable *l2; 3706 pd_entry_t *pl1pd, l1pd; 3707 pt_entry_t *ptep; 3708 u_short l1idx; 3709 3710 if (pm->pm_l1 == NULL) 3711 return (FALSE); 3712 3713 l1idx = L1_IDX(va); 3714 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3715 l1pd = *pl1pd; 3716 3717 if (l1pte_section_p(l1pd)) { 3718 *ptp = NULL; 3719 return (TRUE); 3720 } 3721 3722 if (pm->pm_l2 == NULL) 3723 return (FALSE); 3724 3725 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3726 3727 if (l2 == NULL || 3728 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3729 return (FALSE); 3730 } 3731 3732 *ptp = &ptep[l2pte_index(va)]; 3733 return (TRUE); 3734 } 3735 3736 boolean_t 3737 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 3738 { 3739 u_short l1idx; 3740 3741 if (pm->pm_l1 == NULL) 3742 return (FALSE); 3743 3744 l1idx = L1_IDX(va); 3745 *pdp = &pm->pm_l1->l1_kva[l1idx]; 3746 3747 return (TRUE); 3748 } 3749 3750 /************************ Bootstrapping routines ****************************/ 3751 3752 static void 3753 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 3754 { 3755 int i; 3756 3757 l1->l1_kva = l1pt; 3758 l1->l1_domain_use_count = 0; 3759 l1->l1_domain_first = 0; 3760 3761 for (i = 0; i < PMAP_DOMAINS; i++) 3762 l1->l1_domain_free[i] = i + 1; 3763 3764 /* 3765 * Copy the kernel's L1 entries to each new L1. 3766 */ 3767 if (pmap_initialized) 3768 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 3769 3770 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 3771 &l1->l1_physaddr) == FALSE) 3772 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 3773 3774 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 3775 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 3776 } 3777 3778 /* 3779 * pmap_bootstrap() is called from the board-specific initarm() routine 3780 * once the kernel L1/L2 descriptors tables have been set up. 3781 * 3782 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 3783 * spread over a number of disparate files/functions. 3784 * 3785 * We are passed the following parameters 3786 * - kernel_l1pt 3787 * This is a pointer to the base of the kernel's L1 translation table. 3788 * - vstart 3789 * 1MB-aligned start of managed kernel virtual memory. 3790 * - vend 3791 * 1MB-aligned end of managed kernel virtual memory. 3792 * 3793 * We use the first parameter to build the metadata (struct l1_ttable and 3794 * struct l2_dtable) necessary to track kernel mappings. 3795 */ 3796 #define PMAP_STATIC_L2_SIZE 16 3797 void 3798 pmap_bootstrap(pd_entry_t *kernel_l1pt, vaddr_t vstart, vaddr_t vend) 3799 { 3800 static struct l1_ttable static_l1; 3801 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 3802 struct l1_ttable *l1 = &static_l1; 3803 struct l2_dtable *l2; 3804 struct l2_bucket *l2b; 3805 pmap_t pm = pmap_kernel(); 3806 pd_entry_t pde; 3807 pt_entry_t *ptep; 3808 paddr_t pa; 3809 vaddr_t va; 3810 vsize_t size; 3811 int l1idx, l2idx, l2next = 0; 3812 3813 /* 3814 * Initialise the kernel pmap object 3815 */ 3816 pm->pm_l1 = l1; 3817 pm->pm_domain = PMAP_DOMAIN_KERNEL; 3818 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 3819 simple_lock_init(&pm->pm_lock); 3820 pm->pm_obj.pgops = NULL; 3821 TAILQ_INIT(&pm->pm_obj.memq); 3822 pm->pm_obj.uo_npages = 0; 3823 pm->pm_obj.uo_refs = 1; 3824 3825 /* 3826 * Scan the L1 translation table created by initarm() and create 3827 * the required metadata for all valid mappings found in it. 3828 */ 3829 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 3830 pde = kernel_l1pt[l1idx]; 3831 3832 /* 3833 * We're only interested in Coarse mappings. 3834 * pmap_extract() can deal with section mappings without 3835 * recourse to checking L2 metadata. 3836 */ 3837 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 3838 continue; 3839 3840 /* 3841 * Lookup the KVA of this L2 descriptor table 3842 */ 3843 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 3844 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 3845 if (ptep == NULL) { 3846 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 3847 (u_int)l1idx << L1_S_SHIFT, pa); 3848 } 3849 3850 /* 3851 * Fetch the associated L2 metadata structure. 3852 * Allocate a new one if necessary. 3853 */ 3854 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 3855 if (l2next == PMAP_STATIC_L2_SIZE) 3856 panic("pmap_bootstrap: out of static L2s"); 3857 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 3858 } 3859 3860 /* 3861 * One more L1 slot tracked... 3862 */ 3863 l2->l2_occupancy++; 3864 3865 /* 3866 * Fill in the details of the L2 descriptor in the 3867 * appropriate bucket. 3868 */ 3869 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3870 l2b->l2b_kva = ptep; 3871 l2b->l2b_phys = pa; 3872 l2b->l2b_l1idx = l1idx; 3873 3874 /* 3875 * Establish an initial occupancy count for this descriptor 3876 */ 3877 for (l2idx = 0; 3878 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 3879 l2idx++) { 3880 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 3881 l2b->l2b_occupancy++; 3882 } 3883 } 3884 3885 /* 3886 * Make sure the descriptor itself has the correct cache mode. 3887 * If not, fix it, but bitch about the problem. Port-meisters 3888 * should consider this a clue to fix up their initarm() 3889 * function. :) 3890 */ 3891 if (pmap_set_pt_cache_mode(kernel_l1pt, (vaddr_t)ptep)) { 3892 printf("pmap_bootstrap: WARNING! wrong cache mode for " 3893 "L2 pte @ %p\n", ptep); 3894 } 3895 } 3896 3897 /* 3898 * Ensure the primary (kernel) L1 has the correct cache mode for 3899 * a page table. Bitch if it is not correctly set. 3900 */ 3901 for (va = (vaddr_t)kernel_l1pt; 3902 va < ((vaddr_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 3903 if (pmap_set_pt_cache_mode(kernel_l1pt, va)) 3904 printf("pmap_bootstrap: WARNING! wrong cache mode for " 3905 "primary L1 @ 0x%lx\n", va); 3906 } 3907 3908 cpu_dcache_wbinv_all(); 3909 cpu_tlb_flushID(); 3910 cpu_cpwait(); 3911 3912 /* 3913 * now we allocate the "special" VAs which are used for tmp mappings 3914 * by the pmap (and other modules). we allocate the VAs by advancing 3915 * virtual_avail (note that there are no pages mapped at these VAs). 3916 * 3917 * Managed KVM space start from wherever initarm() tells us. 3918 */ 3919 virtual_avail = vstart; 3920 virtual_end = vend; 3921 3922 pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte); 3923 pmap_set_pt_cache_mode(kernel_l1pt, (vaddr_t)csrc_pte); 3924 pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte); 3925 pmap_set_pt_cache_mode(kernel_l1pt, (vaddr_t)cdst_pte); 3926 pmap_alloc_specials(&virtual_avail, 1, (vaddr_t *)&memhook, NULL); 3927 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 3928 (vaddr_t *)&msgbufaddr, NULL); 3929 3930 /* 3931 * Allocate a range of kernel virtual address space to be used 3932 * for L2 descriptor tables and metadata allocation in 3933 * pmap_growkernel(). 3934 */ 3935 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 3936 pmap_alloc_specials(&virtual_avail, 3937 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 3938 &pmap_kernel_l2ptp_kva, NULL); 3939 3940 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 3941 pmap_alloc_specials(&virtual_avail, 3942 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 3943 &pmap_kernel_l2dtable_kva, NULL); 3944 3945 /* 3946 * init the static-global locks and global pmap list. 3947 */ 3948 #if defined(MULTIPROCESSOR) || defined(LOCKDEBUG) 3949 spinlockinit(&pmap_main_lock, "pmaplk", 0); 3950 #endif 3951 3952 /* 3953 * We can now initialise the first L1's metadata. 3954 */ 3955 SLIST_INIT(&l1_list); 3956 TAILQ_INIT(&l1_lru_list); 3957 simple_lock_init(&l1_lru_lock); 3958 pmap_init_l1(l1, kernel_l1pt); 3959 3960 /* 3961 * Initialize the pmap pool and cache 3962 */ 3963 pool_init(&pmap_pmap_pool, sizeof(struct pmap), 0, 0, 0, "pmappl", 3964 &pool_allocator_nointr); 3965 pool_cache_init(&pmap_pmap_cache, &pmap_pmap_pool, 3966 pmap_pmap_ctor, NULL, NULL); 3967 LIST_INIT(&pmap_pmaps); 3968 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 3969 3970 /* 3971 * Initialize the pv pool. 3972 */ 3973 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 3974 &pmap_bootstrap_pv_allocator); 3975 3976 /* 3977 * Initialize the L2 dtable pool and cache. 3978 */ 3979 pool_init(&pmap_l2dtable_pool, sizeof(struct l2_dtable), 0, 0, 0, 3980 "l2dtblpl", NULL); 3981 pool_cache_init(&pmap_l2dtable_cache, &pmap_l2dtable_pool, 3982 pmap_l2dtable_ctor, NULL, NULL); 3983 3984 /* 3985 * Initialise the L2 descriptor table pool and cache 3986 */ 3987 pool_init(&pmap_l2ptp_pool, L2_TABLE_SIZE_REAL, 0, L2_TABLE_SIZE_REAL, 3988 0, "l2ptppl", NULL); 3989 pool_cache_init(&pmap_l2ptp_cache, &pmap_l2ptp_pool, 3990 pmap_l2ptp_ctor, NULL, NULL); 3991 3992 cpu_dcache_wbinv_all(); 3993 } 3994 3995 static int 3996 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 3997 { 3998 pd_entry_t *pdep, pde; 3999 pt_entry_t *ptep, pte; 4000 vaddr_t pa; 4001 int rv = 0; 4002 4003 /* 4004 * Make sure the descriptor itself has the correct cache mode 4005 */ 4006 pdep = &kl1[L1_IDX(va)]; 4007 pde = *pdep; 4008 4009 if (l1pte_section_p(pde)) { 4010 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 4011 *pdep = (pde & ~L1_S_CACHE_MASK) | 4012 pte_l1_s_cache_mode_pt; 4013 PTE_SYNC(pdep); 4014 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 4015 rv = 1; 4016 } 4017 } else { 4018 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 4019 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 4020 if (ptep == NULL) 4021 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 4022 4023 ptep = &ptep[l2pte_index(va)]; 4024 pte = *ptep; 4025 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 4026 *ptep = (pte & ~L2_S_CACHE_MASK) | 4027 pte_l2_s_cache_mode_pt; 4028 PTE_SYNC(ptep); 4029 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 4030 rv = 1; 4031 } 4032 } 4033 4034 return (rv); 4035 } 4036 4037 static void 4038 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 4039 { 4040 vaddr_t va = *availp; 4041 struct l2_bucket *l2b; 4042 4043 if (ptep) { 4044 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4045 if (l2b == NULL) 4046 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 4047 4048 if (ptep) 4049 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 4050 } 4051 4052 *vap = va; 4053 *availp = va + (PAGE_SIZE * pages); 4054 } 4055 4056 void 4057 pmap_init(void) 4058 { 4059 extern int physmem; 4060 4061 /* 4062 * Set the available memory vars - These do not map to real memory 4063 * addresses and cannot as the physical memory is fragmented. 4064 * They are used by ps for %mem calculations. 4065 * One could argue whether this should be the entire memory or just 4066 * the memory that is useable in a user process. 4067 */ 4068 avail_start = 0; 4069 avail_end = physmem * PAGE_SIZE; 4070 4071 /* 4072 * Now we need to free enough pv_entry structures to allow us to get 4073 * the kmem_map/kmem_object allocated and inited (done after this 4074 * function is finished). to do this we allocate one bootstrap page out 4075 * of kernel_map and use it to provide an initial pool of pv_entry 4076 * structures. we never free this page. 4077 */ 4078 pool_setlowat(&pmap_pv_pool, 4079 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 4080 4081 pmap_initialized = TRUE; 4082 } 4083 4084 static vaddr_t last_bootstrap_page = 0; 4085 static void *free_bootstrap_pages = NULL; 4086 4087 static void * 4088 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 4089 { 4090 extern void *pool_page_alloc(struct pool *, int); 4091 vaddr_t new_page; 4092 void *rv; 4093 4094 if (pmap_initialized) 4095 return (pool_page_alloc(pp, flags)); 4096 4097 if (free_bootstrap_pages) { 4098 rv = free_bootstrap_pages; 4099 free_bootstrap_pages = *((void **)rv); 4100 return (rv); 4101 } 4102 4103 new_page = uvm_km_kmemalloc(kernel_map, NULL, PAGE_SIZE, 4104 (flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT); 4105 4106 KASSERT(new_page > last_bootstrap_page); 4107 last_bootstrap_page = new_page; 4108 return ((void *)new_page); 4109 } 4110 4111 static void 4112 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 4113 { 4114 extern void pool_page_free(struct pool *, void *); 4115 4116 if (pmap_initialized) { 4117 pool_page_free(pp, v); 4118 return; 4119 } 4120 4121 if ((vaddr_t)v < last_bootstrap_page) { 4122 *((void **)v) = free_bootstrap_pages; 4123 free_bootstrap_pages = v; 4124 return; 4125 } 4126 } 4127 4128 /* 4129 * pmap_postinit() 4130 * 4131 * This routine is called after the vm and kmem subsystems have been 4132 * initialised. This allows the pmap code to perform any initialisation 4133 * that can only be done one the memory allocation is in place. 4134 */ 4135 void 4136 pmap_postinit(void) 4137 { 4138 extern paddr_t physical_start, physical_end; 4139 struct l2_bucket *l2b; 4140 struct l1_ttable *l1; 4141 struct pglist plist; 4142 struct vm_page *m; 4143 pd_entry_t *pl1pt; 4144 pt_entry_t *ptep, pte; 4145 vaddr_t va, eva; 4146 u_int loop, needed; 4147 int error; 4148 4149 pool_setlowat(&pmap_l2ptp_pool, 4150 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 4151 pool_setlowat(&pmap_l2dtable_pool, 4152 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 4153 4154 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 4155 needed -= 1; 4156 4157 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 4158 4159 for (loop = 0; loop < needed; loop++, l1++) { 4160 /* Allocate a L1 page table */ 4161 va = uvm_km_valloc(kernel_map, L1_TABLE_SIZE); 4162 if (va == 0) 4163 panic("Cannot allocate L1 KVM"); 4164 4165 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 4166 physical_end, L1_TABLE_SIZE, 0, &plist, 1, M_WAITOK); 4167 if (error) 4168 panic("Cannot allocate L1 physical pages"); 4169 4170 m = TAILQ_FIRST(&plist); 4171 eva = va + L1_TABLE_SIZE; 4172 pl1pt = (pd_entry_t *)va; 4173 4174 while (m && va < eva) { 4175 paddr_t pa = VM_PAGE_TO_PHYS(m); 4176 4177 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE); 4178 4179 /* 4180 * Make sure the L1 descriptor table is mapped 4181 * with the cache-mode set to write-through. 4182 */ 4183 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4184 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4185 pte = *ptep; 4186 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 4187 *ptep = pte; 4188 PTE_SYNC(ptep); 4189 cpu_tlb_flushD_SE(va); 4190 4191 va += PAGE_SIZE; 4192 m = m->pageq.tqe_next; 4193 } 4194 4195 #ifdef DIAGNOSTIC 4196 if (m) 4197 panic("pmap_alloc_l1pt: pglist not empty"); 4198 #endif /* DIAGNOSTIC */ 4199 4200 pmap_init_l1(l1, pl1pt); 4201 } 4202 4203 #ifdef DEBUG 4204 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 4205 needed); 4206 #endif 4207 } 4208 4209 /* 4210 * Note that the following routines are used by board-specific initialisation 4211 * code to configure the initial kernel page tables. 4212 * 4213 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 4214 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 4215 * behaviour of the old pmap, and provides an easy migration path for 4216 * initial bring-up of the new pmap on existing ports. Fortunately, 4217 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 4218 * will be deprecated. 4219 * 4220 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 4221 * tables. 4222 */ 4223 4224 /* 4225 * This list exists for the benefit of pmap_map_chunk(). It keeps track 4226 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 4227 * find them as necessary. 4228 * 4229 * Note that the data on this list MUST remain valid after initarm() returns, 4230 * as pmap_bootstrap() uses it to contruct L2 table metadata. 4231 */ 4232 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 4233 4234 static vaddr_t 4235 kernel_pt_lookup(paddr_t pa) 4236 { 4237 pv_addr_t *pv; 4238 4239 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 4240 #ifndef ARM32_NEW_VM_LAYOUT 4241 if (pv->pv_pa == (pa & ~PGOFSET)) 4242 return (pv->pv_va | (pa & PGOFSET)); 4243 #else 4244 if (pv->pv_pa == pa) 4245 return (pv->pv_va); 4246 #endif 4247 } 4248 return (0); 4249 } 4250 4251 /* 4252 * pmap_map_section: 4253 * 4254 * Create a single section mapping. 4255 */ 4256 void 4257 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 4258 { 4259 pd_entry_t *pde = (pd_entry_t *) l1pt; 4260 pd_entry_t fl; 4261 4262 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 4263 4264 switch (cache) { 4265 case PTE_NOCACHE: 4266 default: 4267 fl = 0; 4268 break; 4269 4270 case PTE_CACHE: 4271 fl = pte_l1_s_cache_mode; 4272 break; 4273 4274 case PTE_PAGETABLE: 4275 fl = pte_l1_s_cache_mode_pt; 4276 break; 4277 } 4278 4279 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4280 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 4281 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4282 } 4283 4284 /* 4285 * pmap_map_entry: 4286 * 4287 * Create a single page mapping. 4288 */ 4289 void 4290 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 4291 { 4292 pd_entry_t *pde = (pd_entry_t *) l1pt; 4293 pt_entry_t fl; 4294 pt_entry_t *pte; 4295 4296 KASSERT(((va | pa) & PGOFSET) == 0); 4297 4298 switch (cache) { 4299 case PTE_NOCACHE: 4300 default: 4301 fl = 0; 4302 break; 4303 4304 case PTE_CACHE: 4305 fl = pte_l2_s_cache_mode; 4306 break; 4307 4308 case PTE_PAGETABLE: 4309 fl = pte_l2_s_cache_mode_pt; 4310 break; 4311 } 4312 4313 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4314 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 4315 4316 #ifndef ARM32_NEW_VM_LAYOUT 4317 pte = (pt_entry_t *) 4318 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 4319 #else 4320 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4321 #endif 4322 if (pte == NULL) 4323 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 4324 4325 #ifndef ARM32_NEW_VM_LAYOUT 4326 pte[(va >> PGSHIFT) & 0x3ff] = 4327 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 4328 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 4329 #else 4330 pte[l2pte_index(va)] = 4331 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 4332 PTE_SYNC(&pte[l2pte_index(va)]); 4333 #endif 4334 } 4335 4336 /* 4337 * pmap_link_l2pt: 4338 * 4339 * Link the L2 page table specified by "l2pv" into the L1 4340 * page table at the slot for "va". 4341 */ 4342 void 4343 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 4344 { 4345 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 4346 u_int slot = va >> L1_S_SHIFT; 4347 4348 #ifndef ARM32_NEW_VM_LAYOUT 4349 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 4350 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 4351 #endif 4352 4353 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 4354 4355 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 4356 #ifdef ARM32_NEW_VM_LAYOUT 4357 PTE_SYNC(&pde[slot]); 4358 #else 4359 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 4360 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 4361 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 4362 PTE_SYNC_RANGE(&pde[slot + 0], 4); 4363 #endif 4364 4365 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 4366 } 4367 4368 /* 4369 * pmap_map_chunk: 4370 * 4371 * Map a chunk of memory using the most efficient mappings 4372 * possible (section, large page, small page) into the 4373 * provided L1 and L2 tables at the specified virtual address. 4374 */ 4375 vsize_t 4376 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 4377 int prot, int cache) 4378 { 4379 pd_entry_t *pde = (pd_entry_t *) l1pt; 4380 pt_entry_t *pte, f1, f2s, f2l; 4381 vsize_t resid; 4382 int i; 4383 4384 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 4385 4386 if (l1pt == 0) 4387 panic("pmap_map_chunk: no L1 table provided"); 4388 4389 #ifdef VERBOSE_INIT_ARM 4390 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 4391 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 4392 #endif 4393 4394 switch (cache) { 4395 case PTE_NOCACHE: 4396 default: 4397 f1 = 0; 4398 f2l = 0; 4399 f2s = 0; 4400 break; 4401 4402 case PTE_CACHE: 4403 f1 = pte_l1_s_cache_mode; 4404 f2l = pte_l2_l_cache_mode; 4405 f2s = pte_l2_s_cache_mode; 4406 break; 4407 4408 case PTE_PAGETABLE: 4409 f1 = pte_l1_s_cache_mode_pt; 4410 f2l = pte_l2_l_cache_mode_pt; 4411 f2s = pte_l2_s_cache_mode_pt; 4412 break; 4413 } 4414 4415 size = resid; 4416 4417 while (resid > 0) { 4418 /* See if we can use a section mapping. */ 4419 if (L1_S_MAPPABLE_P(va, pa, resid)) { 4420 #ifdef VERBOSE_INIT_ARM 4421 printf("S"); 4422 #endif 4423 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4424 L1_S_PROT(PTE_KERNEL, prot) | f1 | 4425 L1_S_DOM(PMAP_DOMAIN_KERNEL); 4426 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4427 va += L1_S_SIZE; 4428 pa += L1_S_SIZE; 4429 resid -= L1_S_SIZE; 4430 continue; 4431 } 4432 4433 /* 4434 * Ok, we're going to use an L2 table. Make sure 4435 * one is actually in the corresponding L1 slot 4436 * for the current VA. 4437 */ 4438 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4439 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 4440 4441 #ifndef ARM32_NEW_VM_LAYOUT 4442 pte = (pt_entry_t *) 4443 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 4444 #else 4445 pte = (pt_entry_t *) kernel_pt_lookup( 4446 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4447 #endif 4448 if (pte == NULL) 4449 panic("pmap_map_chunk: can't find L2 table for VA" 4450 "0x%08lx", va); 4451 4452 /* See if we can use a L2 large page mapping. */ 4453 if (L2_L_MAPPABLE_P(va, pa, resid)) { 4454 #ifdef VERBOSE_INIT_ARM 4455 printf("L"); 4456 #endif 4457 for (i = 0; i < 16; i++) { 4458 #ifndef ARM32_NEW_VM_LAYOUT 4459 pte[((va >> PGSHIFT) & 0x3f0) + i] = 4460 L2_L_PROTO | pa | 4461 L2_L_PROT(PTE_KERNEL, prot) | f2l; 4462 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 4463 #else 4464 pte[l2pte_index(va) + i] = 4465 L2_L_PROTO | pa | 4466 L2_L_PROT(PTE_KERNEL, prot) | f2l; 4467 PTE_SYNC(&pte[l2pte_index(va) + i]); 4468 #endif 4469 } 4470 va += L2_L_SIZE; 4471 pa += L2_L_SIZE; 4472 resid -= L2_L_SIZE; 4473 continue; 4474 } 4475 4476 /* Use a small page mapping. */ 4477 #ifdef VERBOSE_INIT_ARM 4478 printf("P"); 4479 #endif 4480 #ifndef ARM32_NEW_VM_LAYOUT 4481 pte[(va >> PGSHIFT) & 0x3ff] = 4482 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 4483 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 4484 #else 4485 pte[l2pte_index(va)] = 4486 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 4487 PTE_SYNC(&pte[l2pte_index(va)]); 4488 #endif 4489 va += PAGE_SIZE; 4490 pa += PAGE_SIZE; 4491 resid -= PAGE_SIZE; 4492 } 4493 #ifdef VERBOSE_INIT_ARM 4494 printf("\n"); 4495 #endif 4496 return (size); 4497 } 4498 4499 /********************** Static device map routines ***************************/ 4500 4501 static const struct pmap_devmap *pmap_devmap_table; 4502 4503 /* 4504 * Register the devmap table. This is provided in case early console 4505 * initialization needs to register mappings created by bootstrap code 4506 * before pmap_devmap_bootstrap() is called. 4507 */ 4508 void 4509 pmap_devmap_register(const struct pmap_devmap *table) 4510 { 4511 4512 pmap_devmap_table = table; 4513 } 4514 4515 /* 4516 * Map all of the static regions in the devmap table, and remember 4517 * the devmap table so other parts of the kernel can look up entries 4518 * later. 4519 */ 4520 void 4521 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 4522 { 4523 int i; 4524 4525 pmap_devmap_table = table; 4526 4527 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4528 #ifdef VERBOSE_INIT_ARM 4529 printf("devmap: %08lx -> %08lx @ %08lx\n", 4530 pmap_devmap_table[i].pd_pa, 4531 pmap_devmap_table[i].pd_pa + 4532 pmap_devmap_table[i].pd_size - 1, 4533 pmap_devmap_table[i].pd_va); 4534 #endif 4535 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 4536 pmap_devmap_table[i].pd_pa, 4537 pmap_devmap_table[i].pd_size, 4538 pmap_devmap_table[i].pd_prot, 4539 pmap_devmap_table[i].pd_cache); 4540 } 4541 } 4542 4543 const struct pmap_devmap * 4544 pmap_devmap_find_pa(paddr_t pa, psize_t size) 4545 { 4546 int i; 4547 4548 if (pmap_devmap_table == NULL) 4549 return (NULL); 4550 4551 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4552 if (pa >= pmap_devmap_table[i].pd_pa && 4553 pa + size <= pmap_devmap_table[i].pd_pa + 4554 pmap_devmap_table[i].pd_size) 4555 return (&pmap_devmap_table[i]); 4556 } 4557 4558 return (NULL); 4559 } 4560 4561 const struct pmap_devmap * 4562 pmap_devmap_find_va(vaddr_t va, vsize_t size) 4563 { 4564 int i; 4565 4566 if (pmap_devmap_table == NULL) 4567 return (NULL); 4568 4569 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4570 if (va >= pmap_devmap_table[i].pd_va && 4571 va + size <= pmap_devmap_table[i].pd_va + 4572 pmap_devmap_table[i].pd_size) 4573 return (&pmap_devmap_table[i]); 4574 } 4575 4576 return (NULL); 4577 } 4578 4579 /********************** PTE initialization routines **************************/ 4580 4581 /* 4582 * These routines are called when the CPU type is identified to set up 4583 * the PTE prototypes, cache modes, etc. 4584 * 4585 * The variables are always here, just in case LKMs need to reference 4586 * them (though, they shouldn't). 4587 */ 4588 4589 pt_entry_t pte_l1_s_cache_mode; 4590 pt_entry_t pte_l1_s_cache_mode_pt; 4591 pt_entry_t pte_l1_s_cache_mask; 4592 4593 pt_entry_t pte_l2_l_cache_mode; 4594 pt_entry_t pte_l2_l_cache_mode_pt; 4595 pt_entry_t pte_l2_l_cache_mask; 4596 4597 pt_entry_t pte_l2_s_cache_mode; 4598 pt_entry_t pte_l2_s_cache_mode_pt; 4599 pt_entry_t pte_l2_s_cache_mask; 4600 4601 pt_entry_t pte_l2_s_prot_u; 4602 pt_entry_t pte_l2_s_prot_w; 4603 pt_entry_t pte_l2_s_prot_mask; 4604 4605 pt_entry_t pte_l1_s_proto; 4606 pt_entry_t pte_l1_c_proto; 4607 pt_entry_t pte_l2_s_proto; 4608 4609 void (*pmap_copy_page_func)(paddr_t, paddr_t); 4610 void (*pmap_zero_page_func)(paddr_t); 4611 4612 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 4613 void 4614 pmap_pte_init_generic(void) 4615 { 4616 4617 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 4618 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 4619 4620 pte_l2_l_cache_mode = L2_B|L2_C; 4621 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 4622 4623 pte_l2_s_cache_mode = L2_B|L2_C; 4624 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 4625 4626 /* 4627 * If we have a write-through cache, set B and C. If 4628 * we have a write-back cache, then we assume setting 4629 * only C will make those pages write-through. 4630 */ 4631 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 4632 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 4633 pte_l2_l_cache_mode_pt = L2_B|L2_C; 4634 pte_l2_s_cache_mode_pt = L2_B|L2_C; 4635 } else { 4636 pte_l1_s_cache_mode_pt = L1_S_C; 4637 pte_l2_l_cache_mode_pt = L2_C; 4638 pte_l2_s_cache_mode_pt = L2_C; 4639 } 4640 4641 pte_l2_s_prot_u = L2_S_PROT_U_generic; 4642 pte_l2_s_prot_w = L2_S_PROT_W_generic; 4643 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 4644 4645 pte_l1_s_proto = L1_S_PROTO_generic; 4646 pte_l1_c_proto = L1_C_PROTO_generic; 4647 pte_l2_s_proto = L2_S_PROTO_generic; 4648 4649 pmap_copy_page_func = pmap_copy_page_generic; 4650 pmap_zero_page_func = pmap_zero_page_generic; 4651 } 4652 4653 #if defined(CPU_ARM8) 4654 void 4655 pmap_pte_init_arm8(void) 4656 { 4657 4658 /* 4659 * ARM8 is compatible with generic, but we need to use 4660 * the page tables uncached. 4661 */ 4662 pmap_pte_init_generic(); 4663 4664 pte_l1_s_cache_mode_pt = 0; 4665 pte_l2_l_cache_mode_pt = 0; 4666 pte_l2_s_cache_mode_pt = 0; 4667 } 4668 #endif /* CPU_ARM8 */ 4669 4670 #if defined(CPU_ARM9) 4671 void 4672 pmap_pte_init_arm9(void) 4673 { 4674 4675 /* 4676 * ARM9 is compatible with generic, but we want to use 4677 * write-through caching for now. 4678 */ 4679 pmap_pte_init_generic(); 4680 4681 pte_l1_s_cache_mode = L1_S_C; 4682 pte_l2_l_cache_mode = L2_C; 4683 pte_l2_s_cache_mode = L2_C; 4684 4685 pte_l1_s_cache_mode_pt = L1_S_C; 4686 pte_l2_l_cache_mode_pt = L2_C; 4687 pte_l2_s_cache_mode_pt = L2_C; 4688 } 4689 #endif /* CPU_ARM9 */ 4690 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 4691 4692 #if ARM_MMU_SA1 == 1 4693 void 4694 pmap_pte_init_sa1(void) 4695 { 4696 4697 /* 4698 * The StrongARM SA-1 cache does not have a write-through 4699 * mode. So, do the generic initialization, then reset 4700 * the page table cache mode to B=1,C=1, and note that 4701 * the PTEs need to be sync'd. 4702 */ 4703 pmap_pte_init_generic(); 4704 4705 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 4706 pte_l2_l_cache_mode_pt = L2_B|L2_C; 4707 pte_l2_s_cache_mode_pt = L2_B|L2_C; 4708 4709 pmap_needs_pte_sync = 1; 4710 } 4711 #endif /* ARM_MMU_SA1 == 1*/ 4712 4713 #if ARM_MMU_XSCALE == 1 4714 void 4715 pmap_pte_init_xscale(void) 4716 { 4717 uint32_t auxctl; 4718 int write_through = 0; 4719 4720 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 4721 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 4722 4723 pte_l2_l_cache_mode = L2_B|L2_C; 4724 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 4725 4726 pte_l2_s_cache_mode = L2_B|L2_C; 4727 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 4728 4729 pte_l1_s_cache_mode_pt = L1_S_C; 4730 pte_l2_l_cache_mode_pt = L2_C; 4731 pte_l2_s_cache_mode_pt = L2_C; 4732 4733 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 4734 /* 4735 * The XScale core has an enhanced mode where writes that 4736 * miss the cache cause a cache line to be allocated. This 4737 * is significantly faster than the traditional, write-through 4738 * behavior of this case. 4739 */ 4740 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X); 4741 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X); 4742 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X); 4743 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 4744 4745 #ifdef XSCALE_CACHE_WRITE_THROUGH 4746 /* 4747 * Some versions of the XScale core have various bugs in 4748 * their cache units, the work-around for which is to run 4749 * the cache in write-through mode. Unfortunately, this 4750 * has a major (negative) impact on performance. So, we 4751 * go ahead and run fast-and-loose, in the hopes that we 4752 * don't line up the planets in a way that will trip the 4753 * bugs. 4754 * 4755 * However, we give you the option to be slow-but-correct. 4756 */ 4757 write_through = 1; 4758 #elif defined(XSCALE_CACHE_WRITE_BACK) 4759 /* force write back cache mode */ 4760 write_through = 0; 4761 #elif defined(CPU_XSCALE_PXA2X0) 4762 /* 4763 * Intel PXA2[15]0 processors are known to have a bug in 4764 * write-back cache on revision 4 and earlier (stepping 4765 * A[01] and B[012]). Fixed for C0 and later. 4766 */ 4767 { 4768 uint32_t id, type; 4769 4770 id = cpufunc_id(); 4771 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 4772 4773 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 4774 if ((id & CPU_ID_REVISION_MASK) < 5) { 4775 /* write through for stepping A0-1 and B0-2 */ 4776 write_through = 1; 4777 } 4778 } 4779 } 4780 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 4781 4782 if (write_through) { 4783 pte_l1_s_cache_mode = L1_S_C; 4784 pte_l2_l_cache_mode = L2_C; 4785 pte_l2_s_cache_mode = L2_C; 4786 } 4787 4788 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 4789 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 4790 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 4791 4792 pte_l1_s_proto = L1_S_PROTO_xscale; 4793 pte_l1_c_proto = L1_C_PROTO_xscale; 4794 pte_l2_s_proto = L2_S_PROTO_xscale; 4795 4796 pmap_copy_page_func = pmap_copy_page_xscale; 4797 pmap_zero_page_func = pmap_zero_page_xscale; 4798 4799 /* 4800 * Disable ECC protection of page table access, for now. 4801 */ 4802 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" 4803 : "=r" (auxctl)); 4804 auxctl &= ~XSCALE_AUXCTL_P; 4805 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" 4806 : 4807 : "r" (auxctl)); 4808 } 4809 4810 /* 4811 * xscale_setup_minidata: 4812 * 4813 * Set up the mini-data cache clean area. We require the 4814 * caller to allocate the right amount of physically and 4815 * virtually contiguous space. 4816 */ 4817 void 4818 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 4819 { 4820 extern vaddr_t xscale_minidata_clean_addr; 4821 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 4822 pd_entry_t *pde = (pd_entry_t *) l1pt; 4823 pt_entry_t *pte; 4824 vsize_t size; 4825 uint32_t auxctl; 4826 4827 xscale_minidata_clean_addr = va; 4828 4829 /* Round it to page size. */ 4830 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 4831 4832 for (; size != 0; 4833 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 4834 #ifndef ARM32_NEW_VM_LAYOUT 4835 pte = (pt_entry_t *) 4836 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 4837 #else 4838 pte = (pt_entry_t *) kernel_pt_lookup( 4839 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4840 #endif 4841 if (pte == NULL) 4842 panic("xscale_setup_minidata: can't find L2 table for " 4843 "VA 0x%08lx", va); 4844 #ifndef ARM32_NEW_VM_LAYOUT 4845 pte[(va >> PGSHIFT) & 0x3ff] = 4846 #else 4847 pte[l2pte_index(va)] = 4848 #endif 4849 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4850 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); 4851 } 4852 4853 /* 4854 * Configure the mini-data cache for write-back with 4855 * read/write-allocate. 4856 * 4857 * NOTE: In order to reconfigure the mini-data cache, we must 4858 * make sure it contains no valid data! In order to do that, 4859 * we must issue a global data cache invalidate command! 4860 * 4861 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 4862 * THIS IS VERY IMPORTANT! 4863 */ 4864 4865 /* Invalidate data and mini-data. */ 4866 __asm __volatile("mcr p15, 0, %0, c7, c6, 0" 4867 : 4868 : "r" (auxctl)); 4869 4870 4871 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" 4872 : "=r" (auxctl)); 4873 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 4874 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" 4875 : 4876 : "r" (auxctl)); 4877 } 4878 #endif /* ARM_MMU_XSCALE == 1 */ 4879 4880 #if defined(DDB) 4881 /* 4882 * A couple of ddb-callable functions for dumping pmaps 4883 */ 4884 void pmap_dump_all(void); 4885 void pmap_dump(pmap_t); 4886 4887 void 4888 pmap_dump_all(void) 4889 { 4890 pmap_t pm; 4891 4892 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 4893 if (pm == pmap_kernel()) 4894 continue; 4895 pmap_dump(pm); 4896 printf("\n"); 4897 } 4898 } 4899 4900 static pt_entry_t ncptes[64]; 4901 static void pmap_dump_ncpg(pmap_t); 4902 4903 void 4904 pmap_dump(pmap_t pm) 4905 { 4906 struct l2_dtable *l2; 4907 struct l2_bucket *l2b; 4908 pt_entry_t *ptep, pte; 4909 vaddr_t l2_va, l2b_va, va; 4910 int i, j, k, occ, rows = 0; 4911 char ch; 4912 4913 if (pm == pmap_kernel()) 4914 printf("pmap_kernel (%p): ", pm); 4915 else 4916 printf("user pmap (%p): ", pm); 4917 4918 printf("domain %d, l1 at %p\n", pm->pm_domain, pm->pm_l1->l1_kva); 4919 4920 l2_va = 0; 4921 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 4922 l2 = pm->pm_l2[i]; 4923 4924 if (l2 == NULL || l2->l2_occupancy == 0) 4925 continue; 4926 4927 l2b_va = l2_va; 4928 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 4929 l2b = &l2->l2_bucket[j]; 4930 4931 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 4932 continue; 4933 4934 ptep = l2b->l2b_kva; 4935 4936 for (k = 0; k < 256 && ptep[k] == 0; k++) 4937 ; 4938 4939 k &= ~63; 4940 occ = l2b->l2b_occupancy; 4941 va = l2b_va + (k * 4096); 4942 for (; k < 256; k++, va += 0x1000) { 4943 if ((k % 64) == 0) { 4944 if ((rows % 8) == 0) { 4945 printf( 4946 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 4947 } 4948 printf("%08lx: ", va); 4949 } 4950 4951 ncptes[k & 63] = 0; 4952 pte = ptep[k]; 4953 if (pte == 0) { 4954 ch = '.'; 4955 } else { 4956 occ--; 4957 switch (pte & 0x0c) { 4958 case 0x00: 4959 ch = 'D'; /* No cache No buff */ 4960 break; 4961 case 0x04: 4962 ch = 'B'; /* No cache buff */ 4963 break; 4964 case 0x08: 4965 ch = 'C'; /* Cache No buff */ 4966 break; 4967 case 0x0c: 4968 ch = 'F'; /* Cache Buff */ 4969 break; 4970 } 4971 4972 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 4973 ch += 0x20; 4974 4975 if ((pte & 0xc) == 0) 4976 ncptes[k & 63] = pte; 4977 } 4978 4979 if ((k % 64) == 63) { 4980 rows++; 4981 printf("%c\n", ch); 4982 pmap_dump_ncpg(pm); 4983 if (occ == 0) 4984 break; 4985 } else 4986 printf("%c", ch); 4987 } 4988 } 4989 } 4990 } 4991 4992 static void 4993 pmap_dump_ncpg(pmap_t pm) 4994 { 4995 struct vm_page *pg; 4996 struct pv_entry *pv; 4997 int i; 4998 4999 for (i = 0; i < 63; i++) { 5000 if (ncptes[i] == 0) 5001 continue; 5002 5003 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 5004 if (pg == NULL) 5005 continue; 5006 5007 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 5008 pg->phys_addr, 5009 pg->mdpage.krw_mappings, pg->mdpage.kro_mappings, 5010 pg->mdpage.urw_mappings, pg->mdpage.uro_mappings); 5011 5012 for (pv = pg->mdpage.pvh_list; pv; pv = pv->pv_next) { 5013 printf(" %c va 0x%08lx, flags 0x%x\n", 5014 (pm == pv->pv_pmap) ? '*' : ' ', 5015 pv->pv_va, pv->pv_flags); 5016 } 5017 } 5018 } 5019 #endif 5020