1 /* $NetBSD: pmap.c,v 1.219 2010/11/12 07:59:25 uebayasi Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependant vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil@causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of 0xffff0000, then 166 * MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_cpuoptions.h" 190 #include "opt_pmap_debug.h" 191 #include "opt_ddb.h" 192 #include "opt_lockdebug.h" 193 #include "opt_multiprocessor.h" 194 195 #include <sys/param.h> 196 #include <sys/types.h> 197 #include <sys/kernel.h> 198 #include <sys/systm.h> 199 #include <sys/proc.h> 200 #include <sys/malloc.h> 201 #include <sys/pool.h> 202 #include <sys/cdefs.h> 203 #include <sys/cpu.h> 204 #include <sys/sysctl.h> 205 206 #include <uvm/uvm.h> 207 208 #include <machine/bus.h> 209 #include <machine/pmap.h> 210 #include <machine/pcb.h> 211 #include <machine/param.h> 212 #include <arm/arm32/katelib.h> 213 214 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.219 2010/11/12 07:59:25 uebayasi Exp $"); 215 216 #ifdef PMAP_DEBUG 217 218 /* XXX need to get rid of all refs to this */ 219 int pmap_debug_level = 0; 220 221 /* 222 * for switching to potentially finer grained debugging 223 */ 224 #define PDB_FOLLOW 0x0001 225 #define PDB_INIT 0x0002 226 #define PDB_ENTER 0x0004 227 #define PDB_REMOVE 0x0008 228 #define PDB_CREATE 0x0010 229 #define PDB_PTPAGE 0x0020 230 #define PDB_GROWKERN 0x0040 231 #define PDB_BITS 0x0080 232 #define PDB_COLLECT 0x0100 233 #define PDB_PROTECT 0x0200 234 #define PDB_MAP_L1 0x0400 235 #define PDB_BOOTSTRAP 0x1000 236 #define PDB_PARANOIA 0x2000 237 #define PDB_WIRING 0x4000 238 #define PDB_PVDUMP 0x8000 239 #define PDB_VAC 0x10000 240 #define PDB_KENTER 0x20000 241 #define PDB_KREMOVE 0x40000 242 #define PDB_EXEC 0x80000 243 244 int debugmap = 1; 245 int pmapdebug = 0; 246 #define NPDEBUG(_lev_,_stat_) \ 247 if (pmapdebug & (_lev_)) \ 248 ((_stat_)) 249 250 #else /* PMAP_DEBUG */ 251 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 252 #endif /* PMAP_DEBUG */ 253 254 /* 255 * pmap_kernel() points here 256 */ 257 static struct pmap kernel_pmap_store; 258 struct pmap *const kernel_pmap_ptr = &kernel_pmap_store; 259 260 /* 261 * Which pmap is currently 'live' in the cache 262 * 263 * XXXSCW: Fix for SMP ... 264 */ 265 static pmap_t pmap_recent_user; 266 267 /* 268 * Pointer to last active lwp, or NULL if it exited. 269 */ 270 struct lwp *pmap_previous_active_lwp; 271 272 /* 273 * Pool and cache that pmap structures are allocated from. 274 * We use a cache to avoid clearing the pm_l2[] array (1KB) 275 * in pmap_create(). 276 */ 277 static struct pool_cache pmap_cache; 278 static LIST_HEAD(, pmap) pmap_pmaps; 279 280 /* 281 * Pool of PV structures 282 */ 283 static struct pool pmap_pv_pool; 284 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 285 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 286 static struct pool_allocator pmap_bootstrap_pv_allocator = { 287 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 288 }; 289 290 /* 291 * Pool and cache of l2_dtable structures. 292 * We use a cache to avoid clearing the structures when they're 293 * allocated. (196 bytes) 294 */ 295 static struct pool_cache pmap_l2dtable_cache; 296 static vaddr_t pmap_kernel_l2dtable_kva; 297 298 /* 299 * Pool and cache of L2 page descriptors. 300 * We use a cache to avoid clearing the descriptor table 301 * when they're allocated. (1KB) 302 */ 303 static struct pool_cache pmap_l2ptp_cache; 304 static vaddr_t pmap_kernel_l2ptp_kva; 305 static paddr_t pmap_kernel_l2ptp_phys; 306 307 #ifdef PMAPCOUNTERS 308 #define PMAP_EVCNT_INITIALIZER(name) \ 309 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 310 311 #ifdef PMAP_CACHE_VIPT 312 static struct evcnt pmap_ev_vac_clean_one = 313 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 314 static struct evcnt pmap_ev_vac_flush_one = 315 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 316 static struct evcnt pmap_ev_vac_flush_lots = 317 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 318 static struct evcnt pmap_ev_vac_flush_lots2 = 319 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 320 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 321 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 322 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 323 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 324 325 static struct evcnt pmap_ev_vac_color_new = 326 PMAP_EVCNT_INITIALIZER("new page color"); 327 static struct evcnt pmap_ev_vac_color_reuse = 328 PMAP_EVCNT_INITIALIZER("ok first page color"); 329 static struct evcnt pmap_ev_vac_color_ok = 330 PMAP_EVCNT_INITIALIZER("ok page color"); 331 static struct evcnt pmap_ev_vac_color_blind = 332 PMAP_EVCNT_INITIALIZER("blind page color"); 333 static struct evcnt pmap_ev_vac_color_change = 334 PMAP_EVCNT_INITIALIZER("change page color"); 335 static struct evcnt pmap_ev_vac_color_erase = 336 PMAP_EVCNT_INITIALIZER("erase page color"); 337 static struct evcnt pmap_ev_vac_color_none = 338 PMAP_EVCNT_INITIALIZER("no page color"); 339 static struct evcnt pmap_ev_vac_color_restore = 340 PMAP_EVCNT_INITIALIZER("restore page color"); 341 342 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 343 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 344 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 345 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 346 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 350 #endif 351 352 static struct evcnt pmap_ev_mappings = 353 PMAP_EVCNT_INITIALIZER("pages mapped"); 354 static struct evcnt pmap_ev_unmappings = 355 PMAP_EVCNT_INITIALIZER("pages unmapped"); 356 static struct evcnt pmap_ev_remappings = 357 PMAP_EVCNT_INITIALIZER("pages remapped"); 358 359 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 360 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 361 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 362 363 static struct evcnt pmap_ev_kernel_mappings = 364 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 365 static struct evcnt pmap_ev_kernel_unmappings = 366 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 367 static struct evcnt pmap_ev_kernel_remappings = 368 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 369 370 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 371 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 372 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 373 374 static struct evcnt pmap_ev_kenter_mappings = 375 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 376 static struct evcnt pmap_ev_kenter_unmappings = 377 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 378 static struct evcnt pmap_ev_kenter_remappings = 379 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 380 static struct evcnt pmap_ev_pt_mappings = 381 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 382 383 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 384 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 385 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 386 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 387 388 #ifdef PMAP_CACHE_VIPT 389 static struct evcnt pmap_ev_exec_mappings = 390 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 391 static struct evcnt pmap_ev_exec_cached = 392 PMAP_EVCNT_INITIALIZER("exec pages cached"); 393 394 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 395 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 396 397 static struct evcnt pmap_ev_exec_synced = 398 PMAP_EVCNT_INITIALIZER("exec pages synced"); 399 static struct evcnt pmap_ev_exec_synced_map = 400 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 401 static struct evcnt pmap_ev_exec_synced_unmap = 402 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 403 static struct evcnt pmap_ev_exec_synced_remap = 404 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 405 static struct evcnt pmap_ev_exec_synced_clearbit = 406 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 407 static struct evcnt pmap_ev_exec_synced_kremove = 408 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 409 410 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 411 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 412 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 413 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 414 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 415 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 416 417 static struct evcnt pmap_ev_exec_discarded_unmap = 418 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 419 static struct evcnt pmap_ev_exec_discarded_zero = 420 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 421 static struct evcnt pmap_ev_exec_discarded_copy = 422 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 423 static struct evcnt pmap_ev_exec_discarded_page_protect = 424 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 425 static struct evcnt pmap_ev_exec_discarded_clearbit = 426 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 427 static struct evcnt pmap_ev_exec_discarded_kremove = 428 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 429 430 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 431 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 432 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 433 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 434 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 435 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 436 #endif /* PMAP_CACHE_VIPT */ 437 438 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 439 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 440 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 441 442 EVCNT_ATTACH_STATIC(pmap_ev_updates); 443 EVCNT_ATTACH_STATIC(pmap_ev_collects); 444 EVCNT_ATTACH_STATIC(pmap_ev_activations); 445 446 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 447 #else 448 #define PMAPCOUNT(x) ((void)0) 449 #endif 450 451 /* 452 * pmap copy/zero page, and mem(5) hook point 453 */ 454 static pt_entry_t *csrc_pte, *cdst_pte; 455 static vaddr_t csrcp, cdstp; 456 vaddr_t memhook; /* used by mem.c */ 457 kmutex_t memlock; /* used by mem.c */ 458 void *zeropage; /* used by mem.c */ 459 extern void *msgbufaddr; 460 int pmap_kmpages; 461 /* 462 * Flag to indicate if pmap_init() has done its thing 463 */ 464 bool pmap_initialized; 465 466 /* 467 * Misc. locking data structures 468 */ 469 470 #if 0 /* defined(MULTIPROCESSOR) || defined(LOCKDEBUG) */ 471 static struct lock pmap_main_lock; 472 473 #define PMAP_MAP_TO_HEAD_LOCK() \ 474 (void) spinlockmgr(&pmap_main_lock, LK_SHARED, NULL) 475 #define PMAP_MAP_TO_HEAD_UNLOCK() \ 476 (void) spinlockmgr(&pmap_main_lock, LK_RELEASE, NULL) 477 #define PMAP_HEAD_TO_MAP_LOCK() \ 478 (void) spinlockmgr(&pmap_main_lock, LK_EXCLUSIVE, NULL) 479 #define PMAP_HEAD_TO_MAP_UNLOCK() \ 480 spinlockmgr(&pmap_main_lock, LK_RELEASE, (void *) 0) 481 #else 482 #define PMAP_MAP_TO_HEAD_LOCK() /* null */ 483 #define PMAP_MAP_TO_HEAD_UNLOCK() /* null */ 484 #define PMAP_HEAD_TO_MAP_LOCK() /* null */ 485 #define PMAP_HEAD_TO_MAP_UNLOCK() /* null */ 486 #endif 487 488 #define pmap_acquire_pmap_lock(pm) \ 489 do { \ 490 if ((pm) != pmap_kernel()) \ 491 mutex_enter(&(pm)->pm_lock); \ 492 } while (/*CONSTCOND*/0) 493 494 #define pmap_release_pmap_lock(pm) \ 495 do { \ 496 if ((pm) != pmap_kernel()) \ 497 mutex_exit(&(pm)->pm_lock); \ 498 } while (/*CONSTCOND*/0) 499 500 501 /* 502 * Metadata for L1 translation tables. 503 */ 504 struct l1_ttable { 505 /* Entry on the L1 Table list */ 506 SLIST_ENTRY(l1_ttable) l1_link; 507 508 /* Entry on the L1 Least Recently Used list */ 509 TAILQ_ENTRY(l1_ttable) l1_lru; 510 511 /* Track how many domains are allocated from this L1 */ 512 volatile u_int l1_domain_use_count; 513 514 /* 515 * A free-list of domain numbers for this L1. 516 * We avoid using ffs() and a bitmap to track domains since ffs() 517 * is slow on ARM. 518 */ 519 u_int8_t l1_domain_first; 520 u_int8_t l1_domain_free[PMAP_DOMAINS]; 521 522 /* Physical address of this L1 page table */ 523 paddr_t l1_physaddr; 524 525 /* KVA of this L1 page table */ 526 pd_entry_t *l1_kva; 527 }; 528 529 /* 530 * Convert a virtual address into its L1 table index. That is, the 531 * index used to locate the L2 descriptor table pointer in an L1 table. 532 * This is basically used to index l1->l1_kva[]. 533 * 534 * Each L2 descriptor table represents 1MB of VA space. 535 */ 536 #define L1_IDX(va) (((vaddr_t)(va)) >> L1_S_SHIFT) 537 538 /* 539 * L1 Page Tables are tracked using a Least Recently Used list. 540 * - New L1s are allocated from the HEAD. 541 * - Freed L1s are added to the TAIl. 542 * - Recently accessed L1s (where an 'access' is some change to one of 543 * the userland pmaps which owns this L1) are moved to the TAIL. 544 */ 545 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 546 static struct simplelock l1_lru_lock; 547 548 /* 549 * A list of all L1 tables 550 */ 551 static SLIST_HEAD(, l1_ttable) l1_list; 552 553 /* 554 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 555 * 556 * This is normally 16MB worth L2 page descriptors for any given pmap. 557 * Reference counts are maintained for L2 descriptors so they can be 558 * freed when empty. 559 */ 560 struct l2_dtable { 561 /* The number of L2 page descriptors allocated to this l2_dtable */ 562 u_int l2_occupancy; 563 564 /* List of L2 page descriptors */ 565 struct l2_bucket { 566 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 567 paddr_t l2b_phys; /* Physical address of same */ 568 u_short l2b_l1idx; /* This L2 table's L1 index */ 569 u_short l2b_occupancy; /* How many active descriptors */ 570 } l2_bucket[L2_BUCKET_SIZE]; 571 }; 572 573 /* 574 * Given an L1 table index, calculate the corresponding l2_dtable index 575 * and bucket index within the l2_dtable. 576 */ 577 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 578 (L2_SIZE - 1)) 579 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 580 581 /* 582 * Given a virtual address, this macro returns the 583 * virtual address required to drop into the next L2 bucket. 584 */ 585 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 586 587 /* 588 * L2 allocation. 589 */ 590 #define pmap_alloc_l2_dtable() \ 591 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 592 #define pmap_free_l2_dtable(l2) \ 593 pool_cache_put(&pmap_l2dtable_cache, (l2)) 594 #define pmap_alloc_l2_ptp(pap) \ 595 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 596 PR_NOWAIT, (pap))) 597 598 /* 599 * We try to map the page tables write-through, if possible. However, not 600 * all CPUs have a write-through cache mode, so on those we have to sync 601 * the cache when we frob page tables. 602 * 603 * We try to evaluate this at compile time, if possible. However, it's 604 * not always possible to do that, hence this run-time var. 605 */ 606 int pmap_needs_pte_sync; 607 608 /* 609 * Real definition of pv_entry. 610 */ 611 struct pv_entry { 612 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 613 pmap_t pv_pmap; /* pmap where mapping lies */ 614 vaddr_t pv_va; /* virtual address for mapping */ 615 u_int pv_flags; /* flags */ 616 }; 617 618 /* 619 * Macro to determine if a mapping might be resident in the 620 * instruction cache and/or TLB 621 */ 622 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 623 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 624 625 /* 626 * Macro to determine if a mapping might be resident in the 627 * data cache and/or TLB 628 */ 629 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 630 631 /* 632 * Local prototypes 633 */ 634 static int pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t); 635 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 636 pt_entry_t **); 637 static bool pmap_is_current(pmap_t); 638 static bool pmap_is_cached(pmap_t); 639 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 640 pmap_t, vaddr_t, u_int); 641 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 642 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 643 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 644 u_int, u_int); 645 646 static void pmap_pinit(pmap_t); 647 static int pmap_pmap_ctor(void *, void *, int); 648 649 static void pmap_alloc_l1(pmap_t); 650 static void pmap_free_l1(pmap_t); 651 static void pmap_use_l1(pmap_t); 652 653 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 654 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 655 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 656 static int pmap_l2ptp_ctor(void *, void *, int); 657 static int pmap_l2dtable_ctor(void *, void *, int); 658 659 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 660 #ifdef PMAP_CACHE_VIVT 661 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 662 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 663 #endif 664 665 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 666 #ifdef PMAP_CACHE_VIVT 667 static int pmap_clean_page(struct pv_entry *, bool); 668 #endif 669 #ifdef PMAP_CACHE_VIPT 670 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 671 enum pmap_flush_op { 672 PMAP_FLUSH_PRIMARY, 673 PMAP_FLUSH_SECONDARY, 674 PMAP_CLEAN_PRIMARY 675 }; 676 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 677 #endif 678 static void pmap_page_remove(struct vm_page_md *, paddr_t); 679 680 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 681 static vaddr_t kernel_pt_lookup(paddr_t); 682 683 684 /* 685 * External function prototypes 686 */ 687 extern void bzero_page(vaddr_t); 688 extern void bcopy_page(vaddr_t, vaddr_t); 689 690 /* 691 * Misc variables 692 */ 693 vaddr_t virtual_avail; 694 vaddr_t virtual_end; 695 vaddr_t pmap_curmaxkvaddr; 696 697 paddr_t avail_start; 698 paddr_t avail_end; 699 700 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 701 pv_addr_t kernelpages; 702 pv_addr_t kernel_l1pt; 703 pv_addr_t systempage; 704 705 /* Function to set the debug level of the pmap code */ 706 707 #ifdef PMAP_DEBUG 708 void 709 pmap_debug(int level) 710 { 711 pmap_debug_level = level; 712 printf("pmap_debug: level=%d\n", pmap_debug_level); 713 } 714 #endif /* PMAP_DEBUG */ 715 716 /* 717 * A bunch of routines to conditionally flush the caches/TLB depending 718 * on whether the specified pmap actually needs to be flushed at any 719 * given time. 720 */ 721 static inline void 722 pmap_tlb_flushID_SE(pmap_t pm, vaddr_t va) 723 { 724 725 if (pm->pm_cstate.cs_tlb_id) 726 cpu_tlb_flushID_SE(va); 727 } 728 729 static inline void 730 pmap_tlb_flushD_SE(pmap_t pm, vaddr_t va) 731 { 732 733 if (pm->pm_cstate.cs_tlb_d) 734 cpu_tlb_flushD_SE(va); 735 } 736 737 static inline void 738 pmap_tlb_flushID(pmap_t pm) 739 { 740 741 if (pm->pm_cstate.cs_tlb_id) { 742 cpu_tlb_flushID(); 743 pm->pm_cstate.cs_tlb = 0; 744 } 745 } 746 747 static inline void 748 pmap_tlb_flushD(pmap_t pm) 749 { 750 751 if (pm->pm_cstate.cs_tlb_d) { 752 cpu_tlb_flushD(); 753 pm->pm_cstate.cs_tlb_d = 0; 754 } 755 } 756 757 #ifdef PMAP_CACHE_VIVT 758 static inline void 759 pmap_idcache_wbinv_range(pmap_t pm, vaddr_t va, vsize_t len) 760 { 761 if (pm->pm_cstate.cs_cache_id) { 762 cpu_idcache_wbinv_range(va, len); 763 } 764 } 765 766 static inline void 767 pmap_dcache_wb_range(pmap_t pm, vaddr_t va, vsize_t len, 768 bool do_inv, bool rd_only) 769 { 770 771 if (pm->pm_cstate.cs_cache_d) { 772 if (do_inv) { 773 if (rd_only) 774 cpu_dcache_inv_range(va, len); 775 else 776 cpu_dcache_wbinv_range(va, len); 777 } else 778 if (!rd_only) 779 cpu_dcache_wb_range(va, len); 780 } 781 } 782 783 static inline void 784 pmap_idcache_wbinv_all(pmap_t pm) 785 { 786 if (pm->pm_cstate.cs_cache_id) { 787 cpu_idcache_wbinv_all(); 788 pm->pm_cstate.cs_cache = 0; 789 } 790 } 791 792 static inline void 793 pmap_dcache_wbinv_all(pmap_t pm) 794 { 795 if (pm->pm_cstate.cs_cache_d) { 796 cpu_dcache_wbinv_all(); 797 pm->pm_cstate.cs_cache_d = 0; 798 } 799 } 800 #endif /* PMAP_CACHE_VIVT */ 801 802 static inline bool 803 pmap_is_current(pmap_t pm) 804 { 805 806 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 807 return true; 808 809 return false; 810 } 811 812 static inline bool 813 pmap_is_cached(pmap_t pm) 814 { 815 816 if (pm == pmap_kernel() || pmap_recent_user == NULL || 817 pmap_recent_user == pm) 818 return (true); 819 820 return false; 821 } 822 823 /* 824 * PTE_SYNC_CURRENT: 825 * 826 * Make sure the pte is written out to RAM. 827 * We need to do this for one of two cases: 828 * - We're dealing with the kernel pmap 829 * - There is no pmap active in the cache/tlb. 830 * - The specified pmap is 'active' in the cache/tlb. 831 */ 832 #ifdef PMAP_INCLUDE_PTE_SYNC 833 #define PTE_SYNC_CURRENT(pm, ptep) \ 834 do { \ 835 if (PMAP_NEEDS_PTE_SYNC && \ 836 pmap_is_cached(pm)) \ 837 PTE_SYNC(ptep); \ 838 } while (/*CONSTCOND*/0) 839 #else 840 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 841 #endif 842 843 /* 844 * main pv_entry manipulation functions: 845 * pmap_enter_pv: enter a mapping onto a vm_page list 846 * pmap_remove_pv: remove a mappiing from a vm_page list 847 * 848 * NOTE: pmap_enter_pv expects to lock the pvh itself 849 * pmap_remove_pv expects te caller to lock the pvh before calling 850 */ 851 852 /* 853 * pmap_enter_pv: enter a mapping onto a vm_page lst 854 * 855 * => caller should hold the proper lock on pmap_main_lock 856 * => caller should have pmap locked 857 * => we will gain the lock on the vm_page and allocate the new pv_entry 858 * => caller should adjust ptp's wire_count before calling 859 * => caller should not adjust pmap's wire_count 860 */ 861 static void 862 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 863 vaddr_t va, u_int flags) 864 { 865 struct pv_entry **pvp; 866 867 NPDEBUG(PDB_PVDUMP, 868 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 869 870 pv->pv_pmap = pm; 871 pv->pv_va = va; 872 pv->pv_flags = flags; 873 874 simple_lock(&md->pvh_slock); /* lock vm_page */ 875 pvp = &SLIST_FIRST(&md->pvh_list); 876 #ifdef PMAP_CACHE_VIPT 877 /* 878 * Insert unmanaged entries, writeable first, at the head of 879 * the pv list. 880 */ 881 if (__predict_true((flags & PVF_KENTRY) == 0)) { 882 while (*pvp != NULL && (*pvp)->pv_flags & PVF_KENTRY) 883 pvp = &SLIST_NEXT(*pvp, pv_link); 884 } else if ((flags & PVF_WRITE) == 0) { 885 while (*pvp != NULL && (*pvp)->pv_flags & PVF_WRITE) 886 pvp = &SLIST_NEXT(*pvp, pv_link); 887 } 888 #endif 889 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 890 *pvp = pv; /* ... locked list */ 891 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 892 #ifdef PMAP_CACHE_VIPT 893 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 894 md->pvh_attrs |= PVF_KMOD; 895 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 896 md->pvh_attrs |= PVF_DIRTY; 897 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 898 #endif 899 if (pm == pmap_kernel()) { 900 PMAPCOUNT(kernel_mappings); 901 if (flags & PVF_WRITE) 902 md->krw_mappings++; 903 else 904 md->kro_mappings++; 905 } else { 906 if (flags & PVF_WRITE) 907 md->urw_mappings++; 908 else 909 md->uro_mappings++; 910 } 911 912 #ifdef PMAP_CACHE_VIPT 913 /* 914 * If this is an exec mapping and its the first exec mapping 915 * for this page, make sure to sync the I-cache. 916 */ 917 if (PV_IS_EXEC_P(flags)) { 918 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 919 pmap_syncicache_page(md, pa); 920 PMAPCOUNT(exec_synced_map); 921 } 922 PMAPCOUNT(exec_mappings); 923 } 924 #endif 925 926 PMAPCOUNT(mappings); 927 simple_unlock(&md->pvh_slock); /* unlock, done! */ 928 929 if (pv->pv_flags & PVF_WIRED) 930 ++pm->pm_stats.wired_count; 931 } 932 933 /* 934 * 935 * pmap_find_pv: Find a pv entry 936 * 937 * => caller should hold lock on vm_page 938 */ 939 static inline struct pv_entry * 940 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 941 { 942 struct pv_entry *pv; 943 944 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 945 if (pm == pv->pv_pmap && va == pv->pv_va) 946 break; 947 } 948 949 return (pv); 950 } 951 952 /* 953 * pmap_remove_pv: try to remove a mapping from a pv_list 954 * 955 * => caller should hold proper lock on pmap_main_lock 956 * => pmap should be locked 957 * => caller should hold lock on vm_page [so that attrs can be adjusted] 958 * => caller should adjust ptp's wire_count and free PTP if needed 959 * => caller should NOT adjust pmap's wire_count 960 * => we return the removed pv 961 */ 962 static struct pv_entry * 963 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 964 { 965 struct pv_entry *pv, **prevptr; 966 967 NPDEBUG(PDB_PVDUMP, 968 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 969 970 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 971 pv = *prevptr; 972 973 while (pv) { 974 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 975 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 976 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 977 if (pv->pv_flags & PVF_WIRED) { 978 --pm->pm_stats.wired_count; 979 } 980 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 981 if (pm == pmap_kernel()) { 982 PMAPCOUNT(kernel_unmappings); 983 if (pv->pv_flags & PVF_WRITE) 984 md->krw_mappings--; 985 else 986 md->kro_mappings--; 987 } else { 988 if (pv->pv_flags & PVF_WRITE) 989 md->urw_mappings--; 990 else 991 md->uro_mappings--; 992 } 993 994 PMAPCOUNT(unmappings); 995 #ifdef PMAP_CACHE_VIPT 996 if (!(pv->pv_flags & PVF_WRITE)) 997 break; 998 /* 999 * If this page has had an exec mapping, then if 1000 * this was the last mapping, discard the contents, 1001 * otherwise sync the i-cache for this page. 1002 */ 1003 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1004 if (SLIST_EMPTY(&md->pvh_list)) { 1005 md->pvh_attrs &= ~PVF_EXEC; 1006 PMAPCOUNT(exec_discarded_unmap); 1007 } else { 1008 pmap_syncicache_page(md, pa); 1009 PMAPCOUNT(exec_synced_unmap); 1010 } 1011 } 1012 #endif /* PMAP_CACHE_VIPT */ 1013 break; 1014 } 1015 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1016 pv = *prevptr; /* advance */ 1017 } 1018 1019 #ifdef PMAP_CACHE_VIPT 1020 /* 1021 * If we no longer have a WRITEABLE KENTRY at the head of list, 1022 * clear the KMOD attribute from the page. 1023 */ 1024 if (SLIST_FIRST(&md->pvh_list) == NULL 1025 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1026 md->pvh_attrs &= ~PVF_KMOD; 1027 1028 /* 1029 * If this was a writeable page and there are no more writeable 1030 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1031 * the contents to memory. 1032 */ 1033 if (md->krw_mappings + md->urw_mappings == 0) 1034 md->pvh_attrs &= ~PVF_WRITE; 1035 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1036 #endif /* PMAP_CACHE_VIPT */ 1037 1038 return(pv); /* return removed pv */ 1039 } 1040 1041 /* 1042 * 1043 * pmap_modify_pv: Update pv flags 1044 * 1045 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1046 * => caller should NOT adjust pmap's wire_count 1047 * => caller must call pmap_vac_me_harder() if writable status of a page 1048 * may have changed. 1049 * => we return the old flags 1050 * 1051 * Modify a physical-virtual mapping in the pv table 1052 */ 1053 static u_int 1054 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1055 u_int clr_mask, u_int set_mask) 1056 { 1057 struct pv_entry *npv; 1058 u_int flags, oflags; 1059 1060 KASSERT((clr_mask & PVF_KENTRY) == 0); 1061 KASSERT((set_mask & PVF_KENTRY) == 0); 1062 1063 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1064 return (0); 1065 1066 NPDEBUG(PDB_PVDUMP, 1067 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1068 1069 /* 1070 * There is at least one VA mapping this page. 1071 */ 1072 1073 if (clr_mask & (PVF_REF | PVF_MOD)) { 1074 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1075 #ifdef PMAP_CACHE_VIPT 1076 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1077 md->pvh_attrs |= PVF_DIRTY; 1078 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1079 #endif 1080 } 1081 1082 oflags = npv->pv_flags; 1083 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1084 1085 if ((flags ^ oflags) & PVF_WIRED) { 1086 if (flags & PVF_WIRED) 1087 ++pm->pm_stats.wired_count; 1088 else 1089 --pm->pm_stats.wired_count; 1090 } 1091 1092 if ((flags ^ oflags) & PVF_WRITE) { 1093 if (pm == pmap_kernel()) { 1094 if (flags & PVF_WRITE) { 1095 md->krw_mappings++; 1096 md->kro_mappings--; 1097 } else { 1098 md->kro_mappings++; 1099 md->krw_mappings--; 1100 } 1101 } else { 1102 if (flags & PVF_WRITE) { 1103 md->urw_mappings++; 1104 md->uro_mappings--; 1105 } else { 1106 md->uro_mappings++; 1107 md->urw_mappings--; 1108 } 1109 } 1110 } 1111 #ifdef PMAP_CACHE_VIPT 1112 if (md->urw_mappings + md->krw_mappings == 0) 1113 md->pvh_attrs &= ~PVF_WRITE; 1114 /* 1115 * We have two cases here: the first is from enter_pv (new exec 1116 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1117 * Since in latter, pmap_enter_pv won't do anything, we just have 1118 * to do what pmap_remove_pv would do. 1119 */ 1120 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1121 || (PV_IS_EXEC_P(md->pvh_attrs) 1122 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1123 pmap_syncicache_page(md, pa); 1124 PMAPCOUNT(exec_synced_remap); 1125 } 1126 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1127 #endif 1128 1129 PMAPCOUNT(remappings); 1130 1131 return (oflags); 1132 } 1133 1134 /* 1135 * Allocate an L1 translation table for the specified pmap. 1136 * This is called at pmap creation time. 1137 */ 1138 static void 1139 pmap_alloc_l1(pmap_t pm) 1140 { 1141 struct l1_ttable *l1; 1142 u_int8_t domain; 1143 1144 /* 1145 * Remove the L1 at the head of the LRU list 1146 */ 1147 simple_lock(&l1_lru_lock); 1148 l1 = TAILQ_FIRST(&l1_lru_list); 1149 KDASSERT(l1 != NULL); 1150 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1151 1152 /* 1153 * Pick the first available domain number, and update 1154 * the link to the next number. 1155 */ 1156 domain = l1->l1_domain_first; 1157 l1->l1_domain_first = l1->l1_domain_free[domain]; 1158 1159 /* 1160 * If there are still free domain numbers in this L1, 1161 * put it back on the TAIL of the LRU list. 1162 */ 1163 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1164 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1165 1166 simple_unlock(&l1_lru_lock); 1167 1168 /* 1169 * Fix up the relevant bits in the pmap structure 1170 */ 1171 pm->pm_l1 = l1; 1172 pm->pm_domain = domain; 1173 } 1174 1175 /* 1176 * Free an L1 translation table. 1177 * This is called at pmap destruction time. 1178 */ 1179 static void 1180 pmap_free_l1(pmap_t pm) 1181 { 1182 struct l1_ttable *l1 = pm->pm_l1; 1183 1184 simple_lock(&l1_lru_lock); 1185 1186 /* 1187 * If this L1 is currently on the LRU list, remove it. 1188 */ 1189 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1190 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1191 1192 /* 1193 * Free up the domain number which was allocated to the pmap 1194 */ 1195 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 1196 l1->l1_domain_first = pm->pm_domain; 1197 l1->l1_domain_use_count--; 1198 1199 /* 1200 * The L1 now must have at least 1 free domain, so add 1201 * it back to the LRU list. If the use count is zero, 1202 * put it at the head of the list, otherwise it goes 1203 * to the tail. 1204 */ 1205 if (l1->l1_domain_use_count == 0) 1206 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1207 else 1208 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1209 1210 simple_unlock(&l1_lru_lock); 1211 } 1212 1213 static inline void 1214 pmap_use_l1(pmap_t pm) 1215 { 1216 struct l1_ttable *l1; 1217 1218 /* 1219 * Do nothing if we're in interrupt context. 1220 * Access to an L1 by the kernel pmap must not affect 1221 * the LRU list. 1222 */ 1223 if (cpu_intr_p() || pm == pmap_kernel()) 1224 return; 1225 1226 l1 = pm->pm_l1; 1227 1228 /* 1229 * If the L1 is not currently on the LRU list, just return 1230 */ 1231 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1232 return; 1233 1234 simple_lock(&l1_lru_lock); 1235 1236 /* 1237 * Check the use count again, now that we've acquired the lock 1238 */ 1239 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1240 simple_unlock(&l1_lru_lock); 1241 return; 1242 } 1243 1244 /* 1245 * Move the L1 to the back of the LRU list 1246 */ 1247 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1248 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1249 1250 simple_unlock(&l1_lru_lock); 1251 } 1252 1253 /* 1254 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1255 * 1256 * Free an L2 descriptor table. 1257 */ 1258 static inline void 1259 #ifndef PMAP_INCLUDE_PTE_SYNC 1260 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1261 #else 1262 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1263 #endif 1264 { 1265 #ifdef PMAP_INCLUDE_PTE_SYNC 1266 #ifdef PMAP_CACHE_VIVT 1267 /* 1268 * Note: With a write-back cache, we may need to sync this 1269 * L2 table before re-using it. 1270 * This is because it may have belonged to a non-current 1271 * pmap, in which case the cache syncs would have been 1272 * skipped for the pages that were being unmapped. If the 1273 * L2 table were then to be immediately re-allocated to 1274 * the *current* pmap, it may well contain stale mappings 1275 * which have not yet been cleared by a cache write-back 1276 * and so would still be visible to the mmu. 1277 */ 1278 if (need_sync) 1279 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1280 #endif /* PMAP_CACHE_VIVT */ 1281 #endif /* PMAP_INCLUDE_PTE_SYNC */ 1282 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1283 } 1284 1285 /* 1286 * Returns a pointer to the L2 bucket associated with the specified pmap 1287 * and VA, or NULL if no L2 bucket exists for the address. 1288 */ 1289 static inline struct l2_bucket * 1290 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1291 { 1292 struct l2_dtable *l2; 1293 struct l2_bucket *l2b; 1294 u_short l1idx; 1295 1296 l1idx = L1_IDX(va); 1297 1298 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 1299 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 1300 return (NULL); 1301 1302 return (l2b); 1303 } 1304 1305 /* 1306 * Returns a pointer to the L2 bucket associated with the specified pmap 1307 * and VA. 1308 * 1309 * If no L2 bucket exists, perform the necessary allocations to put an L2 1310 * bucket/page table in place. 1311 * 1312 * Note that if a new L2 bucket/page was allocated, the caller *must* 1313 * increment the bucket occupancy counter appropriately *before* 1314 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1315 * the bucket/page in the meantime. 1316 */ 1317 static struct l2_bucket * 1318 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1319 { 1320 struct l2_dtable *l2; 1321 struct l2_bucket *l2b; 1322 u_short l1idx; 1323 1324 l1idx = L1_IDX(va); 1325 1326 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 1327 /* 1328 * No mapping at this address, as there is 1329 * no entry in the L1 table. 1330 * Need to allocate a new l2_dtable. 1331 */ 1332 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1333 return (NULL); 1334 1335 /* 1336 * Link it into the parent pmap 1337 */ 1338 pm->pm_l2[L2_IDX(l1idx)] = l2; 1339 } 1340 1341 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1342 1343 /* 1344 * Fetch pointer to the L2 page table associated with the address. 1345 */ 1346 if (l2b->l2b_kva == NULL) { 1347 pt_entry_t *ptep; 1348 1349 /* 1350 * No L2 page table has been allocated. Chances are, this 1351 * is because we just allocated the l2_dtable, above. 1352 */ 1353 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_phys)) == NULL) { 1354 /* 1355 * Oops, no more L2 page tables available at this 1356 * time. We may need to deallocate the l2_dtable 1357 * if we allocated a new one above. 1358 */ 1359 if (l2->l2_occupancy == 0) { 1360 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1361 pmap_free_l2_dtable(l2); 1362 } 1363 return (NULL); 1364 } 1365 1366 l2->l2_occupancy++; 1367 l2b->l2b_kva = ptep; 1368 l2b->l2b_l1idx = l1idx; 1369 } 1370 1371 return (l2b); 1372 } 1373 1374 /* 1375 * One or more mappings in the specified L2 descriptor table have just been 1376 * invalidated. 1377 * 1378 * Garbage collect the metadata and descriptor table itself if necessary. 1379 * 1380 * The pmap lock must be acquired when this is called (not necessary 1381 * for the kernel pmap). 1382 */ 1383 static void 1384 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1385 { 1386 struct l2_dtable *l2; 1387 pd_entry_t *pl1pd, l1pd; 1388 pt_entry_t *ptep; 1389 u_short l1idx; 1390 1391 KDASSERT(count <= l2b->l2b_occupancy); 1392 1393 /* 1394 * Update the bucket's reference count according to how many 1395 * PTEs the caller has just invalidated. 1396 */ 1397 l2b->l2b_occupancy -= count; 1398 1399 /* 1400 * Note: 1401 * 1402 * Level 2 page tables allocated to the kernel pmap are never freed 1403 * as that would require checking all Level 1 page tables and 1404 * removing any references to the Level 2 page table. See also the 1405 * comment elsewhere about never freeing bootstrap L2 descriptors. 1406 * 1407 * We make do with just invalidating the mapping in the L2 table. 1408 * 1409 * This isn't really a big deal in practice and, in fact, leads 1410 * to a performance win over time as we don't need to continually 1411 * alloc/free. 1412 */ 1413 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1414 return; 1415 1416 /* 1417 * There are no more valid mappings in this level 2 page table. 1418 * Go ahead and NULL-out the pointer in the bucket, then 1419 * free the page table. 1420 */ 1421 l1idx = l2b->l2b_l1idx; 1422 ptep = l2b->l2b_kva; 1423 l2b->l2b_kva = NULL; 1424 1425 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1426 1427 /* 1428 * If the L1 slot matches the pmap's domain 1429 * number, then invalidate it. 1430 */ 1431 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1432 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1433 *pl1pd = 0; 1434 PTE_SYNC(pl1pd); 1435 } 1436 1437 /* 1438 * Release the L2 descriptor table back to the pool cache. 1439 */ 1440 #ifndef PMAP_INCLUDE_PTE_SYNC 1441 pmap_free_l2_ptp(ptep, l2b->l2b_phys); 1442 #else 1443 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_phys); 1444 #endif 1445 1446 /* 1447 * Update the reference count in the associated l2_dtable 1448 */ 1449 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1450 if (--l2->l2_occupancy > 0) 1451 return; 1452 1453 /* 1454 * There are no more valid mappings in any of the Level 1 1455 * slots managed by this l2_dtable. Go ahead and NULL-out 1456 * the pointer in the parent pmap and free the l2_dtable. 1457 */ 1458 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1459 pmap_free_l2_dtable(l2); 1460 } 1461 1462 /* 1463 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1464 * structures. 1465 */ 1466 static int 1467 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1468 { 1469 #ifndef PMAP_INCLUDE_PTE_SYNC 1470 struct l2_bucket *l2b; 1471 pt_entry_t *ptep, pte; 1472 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1473 1474 /* 1475 * The mappings for these page tables were initially made using 1476 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1477 * mode will not be right for page table mappings. To avoid 1478 * polluting the pmap_kenter_pa() code with a special case for 1479 * page tables, we simply fix up the cache-mode here if it's not 1480 * correct. 1481 */ 1482 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1483 KDASSERT(l2b != NULL); 1484 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1485 pte = *ptep; 1486 1487 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1488 /* 1489 * Page tables must have the cache-mode set to Write-Thru. 1490 */ 1491 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1492 PTE_SYNC(ptep); 1493 cpu_tlb_flushD_SE(va); 1494 cpu_cpwait(); 1495 } 1496 #endif 1497 1498 memset(v, 0, L2_TABLE_SIZE_REAL); 1499 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1500 return (0); 1501 } 1502 1503 static int 1504 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1505 { 1506 1507 memset(v, 0, sizeof(struct l2_dtable)); 1508 return (0); 1509 } 1510 1511 static int 1512 pmap_pmap_ctor(void *arg, void *v, int flags) 1513 { 1514 1515 memset(v, 0, sizeof(struct pmap)); 1516 return (0); 1517 } 1518 1519 static void 1520 pmap_pinit(pmap_t pm) 1521 { 1522 struct l2_bucket *l2b; 1523 1524 if (vector_page < KERNEL_BASE) { 1525 /* 1526 * Map the vector page. 1527 */ 1528 pmap_enter(pm, vector_page, systempage.pv_pa, 1529 VM_PROT_READ, VM_PROT_READ | PMAP_WIRED); 1530 pmap_update(pm); 1531 1532 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 1533 l2b = pmap_get_l2_bucket(pm, vector_page); 1534 KDASSERT(l2b != NULL); 1535 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 1536 L1_C_DOM(pm->pm_domain); 1537 } else 1538 pm->pm_pl1vec = NULL; 1539 } 1540 1541 #ifdef PMAP_CACHE_VIVT 1542 /* 1543 * Since we have a virtually indexed cache, we may need to inhibit caching if 1544 * there is more than one mapping and at least one of them is writable. 1545 * Since we purge the cache on every context switch, we only need to check for 1546 * other mappings within the same pmap, or kernel_pmap. 1547 * This function is also called when a page is unmapped, to possibly reenable 1548 * caching on any remaining mappings. 1549 * 1550 * The code implements the following logic, where: 1551 * 1552 * KW = # of kernel read/write pages 1553 * KR = # of kernel read only pages 1554 * UW = # of user read/write pages 1555 * UR = # of user read only pages 1556 * 1557 * KC = kernel mapping is cacheable 1558 * UC = user mapping is cacheable 1559 * 1560 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1561 * +--------------------------------------------- 1562 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1563 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1564 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1565 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1566 */ 1567 1568 static const int pmap_vac_flags[4][4] = { 1569 {-1, 0, 0, PVF_KNC}, 1570 {0, 0, PVF_NC, PVF_NC}, 1571 {0, PVF_NC, PVF_NC, PVF_NC}, 1572 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1573 }; 1574 1575 static inline int 1576 pmap_get_vac_flags(const struct vm_page_md *md) 1577 { 1578 int kidx, uidx; 1579 1580 kidx = 0; 1581 if (md->kro_mappings || md->krw_mappings > 1) 1582 kidx |= 1; 1583 if (md->krw_mappings) 1584 kidx |= 2; 1585 1586 uidx = 0; 1587 if (md->uro_mappings || md->urw_mappings > 1) 1588 uidx |= 1; 1589 if (md->urw_mappings) 1590 uidx |= 2; 1591 1592 return (pmap_vac_flags[uidx][kidx]); 1593 } 1594 1595 static inline void 1596 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1597 { 1598 int nattr; 1599 1600 nattr = pmap_get_vac_flags(md); 1601 1602 if (nattr < 0) { 1603 md->pvh_attrs &= ~PVF_NC; 1604 return; 1605 } 1606 1607 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1608 return; 1609 1610 if (pm == pmap_kernel()) 1611 pmap_vac_me_kpmap(md, pa, pm, va); 1612 else 1613 pmap_vac_me_user(md, pa, pm, va); 1614 1615 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1616 } 1617 1618 static void 1619 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1620 { 1621 u_int u_cacheable, u_entries; 1622 struct pv_entry *pv; 1623 pmap_t last_pmap = pm; 1624 1625 /* 1626 * Pass one, see if there are both kernel and user pmaps for 1627 * this page. Calculate whether there are user-writable or 1628 * kernel-writable pages. 1629 */ 1630 u_cacheable = 0; 1631 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1632 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1633 u_cacheable++; 1634 } 1635 1636 u_entries = md->urw_mappings + md->uro_mappings; 1637 1638 /* 1639 * We know we have just been updating a kernel entry, so if 1640 * all user pages are already cacheable, then there is nothing 1641 * further to do. 1642 */ 1643 if (md->k_mappings == 0 && u_cacheable == u_entries) 1644 return; 1645 1646 if (u_entries) { 1647 /* 1648 * Scan over the list again, for each entry, if it 1649 * might not be set correctly, call pmap_vac_me_user 1650 * to recalculate the settings. 1651 */ 1652 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1653 /* 1654 * We know kernel mappings will get set 1655 * correctly in other calls. We also know 1656 * that if the pmap is the same as last_pmap 1657 * then we've just handled this entry. 1658 */ 1659 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1660 continue; 1661 1662 /* 1663 * If there are kernel entries and this page 1664 * is writable but non-cacheable, then we can 1665 * skip this entry also. 1666 */ 1667 if (md->k_mappings && 1668 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1669 (PVF_NC | PVF_WRITE)) 1670 continue; 1671 1672 /* 1673 * Similarly if there are no kernel-writable 1674 * entries and the page is already 1675 * read-only/cacheable. 1676 */ 1677 if (md->krw_mappings == 0 && 1678 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1679 continue; 1680 1681 /* 1682 * For some of the remaining cases, we know 1683 * that we must recalculate, but for others we 1684 * can't tell if they are correct or not, so 1685 * we recalculate anyway. 1686 */ 1687 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1688 } 1689 1690 if (md->k_mappings == 0) 1691 return; 1692 } 1693 1694 pmap_vac_me_user(md, pa, pm, va); 1695 } 1696 1697 static void 1698 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1699 { 1700 pmap_t kpmap = pmap_kernel(); 1701 struct pv_entry *pv, *npv = NULL; 1702 struct l2_bucket *l2b; 1703 pt_entry_t *ptep, pte; 1704 u_int entries = 0; 1705 u_int writable = 0; 1706 u_int cacheable_entries = 0; 1707 u_int kern_cacheable = 0; 1708 u_int other_writable = 0; 1709 1710 /* 1711 * Count mappings and writable mappings in this pmap. 1712 * Include kernel mappings as part of our own. 1713 * Keep a pointer to the first one. 1714 */ 1715 npv = NULL; 1716 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1717 /* Count mappings in the same pmap */ 1718 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1719 if (entries++ == 0) 1720 npv = pv; 1721 1722 /* Cacheable mappings */ 1723 if ((pv->pv_flags & PVF_NC) == 0) { 1724 cacheable_entries++; 1725 if (kpmap == pv->pv_pmap) 1726 kern_cacheable++; 1727 } 1728 1729 /* Writable mappings */ 1730 if (pv->pv_flags & PVF_WRITE) 1731 ++writable; 1732 } else 1733 if (pv->pv_flags & PVF_WRITE) 1734 other_writable = 1; 1735 } 1736 1737 /* 1738 * Enable or disable caching as necessary. 1739 * Note: the first entry might be part of the kernel pmap, 1740 * so we can't assume this is indicative of the state of the 1741 * other (maybe non-kpmap) entries. 1742 */ 1743 if ((entries > 1 && writable) || 1744 (entries > 0 && pm == kpmap && other_writable)) { 1745 if (cacheable_entries == 0) 1746 return; 1747 1748 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1749 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1750 (pv->pv_flags & PVF_NC)) 1751 continue; 1752 1753 pv->pv_flags |= PVF_NC; 1754 1755 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1756 KDASSERT(l2b != NULL); 1757 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1758 pte = *ptep & ~L2_S_CACHE_MASK; 1759 1760 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1761 l2pte_valid(pte)) { 1762 if (PV_BEEN_EXECD(pv->pv_flags)) { 1763 #ifdef PMAP_CACHE_VIVT 1764 pmap_idcache_wbinv_range(pv->pv_pmap, 1765 pv->pv_va, PAGE_SIZE); 1766 #endif 1767 pmap_tlb_flushID_SE(pv->pv_pmap, 1768 pv->pv_va); 1769 } else 1770 if (PV_BEEN_REFD(pv->pv_flags)) { 1771 #ifdef PMAP_CACHE_VIVT 1772 pmap_dcache_wb_range(pv->pv_pmap, 1773 pv->pv_va, PAGE_SIZE, true, 1774 (pv->pv_flags & PVF_WRITE) == 0); 1775 #endif 1776 pmap_tlb_flushD_SE(pv->pv_pmap, 1777 pv->pv_va); 1778 } 1779 } 1780 1781 *ptep = pte; 1782 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1783 } 1784 cpu_cpwait(); 1785 } else 1786 if (entries > cacheable_entries) { 1787 /* 1788 * Turn cacheing back on for some pages. If it is a kernel 1789 * page, only do so if there are no other writable pages. 1790 */ 1791 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1792 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1793 (kpmap != pv->pv_pmap || other_writable))) 1794 continue; 1795 1796 pv->pv_flags &= ~PVF_NC; 1797 1798 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1799 KDASSERT(l2b != NULL); 1800 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1801 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1802 1803 if (l2pte_valid(pte)) { 1804 if (PV_BEEN_EXECD(pv->pv_flags)) { 1805 pmap_tlb_flushID_SE(pv->pv_pmap, 1806 pv->pv_va); 1807 } else 1808 if (PV_BEEN_REFD(pv->pv_flags)) { 1809 pmap_tlb_flushD_SE(pv->pv_pmap, 1810 pv->pv_va); 1811 } 1812 } 1813 1814 *ptep = pte; 1815 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1816 } 1817 } 1818 } 1819 #endif 1820 1821 #ifdef PMAP_CACHE_VIPT 1822 static void 1823 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1824 { 1825 struct pv_entry *pv; 1826 vaddr_t tst_mask; 1827 bool bad_alias; 1828 struct l2_bucket *l2b; 1829 pt_entry_t *ptep, pte, opte; 1830 const u_int 1831 rw_mappings = md->urw_mappings + md->krw_mappings, 1832 ro_mappings = md->uro_mappings + md->kro_mappings; 1833 1834 /* do we need to do anything? */ 1835 if (arm_cache_prefer_mask == 0) 1836 return; 1837 1838 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 1839 md, pm, va)); 1840 1841 KASSERT(!va || pm); 1842 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1843 1844 /* Already a conflict? */ 1845 if (__predict_false(md->pvh_attrs & PVF_NC)) { 1846 /* just an add, things are already non-cached */ 1847 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 1848 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1849 bad_alias = false; 1850 if (va) { 1851 PMAPCOUNT(vac_color_none); 1852 bad_alias = true; 1853 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1854 goto fixup; 1855 } 1856 pv = SLIST_FIRST(&md->pvh_list); 1857 /* the list can't be empty because it would be cachable */ 1858 if (md->pvh_attrs & PVF_KMPAGE) { 1859 tst_mask = md->pvh_attrs; 1860 } else { 1861 KASSERT(pv); 1862 tst_mask = pv->pv_va; 1863 pv = SLIST_NEXT(pv, pv_link); 1864 } 1865 /* 1866 * Only check for a bad alias if we have writable mappings. 1867 */ 1868 tst_mask &= arm_cache_prefer_mask; 1869 if (rw_mappings > 0 && arm_cache_prefer_mask) { 1870 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 1871 /* if there's a bad alias, stop checking. */ 1872 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 1873 bad_alias = true; 1874 } 1875 md->pvh_attrs |= PVF_WRITE; 1876 if (!bad_alias) 1877 md->pvh_attrs |= PVF_DIRTY; 1878 } else { 1879 /* 1880 * We have only read-only mappings. Let's see if there 1881 * are multiple colors in use or if we mapped a KMPAGE. 1882 * If the latter, we have a bad alias. If the former, 1883 * we need to remember that. 1884 */ 1885 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 1886 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 1887 if (md->pvh_attrs & PVF_KMPAGE) 1888 bad_alias = true; 1889 break; 1890 } 1891 } 1892 md->pvh_attrs &= ~PVF_WRITE; 1893 /* 1894 * No KMPAGE and we exited early, so we must have 1895 * multiple color mappings. 1896 */ 1897 if (!bad_alias && pv != NULL) 1898 md->pvh_attrs |= PVF_MULTCLR; 1899 } 1900 1901 /* If no conflicting colors, set everything back to cached */ 1902 if (!bad_alias) { 1903 #ifdef DEBUG 1904 if ((md->pvh_attrs & PVF_WRITE) 1905 || ro_mappings < 2) { 1906 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 1907 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1908 } 1909 #endif 1910 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 1911 md->pvh_attrs |= tst_mask | PVF_COLORED; 1912 /* 1913 * Restore DIRTY bit if page is modified 1914 */ 1915 if (md->pvh_attrs & PVF_DMOD) 1916 md->pvh_attrs |= PVF_DIRTY; 1917 PMAPCOUNT(vac_color_restore); 1918 } else { 1919 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 1920 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 1921 } 1922 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1923 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1924 } else if (!va) { 1925 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 1926 KASSERT(!(md->pvh_attrs & PVF_WRITE) 1927 || (md->pvh_attrs & PVF_DIRTY)); 1928 if (rw_mappings == 0) { 1929 md->pvh_attrs &= ~PVF_WRITE; 1930 if (ro_mappings == 1 1931 && (md->pvh_attrs & PVF_MULTCLR)) { 1932 /* 1933 * If this is the last readonly mapping 1934 * but it doesn't match the current color 1935 * for the page, change the current color 1936 * to match this last readonly mapping. 1937 */ 1938 pv = SLIST_FIRST(&md->pvh_list); 1939 tst_mask = (md->pvh_attrs ^ pv->pv_va) 1940 & arm_cache_prefer_mask; 1941 if (tst_mask) { 1942 md->pvh_attrs ^= tst_mask; 1943 PMAPCOUNT(vac_color_change); 1944 } 1945 } 1946 } 1947 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1948 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1949 return; 1950 } else if (!pmap_is_page_colored_p(md)) { 1951 /* not colored so we just use its color */ 1952 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 1953 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 1954 PMAPCOUNT(vac_color_new); 1955 md->pvh_attrs &= PAGE_SIZE - 1; 1956 md->pvh_attrs |= PVF_COLORED 1957 | (va & arm_cache_prefer_mask) 1958 | (rw_mappings > 0 ? PVF_WRITE : 0); 1959 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1960 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 1961 return; 1962 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 1963 bad_alias = false; 1964 if (rw_mappings > 0) { 1965 /* 1966 * We now have writeable mappings and if we have 1967 * readonly mappings in more than once color, we have 1968 * an aliasing problem. Regardless mark the page as 1969 * writeable. 1970 */ 1971 if (md->pvh_attrs & PVF_MULTCLR) { 1972 if (ro_mappings < 2) { 1973 /* 1974 * If we only have less than two 1975 * read-only mappings, just flush the 1976 * non-primary colors from the cache. 1977 */ 1978 pmap_flush_page(md, pa, 1979 PMAP_FLUSH_SECONDARY); 1980 } else { 1981 bad_alias = true; 1982 } 1983 } 1984 md->pvh_attrs |= PVF_WRITE; 1985 } 1986 /* If no conflicting colors, set everything back to cached */ 1987 if (!bad_alias) { 1988 #ifdef DEBUG 1989 if (rw_mappings > 0 1990 || (md->pvh_attrs & PMAP_KMPAGE)) { 1991 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 1992 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 1993 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 1994 } 1995 #endif 1996 if (SLIST_EMPTY(&md->pvh_list)) 1997 PMAPCOUNT(vac_color_reuse); 1998 else 1999 PMAPCOUNT(vac_color_ok); 2000 2001 /* matching color, just return */ 2002 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2003 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2004 return; 2005 } 2006 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2007 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2008 2009 /* color conflict. evict from cache. */ 2010 2011 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2012 md->pvh_attrs &= ~PVF_COLORED; 2013 md->pvh_attrs |= PVF_NC; 2014 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2015 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2016 PMAPCOUNT(vac_color_erase); 2017 } else if (rw_mappings == 0 2018 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2019 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2020 2021 /* 2022 * If the page has dirty cache lines, clean it. 2023 */ 2024 if (md->pvh_attrs & PVF_DIRTY) 2025 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2026 2027 /* 2028 * If this is the first remapping (we know that there are no 2029 * writeable mappings), then this is a simple color change. 2030 * Otherwise this is a seconary r/o mapping, which means 2031 * we don't have to do anything. 2032 */ 2033 if (ro_mappings == 1) { 2034 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2035 md->pvh_attrs &= PAGE_SIZE - 1; 2036 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2037 PMAPCOUNT(vac_color_change); 2038 } else { 2039 PMAPCOUNT(vac_color_blind); 2040 } 2041 md->pvh_attrs |= PVF_MULTCLR; 2042 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2043 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2044 return; 2045 } else { 2046 if (rw_mappings > 0) 2047 md->pvh_attrs |= PVF_WRITE; 2048 2049 /* color conflict. evict from cache. */ 2050 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2051 2052 /* the list can't be empty because this was a enter/modify */ 2053 pv = SLIST_FIRST(&md->pvh_list); 2054 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2055 KASSERT(pv); 2056 /* 2057 * If there's only one mapped page, change color to the 2058 * page's new color and return. Restore the DIRTY bit 2059 * that was erased by pmap_flush_page. 2060 */ 2061 if (SLIST_NEXT(pv, pv_link) == NULL) { 2062 md->pvh_attrs &= PAGE_SIZE - 1; 2063 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2064 if (md->pvh_attrs & PVF_DMOD) 2065 md->pvh_attrs |= PVF_DIRTY; 2066 PMAPCOUNT(vac_color_change); 2067 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2068 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2069 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2070 return; 2071 } 2072 } 2073 bad_alias = true; 2074 md->pvh_attrs &= ~PVF_COLORED; 2075 md->pvh_attrs |= PVF_NC; 2076 PMAPCOUNT(vac_color_erase); 2077 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2078 } 2079 2080 fixup: 2081 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2082 2083 /* 2084 * Turn cacheing on/off for all pages. 2085 */ 2086 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2087 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2088 KDASSERT(l2b != NULL); 2089 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2090 opte = *ptep; 2091 pte = opte & ~L2_S_CACHE_MASK; 2092 if (bad_alias) { 2093 pv->pv_flags |= PVF_NC; 2094 } else { 2095 pv->pv_flags &= ~PVF_NC; 2096 pte |= pte_l2_s_cache_mode; 2097 } 2098 2099 if (opte == pte) /* only update is there's a change */ 2100 continue; 2101 2102 if (l2pte_valid(pte)) { 2103 if (PV_BEEN_EXECD(pv->pv_flags)) { 2104 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 2105 } else if (PV_BEEN_REFD(pv->pv_flags)) { 2106 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va); 2107 } 2108 } 2109 2110 *ptep = pte; 2111 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2112 } 2113 } 2114 #endif /* PMAP_CACHE_VIPT */ 2115 2116 2117 /* 2118 * Modify pte bits for all ptes corresponding to the given physical address. 2119 * We use `maskbits' rather than `clearbits' because we're always passing 2120 * constants and the latter would require an extra inversion at run-time. 2121 */ 2122 static void 2123 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2124 { 2125 struct l2_bucket *l2b; 2126 struct pv_entry *pv; 2127 pt_entry_t *ptep, npte, opte; 2128 pmap_t pm; 2129 vaddr_t va; 2130 u_int oflags; 2131 #ifdef PMAP_CACHE_VIPT 2132 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2133 bool need_syncicache = false; 2134 bool did_syncicache = false; 2135 bool need_vac_me_harder = false; 2136 #endif 2137 2138 NPDEBUG(PDB_BITS, 2139 printf("pmap_clearbit: md %p mask 0x%x\n", 2140 md, maskbits)); 2141 2142 PMAP_HEAD_TO_MAP_LOCK(); 2143 simple_lock(&md->pvh_slock); 2144 2145 #ifdef PMAP_CACHE_VIPT 2146 /* 2147 * If we might want to sync the I-cache and we've modified it, 2148 * then we know we definitely need to sync or discard it. 2149 */ 2150 if (want_syncicache) 2151 need_syncicache = md->pvh_attrs & PVF_MOD; 2152 #endif 2153 /* 2154 * Clear saved attributes (modify, reference) 2155 */ 2156 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2157 2158 if (SLIST_EMPTY(&md->pvh_list)) { 2159 #ifdef PMAP_CACHE_VIPT 2160 if (need_syncicache) { 2161 /* 2162 * No one has it mapped, so just discard it. The next 2163 * exec remapping will cause it to be synced. 2164 */ 2165 md->pvh_attrs &= ~PVF_EXEC; 2166 PMAPCOUNT(exec_discarded_clearbit); 2167 } 2168 #endif 2169 simple_unlock(&md->pvh_slock); 2170 PMAP_HEAD_TO_MAP_UNLOCK(); 2171 return; 2172 } 2173 2174 /* 2175 * Loop over all current mappings setting/clearing as appropos 2176 */ 2177 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2178 va = pv->pv_va; 2179 pm = pv->pv_pmap; 2180 oflags = pv->pv_flags; 2181 /* 2182 * Kernel entries are unmanaged and as such not to be changed. 2183 */ 2184 if (oflags & PVF_KENTRY) 2185 continue; 2186 pv->pv_flags &= ~maskbits; 2187 2188 pmap_acquire_pmap_lock(pm); 2189 2190 l2b = pmap_get_l2_bucket(pm, va); 2191 KDASSERT(l2b != NULL); 2192 2193 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2194 npte = opte = *ptep; 2195 2196 NPDEBUG(PDB_BITS, 2197 printf( 2198 "pmap_clearbit: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2199 pv, pv->pv_pmap, pv->pv_va, oflags)); 2200 2201 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2202 #ifdef PMAP_CACHE_VIVT 2203 if ((pv->pv_flags & PVF_NC)) { 2204 /* 2205 * Entry is not cacheable: 2206 * 2207 * Don't turn caching on again if this is a 2208 * modified emulation. This would be 2209 * inconsitent with the settings created by 2210 * pmap_vac_me_harder(). Otherwise, it's safe 2211 * to re-enable cacheing. 2212 * 2213 * There's no need to call pmap_vac_me_harder() 2214 * here: all pages are losing their write 2215 * permission. 2216 */ 2217 if (maskbits & PVF_WRITE) { 2218 npte |= pte_l2_s_cache_mode; 2219 pv->pv_flags &= ~PVF_NC; 2220 } 2221 } else 2222 if (l2pte_writable_p(opte)) { 2223 /* 2224 * Entry is writable/cacheable: check if pmap 2225 * is current if it is flush it, otherwise it 2226 * won't be in the cache 2227 */ 2228 if (PV_BEEN_EXECD(oflags)) 2229 pmap_idcache_wbinv_range(pm, pv->pv_va, 2230 PAGE_SIZE); 2231 else 2232 if (PV_BEEN_REFD(oflags)) 2233 pmap_dcache_wb_range(pm, pv->pv_va, 2234 PAGE_SIZE, 2235 (maskbits & PVF_REF) != 0, false); 2236 } 2237 #endif 2238 2239 /* make the pte read only */ 2240 npte = l2pte_set_readonly(npte); 2241 2242 if (maskbits & oflags & PVF_WRITE) { 2243 /* 2244 * Keep alias accounting up to date 2245 */ 2246 if (pv->pv_pmap == pmap_kernel()) { 2247 md->krw_mappings--; 2248 md->kro_mappings++; 2249 } else { 2250 md->urw_mappings--; 2251 md->uro_mappings++; 2252 } 2253 #ifdef PMAP_CACHE_VIPT 2254 if (md->urw_mappings + md->krw_mappings == 0) 2255 md->pvh_attrs &= ~PVF_WRITE; 2256 if (want_syncicache) 2257 need_syncicache = true; 2258 need_vac_me_harder = true; 2259 #endif 2260 } 2261 } 2262 2263 if (maskbits & PVF_REF) { 2264 if ((pv->pv_flags & PVF_NC) == 0 && 2265 (maskbits & (PVF_WRITE|PVF_MOD)) == 0 && 2266 l2pte_valid(npte)) { 2267 #ifdef PMAP_CACHE_VIVT 2268 /* 2269 * Check npte here; we may have already 2270 * done the wbinv above, and the validity 2271 * of the PTE is the same for opte and 2272 * npte. 2273 */ 2274 /* XXXJRT need idcache_inv_range */ 2275 if (PV_BEEN_EXECD(oflags)) 2276 pmap_idcache_wbinv_range(pm, 2277 pv->pv_va, PAGE_SIZE); 2278 else 2279 if (PV_BEEN_REFD(oflags)) 2280 pmap_dcache_wb_range(pm, 2281 pv->pv_va, PAGE_SIZE, 2282 true, true); 2283 #endif 2284 } 2285 2286 /* 2287 * Make the PTE invalid so that we will take a 2288 * page fault the next time the mapping is 2289 * referenced. 2290 */ 2291 npte &= ~L2_TYPE_MASK; 2292 npte |= L2_TYPE_INV; 2293 } 2294 2295 if (npte != opte) { 2296 *ptep = npte; 2297 PTE_SYNC(ptep); 2298 /* Flush the TLB entry if a current pmap. */ 2299 if (PV_BEEN_EXECD(oflags)) 2300 pmap_tlb_flushID_SE(pm, pv->pv_va); 2301 else 2302 if (PV_BEEN_REFD(oflags)) 2303 pmap_tlb_flushD_SE(pm, pv->pv_va); 2304 } 2305 2306 pmap_release_pmap_lock(pm); 2307 2308 NPDEBUG(PDB_BITS, 2309 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2310 pm, va, opte, npte)); 2311 } 2312 2313 #ifdef PMAP_CACHE_VIPT 2314 /* 2315 * If we need to sync the I-cache and we haven't done it yet, do it. 2316 */ 2317 if (need_syncicache && !did_syncicache) { 2318 pmap_syncicache_page(md, pa); 2319 PMAPCOUNT(exec_synced_clearbit); 2320 } 2321 /* 2322 * If we are changing this to read-only, we need to call vac_me_harder 2323 * so we can change all the read-only pages to cacheable. We pretend 2324 * this as a page deletion. 2325 */ 2326 if (need_vac_me_harder) { 2327 if (md->pvh_attrs & PVF_NC) 2328 pmap_vac_me_harder(md, pa, NULL, 0); 2329 } 2330 #endif 2331 2332 simple_unlock(&md->pvh_slock); 2333 PMAP_HEAD_TO_MAP_UNLOCK(); 2334 } 2335 2336 /* 2337 * pmap_clean_page() 2338 * 2339 * This is a local function used to work out the best strategy to clean 2340 * a single page referenced by its entry in the PV table. It's used by 2341 * pmap_copy_page, pmap_zero page and maybe some others later on. 2342 * 2343 * Its policy is effectively: 2344 * o If there are no mappings, we don't bother doing anything with the cache. 2345 * o If there is one mapping, we clean just that page. 2346 * o If there are multiple mappings, we clean the entire cache. 2347 * 2348 * So that some functions can be further optimised, it returns 0 if it didn't 2349 * clean the entire cache, or 1 if it did. 2350 * 2351 * XXX One bug in this routine is that if the pv_entry has a single page 2352 * mapped at 0x00000000 a whole cache clean will be performed rather than 2353 * just the 1 page. Since this should not occur in everyday use and if it does 2354 * it will just result in not the most efficient clean for the page. 2355 */ 2356 #ifdef PMAP_CACHE_VIVT 2357 static int 2358 pmap_clean_page(struct pv_entry *pv, bool is_src) 2359 { 2360 pmap_t pm_to_clean = NULL; 2361 struct pv_entry *npv; 2362 u_int cache_needs_cleaning = 0; 2363 u_int flags = 0; 2364 vaddr_t page_to_clean = 0; 2365 2366 if (pv == NULL) { 2367 /* nothing mapped in so nothing to flush */ 2368 return (0); 2369 } 2370 2371 /* 2372 * Since we flush the cache each time we change to a different 2373 * user vmspace, we only need to flush the page if it is in the 2374 * current pmap. 2375 */ 2376 2377 for (npv = pv; npv; npv = SLIST_NEXT(npv, pv_link)) { 2378 if (pmap_is_current(npv->pv_pmap)) { 2379 flags |= npv->pv_flags; 2380 /* 2381 * The page is mapped non-cacheable in 2382 * this map. No need to flush the cache. 2383 */ 2384 if (npv->pv_flags & PVF_NC) { 2385 #ifdef DIAGNOSTIC 2386 if (cache_needs_cleaning) 2387 panic("pmap_clean_page: " 2388 "cache inconsistency"); 2389 #endif 2390 break; 2391 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 2392 continue; 2393 if (cache_needs_cleaning) { 2394 page_to_clean = 0; 2395 break; 2396 } else { 2397 page_to_clean = npv->pv_va; 2398 pm_to_clean = npv->pv_pmap; 2399 } 2400 cache_needs_cleaning = 1; 2401 } 2402 } 2403 2404 if (page_to_clean) { 2405 if (PV_BEEN_EXECD(flags)) 2406 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 2407 PAGE_SIZE); 2408 else 2409 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 2410 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 2411 } else if (cache_needs_cleaning) { 2412 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2413 2414 if (PV_BEEN_EXECD(flags)) 2415 pmap_idcache_wbinv_all(pm); 2416 else 2417 pmap_dcache_wbinv_all(pm); 2418 return (1); 2419 } 2420 return (0); 2421 } 2422 #endif 2423 2424 #ifdef PMAP_CACHE_VIPT 2425 /* 2426 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2427 * right cache alias to make sure we flush the right stuff. 2428 */ 2429 void 2430 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2431 { 2432 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2433 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 2434 2435 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2436 md, md->pvh_attrs)); 2437 /* 2438 * No need to clean the page if it's non-cached. 2439 */ 2440 if (md->pvh_attrs & PVF_NC) 2441 return; 2442 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2443 2444 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2445 /* 2446 * Set up a PTE with the right coloring to flush existing cache lines. 2447 */ 2448 *ptep = L2_S_PROTO | 2449 pa 2450 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2451 | pte_l2_s_cache_mode; 2452 PTE_SYNC(ptep); 2453 2454 /* 2455 * Flush it. 2456 */ 2457 cpu_icache_sync_range(cdstp + va_offset, PAGE_SIZE); 2458 /* 2459 * Unmap the page. 2460 */ 2461 *ptep = 0; 2462 PTE_SYNC(ptep); 2463 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2464 2465 md->pvh_attrs |= PVF_EXEC; 2466 PMAPCOUNT(exec_synced); 2467 } 2468 2469 void 2470 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2471 { 2472 vsize_t va_offset, end_va; 2473 void (*cf)(vaddr_t, vsize_t); 2474 2475 if (arm_cache_prefer_mask == 0) 2476 return; 2477 2478 switch (flush) { 2479 case PMAP_FLUSH_PRIMARY: 2480 if (md->pvh_attrs & PVF_MULTCLR) { 2481 va_offset = 0; 2482 end_va = arm_cache_prefer_mask; 2483 md->pvh_attrs &= ~PVF_MULTCLR; 2484 PMAPCOUNT(vac_flush_lots); 2485 } else { 2486 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2487 end_va = va_offset; 2488 PMAPCOUNT(vac_flush_one); 2489 } 2490 /* 2491 * Mark that the page is no longer dirty. 2492 */ 2493 md->pvh_attrs &= ~PVF_DIRTY; 2494 cf = cpufuncs.cf_idcache_wbinv_range; 2495 break; 2496 case PMAP_FLUSH_SECONDARY: 2497 va_offset = 0; 2498 end_va = arm_cache_prefer_mask; 2499 cf = cpufuncs.cf_idcache_wbinv_range; 2500 md->pvh_attrs &= ~PVF_MULTCLR; 2501 PMAPCOUNT(vac_flush_lots); 2502 break; 2503 case PMAP_CLEAN_PRIMARY: 2504 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2505 end_va = va_offset; 2506 cf = cpufuncs.cf_dcache_wb_range; 2507 /* 2508 * Mark that the page is no longer dirty. 2509 */ 2510 if ((md->pvh_attrs & PVF_DMOD) == 0) 2511 md->pvh_attrs &= ~PVF_DIRTY; 2512 PMAPCOUNT(vac_clean_one); 2513 break; 2514 default: 2515 return; 2516 } 2517 2518 KASSERT(!(md->pvh_attrs & PVF_NC)); 2519 2520 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2521 md, md->pvh_attrs)); 2522 2523 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2524 const size_t pte_offset = va_offset >> PGSHIFT; 2525 pt_entry_t * const ptep = &cdst_pte[pte_offset]; 2526 const pt_entry_t oldpte = *ptep; 2527 2528 if (flush == PMAP_FLUSH_SECONDARY 2529 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2530 continue; 2531 2532 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2533 /* 2534 * Set up a PTE with the right coloring to flush 2535 * existing cache entries. 2536 */ 2537 *ptep = L2_S_PROTO 2538 | pa 2539 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2540 | pte_l2_s_cache_mode; 2541 PTE_SYNC(ptep); 2542 2543 /* 2544 * Flush it. 2545 */ 2546 (*cf)(cdstp + va_offset, PAGE_SIZE); 2547 2548 /* 2549 * Restore the page table entry since we might have interrupted 2550 * pmap_zero_page or pmap_copy_page which was already using 2551 * this pte. 2552 */ 2553 *ptep = oldpte; 2554 PTE_SYNC(ptep); 2555 pmap_tlb_flushID_SE(pmap_kernel(), cdstp + va_offset); 2556 } 2557 } 2558 #endif /* PMAP_CACHE_VIPT */ 2559 2560 /* 2561 * Routine: pmap_page_remove 2562 * Function: 2563 * Removes this physical page from 2564 * all physical maps in which it resides. 2565 * Reflects back modify bits to the pager. 2566 */ 2567 static void 2568 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2569 { 2570 struct l2_bucket *l2b; 2571 struct pv_entry *pv, *npv, **pvp; 2572 pmap_t pm; 2573 pt_entry_t *ptep; 2574 bool flush; 2575 u_int flags; 2576 2577 NPDEBUG(PDB_FOLLOW, 2578 printf("pmap_page_remove: md %p (0x%08lx)\n", md, 2579 pa)); 2580 2581 PMAP_HEAD_TO_MAP_LOCK(); 2582 simple_lock(&md->pvh_slock); 2583 2584 pv = SLIST_FIRST(&md->pvh_list); 2585 if (pv == NULL) { 2586 #ifdef PMAP_CACHE_VIPT 2587 /* 2588 * We *know* the page contents are about to be replaced. 2589 * Discard the exec contents 2590 */ 2591 if (PV_IS_EXEC_P(md->pvh_attrs)) 2592 PMAPCOUNT(exec_discarded_page_protect); 2593 md->pvh_attrs &= ~PVF_EXEC; 2594 KASSERT((md->urw_mappings + md->krw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2595 #endif 2596 simple_unlock(&md->pvh_slock); 2597 PMAP_HEAD_TO_MAP_UNLOCK(); 2598 return; 2599 } 2600 #ifdef PMAP_CACHE_VIPT 2601 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2602 #endif 2603 2604 /* 2605 * Clear alias counts 2606 */ 2607 #ifdef PMAP_CACHE_VIVT 2608 md->k_mappings = 0; 2609 #endif 2610 md->urw_mappings = md->uro_mappings = 0; 2611 2612 flush = false; 2613 flags = 0; 2614 2615 #ifdef PMAP_CACHE_VIVT 2616 pmap_clean_page(pv, false); 2617 #endif 2618 2619 pvp = &SLIST_FIRST(&md->pvh_list); 2620 while (pv) { 2621 pm = pv->pv_pmap; 2622 npv = SLIST_NEXT(pv, pv_link); 2623 if (flush == false && pmap_is_current(pm)) 2624 flush = true; 2625 2626 if (pm == pmap_kernel()) { 2627 #ifdef PMAP_CACHE_VIPT 2628 /* 2629 * If this was unmanaged mapping, it must be preserved. 2630 * Move it back on the list and advance the end-of-list 2631 * pointer. 2632 */ 2633 if (pv->pv_flags & PVF_KENTRY) { 2634 *pvp = pv; 2635 pvp = &SLIST_NEXT(pv, pv_link); 2636 pv = npv; 2637 continue; 2638 } 2639 if (pv->pv_flags & PVF_WRITE) 2640 md->krw_mappings--; 2641 else 2642 md->kro_mappings--; 2643 #endif 2644 PMAPCOUNT(kernel_unmappings); 2645 } 2646 PMAPCOUNT(unmappings); 2647 2648 pmap_acquire_pmap_lock(pm); 2649 2650 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2651 KDASSERT(l2b != NULL); 2652 2653 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2654 2655 /* 2656 * Update statistics 2657 */ 2658 --pm->pm_stats.resident_count; 2659 2660 /* Wired bit */ 2661 if (pv->pv_flags & PVF_WIRED) 2662 --pm->pm_stats.wired_count; 2663 2664 flags |= pv->pv_flags; 2665 2666 /* 2667 * Invalidate the PTEs. 2668 */ 2669 *ptep = 0; 2670 PTE_SYNC_CURRENT(pm, ptep); 2671 pmap_free_l2_bucket(pm, l2b, 1); 2672 2673 pool_put(&pmap_pv_pool, pv); 2674 pv = npv; 2675 /* 2676 * if we reach the end of the list and there are still 2677 * mappings, they might be able to be cached now. 2678 */ 2679 if (pv == NULL) { 2680 *pvp = NULL; 2681 if (!SLIST_EMPTY(&md->pvh_list)) 2682 pmap_vac_me_harder(md, pa, pm, 0); 2683 } 2684 pmap_release_pmap_lock(pm); 2685 } 2686 #ifdef PMAP_CACHE_VIPT 2687 /* 2688 * Its EXEC cache is now gone. 2689 */ 2690 if (PV_IS_EXEC_P(md->pvh_attrs)) 2691 PMAPCOUNT(exec_discarded_page_protect); 2692 md->pvh_attrs &= ~PVF_EXEC; 2693 KASSERT(md->urw_mappings == 0); 2694 KASSERT(md->uro_mappings == 0); 2695 if (md->krw_mappings == 0) 2696 md->pvh_attrs &= ~PVF_WRITE; 2697 KASSERT((md->urw_mappings + md->krw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2698 #endif 2699 simple_unlock(&md->pvh_slock); 2700 PMAP_HEAD_TO_MAP_UNLOCK(); 2701 2702 if (flush) { 2703 /* 2704 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2705 * would need a subsequent call to pmap_update() to ensure 2706 * curpm->pm_cstate.cs_all is reset. Our callers are not 2707 * required to do that (see pmap(9)), so we can't modify 2708 * the current pmap's state. 2709 */ 2710 if (PV_BEEN_EXECD(flags)) 2711 cpu_tlb_flushID(); 2712 else 2713 cpu_tlb_flushD(); 2714 } 2715 cpu_cpwait(); 2716 } 2717 2718 /* 2719 * pmap_t pmap_create(void) 2720 * 2721 * Create a new pmap structure from scratch. 2722 */ 2723 pmap_t 2724 pmap_create(void) 2725 { 2726 pmap_t pm; 2727 2728 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2729 2730 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 2731 pm->pm_stats.wired_count = 0; 2732 pm->pm_stats.resident_count = 1; 2733 pm->pm_cstate.cs_all = 0; 2734 pmap_alloc_l1(pm); 2735 2736 /* 2737 * Note: The pool cache ensures that the pm_l2[] array is already 2738 * initialised to zero. 2739 */ 2740 2741 pmap_pinit(pm); 2742 2743 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 2744 2745 return (pm); 2746 } 2747 2748 /* 2749 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 2750 * u_int flags) 2751 * 2752 * Insert the given physical page (p) at 2753 * the specified virtual address (v) in the 2754 * target physical map with the protection requested. 2755 * 2756 * NB: This is the only routine which MAY NOT lazy-evaluate 2757 * or lose information. That is, this routine must actually 2758 * insert this page into the given map NOW. 2759 */ 2760 int 2761 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 2762 { 2763 struct l2_bucket *l2b; 2764 struct vm_page *pg, *opg; 2765 struct pv_entry *pv; 2766 pt_entry_t *ptep, npte, opte; 2767 u_int nflags; 2768 u_int oflags; 2769 2770 NPDEBUG(PDB_ENTER, printf("pmap_enter: pm %p va 0x%lx pa 0x%lx prot %x flag %x\n", pm, va, pa, prot, flags)); 2771 2772 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 2773 KDASSERT(((va | pa) & PGOFSET) == 0); 2774 2775 /* 2776 * Get a pointer to the page. Later on in this function, we 2777 * test for a managed page by checking pg != NULL. 2778 */ 2779 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 2780 2781 nflags = 0; 2782 if (prot & VM_PROT_WRITE) 2783 nflags |= PVF_WRITE; 2784 if (prot & VM_PROT_EXECUTE) 2785 nflags |= PVF_EXEC; 2786 if (flags & PMAP_WIRED) 2787 nflags |= PVF_WIRED; 2788 2789 PMAP_MAP_TO_HEAD_LOCK(); 2790 pmap_acquire_pmap_lock(pm); 2791 2792 /* 2793 * Fetch the L2 bucket which maps this page, allocating one if 2794 * necessary for user pmaps. 2795 */ 2796 if (pm == pmap_kernel()) 2797 l2b = pmap_get_l2_bucket(pm, va); 2798 else 2799 l2b = pmap_alloc_l2_bucket(pm, va); 2800 if (l2b == NULL) { 2801 if (flags & PMAP_CANFAIL) { 2802 pmap_release_pmap_lock(pm); 2803 PMAP_MAP_TO_HEAD_UNLOCK(); 2804 return (ENOMEM); 2805 } 2806 panic("pmap_enter: failed to allocate L2 bucket"); 2807 } 2808 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2809 opte = *ptep; 2810 npte = pa; 2811 oflags = 0; 2812 2813 if (opte) { 2814 /* 2815 * There is already a mapping at this address. 2816 * If the physical address is different, lookup the 2817 * vm_page. 2818 */ 2819 if (l2pte_pa(opte) != pa) 2820 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 2821 else 2822 opg = pg; 2823 } else 2824 opg = NULL; 2825 2826 if (pg) { 2827 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 2828 2829 /* 2830 * This is to be a managed mapping. 2831 */ 2832 if ((flags & VM_PROT_ALL) || 2833 (md->pvh_attrs & PVF_REF)) { 2834 /* 2835 * - The access type indicates that we don't need 2836 * to do referenced emulation. 2837 * OR 2838 * - The physical page has already been referenced 2839 * so no need to re-do referenced emulation here. 2840 */ 2841 npte |= l2pte_set_readonly(L2_S_PROTO); 2842 2843 nflags |= PVF_REF; 2844 2845 if ((prot & VM_PROT_WRITE) != 0 && 2846 ((flags & VM_PROT_WRITE) != 0 || 2847 (md->pvh_attrs & PVF_MOD) != 0)) { 2848 /* 2849 * This is a writable mapping, and the 2850 * page's mod state indicates it has 2851 * already been modified. Make it 2852 * writable from the outset. 2853 */ 2854 npte = l2pte_set_writable(npte); 2855 nflags |= PVF_MOD; 2856 } 2857 } else { 2858 /* 2859 * Need to do page referenced emulation. 2860 */ 2861 npte |= L2_TYPE_INV; 2862 } 2863 2864 npte |= pte_l2_s_cache_mode; 2865 2866 if (pg == opg) { 2867 /* 2868 * We're changing the attrs of an existing mapping. 2869 */ 2870 simple_lock(&md->pvh_slock); 2871 oflags = pmap_modify_pv(md, pa, pm, va, 2872 PVF_WRITE | PVF_EXEC | PVF_WIRED | 2873 PVF_MOD | PVF_REF, nflags); 2874 simple_unlock(&md->pvh_slock); 2875 2876 #ifdef PMAP_CACHE_VIVT 2877 /* 2878 * We may need to flush the cache if we're 2879 * doing rw-ro... 2880 */ 2881 if (pm->pm_cstate.cs_cache_d && 2882 (oflags & PVF_NC) == 0 && 2883 l2pte_writable_p(opte) && 2884 (prot & VM_PROT_WRITE) == 0) 2885 cpu_dcache_wb_range(va, PAGE_SIZE); 2886 #endif 2887 } else { 2888 /* 2889 * New mapping, or changing the backing page 2890 * of an existing mapping. 2891 */ 2892 if (opg) { 2893 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2894 paddr_t opa = VM_PAGE_TO_PHYS(opg); 2895 2896 /* 2897 * Replacing an existing mapping with a new one. 2898 * It is part of our managed memory so we 2899 * must remove it from the PV list 2900 */ 2901 simple_lock(&omd->pvh_slock); 2902 pv = pmap_remove_pv(omd, opa, pm, va); 2903 pmap_vac_me_harder(omd, opa, pm, 0); 2904 simple_unlock(&omd->pvh_slock); 2905 oflags = pv->pv_flags; 2906 2907 #ifdef PMAP_CACHE_VIVT 2908 /* 2909 * If the old mapping was valid (ref/mod 2910 * emulation creates 'invalid' mappings 2911 * initially) then make sure to frob 2912 * the cache. 2913 */ 2914 if ((oflags & PVF_NC) == 0 && 2915 l2pte_valid(opte)) { 2916 if (PV_BEEN_EXECD(oflags)) { 2917 pmap_idcache_wbinv_range(pm, va, 2918 PAGE_SIZE); 2919 } else 2920 if (PV_BEEN_REFD(oflags)) { 2921 pmap_dcache_wb_range(pm, va, 2922 PAGE_SIZE, true, 2923 (oflags & PVF_WRITE) == 0); 2924 } 2925 } 2926 #endif 2927 } else 2928 if ((pv = pool_get(&pmap_pv_pool, PR_NOWAIT)) == NULL){ 2929 if ((flags & PMAP_CANFAIL) == 0) 2930 panic("pmap_enter: no pv entries"); 2931 2932 if (pm != pmap_kernel()) 2933 pmap_free_l2_bucket(pm, l2b, 0); 2934 pmap_release_pmap_lock(pm); 2935 PMAP_MAP_TO_HEAD_UNLOCK(); 2936 NPDEBUG(PDB_ENTER, 2937 printf("pmap_enter: ENOMEM\n")); 2938 return (ENOMEM); 2939 } 2940 2941 pmap_enter_pv(md, pa, pv, pm, va, nflags); 2942 } 2943 } else { 2944 /* 2945 * We're mapping an unmanaged page. 2946 * These are always readable, and possibly writable, from 2947 * the get go as we don't need to track ref/mod status. 2948 */ 2949 npte |= l2pte_set_readonly(L2_S_PROTO); 2950 if (prot & VM_PROT_WRITE) 2951 npte = l2pte_set_writable(npte); 2952 2953 /* 2954 * Make sure the vector table is mapped cacheable 2955 */ 2956 if (pm != pmap_kernel() && va == vector_page) 2957 npte |= pte_l2_s_cache_mode; 2958 2959 if (opg) { 2960 /* 2961 * Looks like there's an existing 'managed' mapping 2962 * at this address. 2963 */ 2964 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 2965 paddr_t opa = VM_PAGE_TO_PHYS(opg); 2966 2967 simple_lock(&omd->pvh_slock); 2968 pv = pmap_remove_pv(omd, opa, pm, va); 2969 pmap_vac_me_harder(omd, opa, pm, 0); 2970 simple_unlock(&omd->pvh_slock); 2971 oflags = pv->pv_flags; 2972 2973 #ifdef PMAP_CACHE_VIVT 2974 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 2975 if (PV_BEEN_EXECD(oflags)) 2976 pmap_idcache_wbinv_range(pm, va, 2977 PAGE_SIZE); 2978 else 2979 if (PV_BEEN_REFD(oflags)) 2980 pmap_dcache_wb_range(pm, va, PAGE_SIZE, 2981 true, (oflags & PVF_WRITE) == 0); 2982 } 2983 #endif 2984 pool_put(&pmap_pv_pool, pv); 2985 } 2986 } 2987 2988 /* 2989 * Make sure userland mappings get the right permissions 2990 */ 2991 if (pm != pmap_kernel() && va != vector_page) 2992 npte |= L2_S_PROT_U; 2993 2994 /* 2995 * Keep the stats up to date 2996 */ 2997 if (opte == 0) { 2998 l2b->l2b_occupancy++; 2999 pm->pm_stats.resident_count++; 3000 } 3001 3002 NPDEBUG(PDB_ENTER, 3003 printf("pmap_enter: opte 0x%08x npte 0x%08x\n", opte, npte)); 3004 3005 /* 3006 * If this is just a wiring change, the two PTEs will be 3007 * identical, so there's no need to update the page table. 3008 */ 3009 if (npte != opte) { 3010 bool is_cached = pmap_is_cached(pm); 3011 3012 *ptep = npte; 3013 if (is_cached) { 3014 /* 3015 * We only need to frob the cache/tlb if this pmap 3016 * is current 3017 */ 3018 PTE_SYNC(ptep); 3019 if (va != vector_page && l2pte_valid(npte)) { 3020 /* 3021 * This mapping is likely to be accessed as 3022 * soon as we return to userland. Fix up the 3023 * L1 entry to avoid taking another 3024 * page/domain fault. 3025 */ 3026 pd_entry_t *pl1pd, l1pd; 3027 3028 pl1pd = &pm->pm_l1->l1_kva[L1_IDX(va)]; 3029 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | 3030 L1_C_PROTO; 3031 if (*pl1pd != l1pd) { 3032 *pl1pd = l1pd; 3033 PTE_SYNC(pl1pd); 3034 } 3035 } 3036 } 3037 3038 if (PV_BEEN_EXECD(oflags)) 3039 pmap_tlb_flushID_SE(pm, va); 3040 else 3041 if (PV_BEEN_REFD(oflags)) 3042 pmap_tlb_flushD_SE(pm, va); 3043 3044 NPDEBUG(PDB_ENTER, 3045 printf("pmap_enter: is_cached %d cs 0x%08x\n", 3046 is_cached, pm->pm_cstate.cs_all)); 3047 3048 if (pg != NULL) { 3049 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3050 3051 simple_lock(&md->pvh_slock); 3052 pmap_vac_me_harder(md, pa, pm, va); 3053 simple_unlock(&md->pvh_slock); 3054 } 3055 } 3056 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3057 if (pg) { 3058 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3059 3060 simple_lock(&md->pvh_slock); 3061 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3062 KASSERT(((md->pvh_attrs & PVF_WRITE) == 0) == (md->urw_mappings + md->krw_mappings == 0)); 3063 simple_unlock(&md->pvh_slock); 3064 } 3065 #endif 3066 3067 pmap_release_pmap_lock(pm); 3068 PMAP_MAP_TO_HEAD_UNLOCK(); 3069 3070 return (0); 3071 } 3072 3073 /* 3074 * pmap_remove() 3075 * 3076 * pmap_remove is responsible for nuking a number of mappings for a range 3077 * of virtual address space in the current pmap. To do this efficiently 3078 * is interesting, because in a number of cases a wide virtual address 3079 * range may be supplied that contains few actual mappings. So, the 3080 * optimisations are: 3081 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3082 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3083 * maybe do just a partial cache clean. This path of execution is 3084 * complicated by the fact that the cache must be flushed _before_ 3085 * the PTE is nuked, being a VAC :-) 3086 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3087 * all invalidations until pmap_update(), since pmap_remove_all() has 3088 * already flushed the cache. 3089 * 4. Maybe later fast-case a single page, but I don't think this is 3090 * going to make _that_ much difference overall. 3091 */ 3092 3093 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3094 3095 void 3096 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3097 { 3098 struct l2_bucket *l2b; 3099 vaddr_t next_bucket; 3100 pt_entry_t *ptep; 3101 u_int cleanlist_idx, total, cnt; 3102 struct { 3103 vaddr_t va; 3104 pt_entry_t *ptep; 3105 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3106 u_int mappings, is_exec, is_refd; 3107 3108 NPDEBUG(PDB_REMOVE, printf("pmap_do_remove: pmap=%p sva=%08lx " 3109 "eva=%08lx\n", pm, sva, eva)); 3110 3111 /* 3112 * we lock in the pmap => pv_head direction 3113 */ 3114 PMAP_MAP_TO_HEAD_LOCK(); 3115 pmap_acquire_pmap_lock(pm); 3116 3117 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3118 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3119 if (pm->pm_cstate.cs_tlb == 0) 3120 pm->pm_remove_all = true; 3121 } else 3122 cleanlist_idx = 0; 3123 3124 total = 0; 3125 3126 while (sva < eva) { 3127 /* 3128 * Do one L2 bucket's worth at a time. 3129 */ 3130 next_bucket = L2_NEXT_BUCKET(sva); 3131 if (next_bucket > eva) 3132 next_bucket = eva; 3133 3134 l2b = pmap_get_l2_bucket(pm, sva); 3135 if (l2b == NULL) { 3136 sva = next_bucket; 3137 continue; 3138 } 3139 3140 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3141 3142 for (mappings = 0; sva < next_bucket; sva += PAGE_SIZE, ptep++){ 3143 struct vm_page *pg; 3144 pt_entry_t pte; 3145 paddr_t pa; 3146 3147 pte = *ptep; 3148 3149 if (pte == 0) { 3150 /* Nothing here, move along */ 3151 continue; 3152 } 3153 3154 pa = l2pte_pa(pte); 3155 is_exec = 0; 3156 is_refd = 1; 3157 3158 /* 3159 * Update flags. In a number of circumstances, 3160 * we could cluster a lot of these and do a 3161 * number of sequential pages in one go. 3162 */ 3163 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3164 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3165 struct pv_entry *pv; 3166 3167 simple_lock(&md->pvh_slock); 3168 pv = pmap_remove_pv(md, pa, pm, sva); 3169 pmap_vac_me_harder(md, pa, pm, 0); 3170 simple_unlock(&md->pvh_slock); 3171 if (pv != NULL) { 3172 if (pm->pm_remove_all == false) { 3173 is_exec = 3174 PV_BEEN_EXECD(pv->pv_flags); 3175 is_refd = 3176 PV_BEEN_REFD(pv->pv_flags); 3177 } 3178 pool_put(&pmap_pv_pool, pv); 3179 } 3180 } 3181 mappings++; 3182 3183 if (!l2pte_valid(pte)) { 3184 /* 3185 * Ref/Mod emulation is still active for this 3186 * mapping, therefore it is has not yet been 3187 * accessed. No need to frob the cache/tlb. 3188 */ 3189 *ptep = 0; 3190 PTE_SYNC_CURRENT(pm, ptep); 3191 continue; 3192 } 3193 3194 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3195 /* Add to the clean list. */ 3196 cleanlist[cleanlist_idx].ptep = ptep; 3197 cleanlist[cleanlist_idx].va = 3198 sva | (is_exec & 1); 3199 cleanlist_idx++; 3200 } else 3201 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3202 /* Nuke everything if needed. */ 3203 #ifdef PMAP_CACHE_VIVT 3204 pmap_idcache_wbinv_all(pm); 3205 #endif 3206 pmap_tlb_flushID(pm); 3207 3208 /* 3209 * Roll back the previous PTE list, 3210 * and zero out the current PTE. 3211 */ 3212 for (cnt = 0; 3213 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3214 *cleanlist[cnt].ptep = 0; 3215 PTE_SYNC(cleanlist[cnt].ptep); 3216 } 3217 *ptep = 0; 3218 PTE_SYNC(ptep); 3219 cleanlist_idx++; 3220 pm->pm_remove_all = true; 3221 } else { 3222 *ptep = 0; 3223 PTE_SYNC(ptep); 3224 if (pm->pm_remove_all == false) { 3225 if (is_exec) 3226 pmap_tlb_flushID_SE(pm, sva); 3227 else 3228 if (is_refd) 3229 pmap_tlb_flushD_SE(pm, sva); 3230 } 3231 } 3232 } 3233 3234 /* 3235 * Deal with any left overs 3236 */ 3237 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3238 total += cleanlist_idx; 3239 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3240 if (pm->pm_cstate.cs_all != 0) { 3241 vaddr_t clva = cleanlist[cnt].va & ~1; 3242 if (cleanlist[cnt].va & 1) { 3243 #ifdef PMAP_CACHE_VIVT 3244 pmap_idcache_wbinv_range(pm, 3245 clva, PAGE_SIZE); 3246 #endif 3247 pmap_tlb_flushID_SE(pm, clva); 3248 } else { 3249 #ifdef PMAP_CACHE_VIVT 3250 pmap_dcache_wb_range(pm, 3251 clva, PAGE_SIZE, true, 3252 false); 3253 #endif 3254 pmap_tlb_flushD_SE(pm, clva); 3255 } 3256 } 3257 *cleanlist[cnt].ptep = 0; 3258 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3259 } 3260 3261 /* 3262 * If it looks like we're removing a whole bunch 3263 * of mappings, it's faster to just write-back 3264 * the whole cache now and defer TLB flushes until 3265 * pmap_update() is called. 3266 */ 3267 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3268 cleanlist_idx = 0; 3269 else { 3270 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3271 #ifdef PMAP_CACHE_VIVT 3272 pmap_idcache_wbinv_all(pm); 3273 #endif 3274 pm->pm_remove_all = true; 3275 } 3276 } 3277 3278 pmap_free_l2_bucket(pm, l2b, mappings); 3279 pm->pm_stats.resident_count -= mappings; 3280 } 3281 3282 pmap_release_pmap_lock(pm); 3283 PMAP_MAP_TO_HEAD_UNLOCK(); 3284 } 3285 3286 #ifdef PMAP_CACHE_VIPT 3287 static struct pv_entry * 3288 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3289 { 3290 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3291 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3292 struct pv_entry *pv; 3293 3294 simple_lock(&md->pvh_slock); 3295 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3296 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3297 3298 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3299 KASSERT(pv); 3300 KASSERT(pv->pv_flags & PVF_KENTRY); 3301 3302 /* 3303 * If we are removing a writeable mapping to a cached exec page, 3304 * if it's the last mapping then clear it execness other sync 3305 * the page to the icache. 3306 */ 3307 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3308 && (pv->pv_flags & PVF_WRITE) != 0) { 3309 if (SLIST_EMPTY(&md->pvh_list)) { 3310 md->pvh_attrs &= ~PVF_EXEC; 3311 PMAPCOUNT(exec_discarded_kremove); 3312 } else { 3313 pmap_syncicache_page(md, pa); 3314 PMAPCOUNT(exec_synced_kremove); 3315 } 3316 } 3317 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3318 simple_unlock(&md->pvh_slock); 3319 3320 return pv; 3321 } 3322 #endif /* PMAP_CACHE_VIPT */ 3323 3324 /* 3325 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3326 * 3327 * We assume there is already sufficient KVM space available 3328 * to do this, as we can't allocate L2 descriptor tables/metadata 3329 * from here. 3330 */ 3331 void 3332 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3333 { 3334 struct l2_bucket *l2b; 3335 pt_entry_t *ptep, opte; 3336 #ifdef PMAP_CACHE_VIVT 3337 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3338 #endif 3339 #ifdef PMAP_CACHE_VIPT 3340 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3341 struct vm_page *opg; 3342 struct pv_entry *pv = NULL; 3343 #endif 3344 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3345 3346 NPDEBUG(PDB_KENTER, 3347 printf("pmap_kenter_pa: va 0x%08lx, pa 0x%08lx, prot 0x%x\n", 3348 va, pa, prot)); 3349 3350 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3351 KDASSERT(l2b != NULL); 3352 3353 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3354 opte = *ptep; 3355 3356 if (opte == 0) { 3357 PMAPCOUNT(kenter_mappings); 3358 l2b->l2b_occupancy++; 3359 } else { 3360 PMAPCOUNT(kenter_remappings); 3361 #ifdef PMAP_CACHE_VIPT 3362 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3363 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3364 if (opg) { 3365 KASSERT(opg != pg); 3366 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3367 KASSERT((flags & PMAP_KMPAGE) == 0); 3368 simple_lock(&omd->pvh_slock); 3369 pv = pmap_kremove_pg(opg, va); 3370 simple_unlock(&omd->pvh_slock); 3371 } 3372 #endif 3373 if (l2pte_valid(opte)) { 3374 #ifdef PMAP_CACHE_VIVT 3375 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3376 #endif 3377 cpu_tlb_flushD_SE(va); 3378 cpu_cpwait(); 3379 } 3380 } 3381 3382 *ptep = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | 3383 pte_l2_s_cache_mode; 3384 PTE_SYNC(ptep); 3385 3386 if (pg) { 3387 if (flags & PMAP_KMPAGE) { 3388 simple_lock(&md->pvh_slock); 3389 KASSERT(md->urw_mappings == 0); 3390 KASSERT(md->uro_mappings == 0); 3391 KASSERT(md->krw_mappings == 0); 3392 KASSERT(md->kro_mappings == 0); 3393 #ifdef PMAP_CACHE_VIPT 3394 KASSERT(pv == NULL); 3395 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3396 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3397 /* if there is a color conflict, evict from cache. */ 3398 if (pmap_is_page_colored_p(md) 3399 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3400 PMAPCOUNT(vac_color_change); 3401 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3402 } else if (md->pvh_attrs & PVF_MULTCLR) { 3403 /* 3404 * If this page has multiple colors, expunge 3405 * them. 3406 */ 3407 PMAPCOUNT(vac_flush_lots2); 3408 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3409 } 3410 md->pvh_attrs &= PAGE_SIZE - 1; 3411 md->pvh_attrs |= PVF_KMPAGE 3412 | PVF_COLORED | PVF_DIRTY 3413 | (va & arm_cache_prefer_mask); 3414 #endif 3415 #ifdef PMAP_CACHE_VIVT 3416 md->pvh_attrs |= PVF_KMPAGE; 3417 #endif 3418 pmap_kmpages++; 3419 simple_unlock(&md->pvh_slock); 3420 #ifdef PMAP_CACHE_VIPT 3421 } else { 3422 if (pv == NULL) { 3423 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3424 KASSERT(pv != NULL); 3425 } 3426 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3427 PVF_WIRED | PVF_KENTRY 3428 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3429 if ((prot & VM_PROT_WRITE) 3430 && !(md->pvh_attrs & PVF_NC)) 3431 md->pvh_attrs |= PVF_DIRTY; 3432 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3433 simple_lock(&md->pvh_slock); 3434 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3435 simple_unlock(&md->pvh_slock); 3436 #endif 3437 } 3438 #ifdef PMAP_CACHE_VIPT 3439 } else { 3440 if (pv != NULL) 3441 pool_put(&pmap_pv_pool, pv); 3442 #endif 3443 } 3444 } 3445 3446 void 3447 pmap_kremove(vaddr_t va, vsize_t len) 3448 { 3449 struct l2_bucket *l2b; 3450 pt_entry_t *ptep, *sptep, opte; 3451 vaddr_t next_bucket, eva; 3452 u_int mappings; 3453 struct vm_page *opg; 3454 3455 PMAPCOUNT(kenter_unmappings); 3456 3457 NPDEBUG(PDB_KREMOVE, printf("pmap_kremove: va 0x%08lx, len 0x%08lx\n", 3458 va, len)); 3459 3460 eva = va + len; 3461 3462 while (va < eva) { 3463 next_bucket = L2_NEXT_BUCKET(va); 3464 if (next_bucket > eva) 3465 next_bucket = eva; 3466 3467 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3468 KDASSERT(l2b != NULL); 3469 3470 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 3471 mappings = 0; 3472 3473 while (va < next_bucket) { 3474 opte = *ptep; 3475 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3476 if (opg) { 3477 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3478 3479 if (omd->pvh_attrs & PVF_KMPAGE) { 3480 simple_lock(&omd->pvh_slock); 3481 KASSERT(omd->urw_mappings == 0); 3482 KASSERT(omd->uro_mappings == 0); 3483 KASSERT(omd->krw_mappings == 0); 3484 KASSERT(omd->kro_mappings == 0); 3485 omd->pvh_attrs &= ~PVF_KMPAGE; 3486 #ifdef PMAP_CACHE_VIPT 3487 omd->pvh_attrs &= ~PVF_WRITE; 3488 #endif 3489 pmap_kmpages--; 3490 simple_unlock(&omd->pvh_slock); 3491 #ifdef PMAP_CACHE_VIPT 3492 } else { 3493 pool_put(&pmap_pv_pool, 3494 pmap_kremove_pg(opg, va)); 3495 #endif 3496 } 3497 } 3498 if (l2pte_valid(opte)) { 3499 #ifdef PMAP_CACHE_VIVT 3500 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3501 #endif 3502 cpu_tlb_flushD_SE(va); 3503 } 3504 if (opte) { 3505 *ptep = 0; 3506 mappings++; 3507 } 3508 va += PAGE_SIZE; 3509 ptep++; 3510 } 3511 KDASSERT(mappings <= l2b->l2b_occupancy); 3512 l2b->l2b_occupancy -= mappings; 3513 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3514 } 3515 cpu_cpwait(); 3516 } 3517 3518 bool 3519 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3520 { 3521 struct l2_dtable *l2; 3522 pd_entry_t *pl1pd, l1pd; 3523 pt_entry_t *ptep, pte; 3524 paddr_t pa; 3525 u_int l1idx; 3526 3527 pmap_acquire_pmap_lock(pm); 3528 3529 l1idx = L1_IDX(va); 3530 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3531 l1pd = *pl1pd; 3532 3533 if (l1pte_section_p(l1pd)) { 3534 /* 3535 * These should only happen for pmap_kernel() 3536 */ 3537 KDASSERT(pm == pmap_kernel()); 3538 pmap_release_pmap_lock(pm); 3539 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3540 } else { 3541 /* 3542 * Note that we can't rely on the validity of the L1 3543 * descriptor as an indication that a mapping exists. 3544 * We have to look it up in the L2 dtable. 3545 */ 3546 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3547 3548 if (l2 == NULL || 3549 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3550 pmap_release_pmap_lock(pm); 3551 return false; 3552 } 3553 3554 ptep = &ptep[l2pte_index(va)]; 3555 pte = *ptep; 3556 pmap_release_pmap_lock(pm); 3557 3558 if (pte == 0) 3559 return false; 3560 3561 switch (pte & L2_TYPE_MASK) { 3562 case L2_TYPE_L: 3563 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3564 break; 3565 3566 default: 3567 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3568 break; 3569 } 3570 } 3571 3572 if (pap != NULL) 3573 *pap = pa; 3574 3575 return true; 3576 } 3577 3578 void 3579 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3580 { 3581 struct l2_bucket *l2b; 3582 pt_entry_t *ptep, pte; 3583 vaddr_t next_bucket; 3584 u_int flags; 3585 u_int clr_mask; 3586 int flush; 3587 3588 NPDEBUG(PDB_PROTECT, 3589 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3590 pm, sva, eva, prot)); 3591 3592 if ((prot & VM_PROT_READ) == 0) { 3593 pmap_remove(pm, sva, eva); 3594 return; 3595 } 3596 3597 if (prot & VM_PROT_WRITE) { 3598 /* 3599 * If this is a read->write transition, just ignore it and let 3600 * uvm_fault() take care of it later. 3601 */ 3602 return; 3603 } 3604 3605 PMAP_MAP_TO_HEAD_LOCK(); 3606 pmap_acquire_pmap_lock(pm); 3607 3608 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3609 flags = 0; 3610 clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3611 3612 while (sva < eva) { 3613 next_bucket = L2_NEXT_BUCKET(sva); 3614 if (next_bucket > eva) 3615 next_bucket = eva; 3616 3617 l2b = pmap_get_l2_bucket(pm, sva); 3618 if (l2b == NULL) { 3619 sva = next_bucket; 3620 continue; 3621 } 3622 3623 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3624 3625 while (sva < next_bucket) { 3626 pte = *ptep; 3627 if (l2pte_valid(pte) != 0 && l2pte_writable_p(pte)) { 3628 struct vm_page *pg; 3629 u_int f; 3630 3631 #ifdef PMAP_CACHE_VIVT 3632 /* 3633 * OK, at this point, we know we're doing 3634 * write-protect operation. If the pmap is 3635 * active, write-back the page. 3636 */ 3637 pmap_dcache_wb_range(pm, sva, PAGE_SIZE, 3638 false, false); 3639 #endif 3640 3641 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3642 pte = l2pte_set_readonly(pte); 3643 *ptep = pte; 3644 PTE_SYNC(ptep); 3645 3646 if (pg != NULL) { 3647 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3648 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3649 3650 simple_lock(&md->pvh_slock); 3651 f = pmap_modify_pv(md, pa, pm, sva, 3652 clr_mask, 0); 3653 pmap_vac_me_harder(md, pa, pm, sva); 3654 simple_unlock(&md->pvh_slock); 3655 } else 3656 f = PVF_REF | PVF_EXEC; 3657 3658 if (flush >= 0) { 3659 flush++; 3660 flags |= f; 3661 } else 3662 if (PV_BEEN_EXECD(f)) 3663 pmap_tlb_flushID_SE(pm, sva); 3664 else 3665 if (PV_BEEN_REFD(f)) 3666 pmap_tlb_flushD_SE(pm, sva); 3667 } 3668 3669 sva += PAGE_SIZE; 3670 ptep++; 3671 } 3672 } 3673 3674 pmap_release_pmap_lock(pm); 3675 PMAP_MAP_TO_HEAD_UNLOCK(); 3676 3677 if (flush) { 3678 if (PV_BEEN_EXECD(flags)) 3679 pmap_tlb_flushID(pm); 3680 else 3681 if (PV_BEEN_REFD(flags)) 3682 pmap_tlb_flushD(pm); 3683 } 3684 } 3685 3686 void 3687 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 3688 { 3689 struct l2_bucket *l2b; 3690 pt_entry_t *ptep; 3691 vaddr_t next_bucket; 3692 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 3693 3694 NPDEBUG(PDB_EXEC, 3695 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 3696 pm, sva, eva)); 3697 3698 PMAP_MAP_TO_HEAD_LOCK(); 3699 pmap_acquire_pmap_lock(pm); 3700 3701 while (sva < eva) { 3702 next_bucket = L2_NEXT_BUCKET(sva); 3703 if (next_bucket > eva) 3704 next_bucket = eva; 3705 3706 l2b = pmap_get_l2_bucket(pm, sva); 3707 if (l2b == NULL) { 3708 sva = next_bucket; 3709 continue; 3710 } 3711 3712 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3713 sva < next_bucket; 3714 sva += page_size, ptep++, page_size = PAGE_SIZE) { 3715 if (l2pte_valid(*ptep)) { 3716 cpu_icache_sync_range(sva, 3717 min(page_size, eva - sva)); 3718 } 3719 } 3720 } 3721 3722 pmap_release_pmap_lock(pm); 3723 PMAP_MAP_TO_HEAD_UNLOCK(); 3724 } 3725 3726 void 3727 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 3728 { 3729 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3730 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3731 3732 NPDEBUG(PDB_PROTECT, 3733 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 3734 md, pa, prot)); 3735 3736 switch(prot) { 3737 case VM_PROT_READ|VM_PROT_WRITE: 3738 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3739 pmap_clearbit(md, pa, PVF_EXEC); 3740 break; 3741 #endif 3742 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 3743 break; 3744 3745 case VM_PROT_READ: 3746 #if defined(PMAP_CHECK_VIPT) && defined(PMAP_APX) 3747 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 3748 break; 3749 #endif 3750 case VM_PROT_READ|VM_PROT_EXECUTE: 3751 pmap_clearbit(md, pa, PVF_WRITE); 3752 break; 3753 3754 default: 3755 pmap_page_remove(md, pa); 3756 break; 3757 } 3758 } 3759 3760 /* 3761 * pmap_clear_modify: 3762 * 3763 * Clear the "modified" attribute for a page. 3764 */ 3765 bool 3766 pmap_clear_modify(struct vm_page *pg) 3767 { 3768 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3769 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3770 bool rv; 3771 3772 if (md->pvh_attrs & PVF_MOD) { 3773 rv = true; 3774 #ifdef PMAP_CACHE_VIPT 3775 /* 3776 * If we are going to clear the modified bit and there are 3777 * no other modified bits set, flush the page to memory and 3778 * mark it clean. 3779 */ 3780 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 3781 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 3782 #endif 3783 pmap_clearbit(md, pa, PVF_MOD); 3784 } else 3785 rv = false; 3786 3787 return (rv); 3788 } 3789 3790 /* 3791 * pmap_clear_reference: 3792 * 3793 * Clear the "referenced" attribute for a page. 3794 */ 3795 bool 3796 pmap_clear_reference(struct vm_page *pg) 3797 { 3798 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3799 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3800 bool rv; 3801 3802 if (md->pvh_attrs & PVF_REF) { 3803 rv = true; 3804 pmap_clearbit(md, pa, PVF_REF); 3805 } else 3806 rv = false; 3807 3808 return (rv); 3809 } 3810 3811 /* 3812 * pmap_is_modified: 3813 * 3814 * Test if a page has the "modified" attribute. 3815 */ 3816 /* See <arm/arm32/pmap.h> */ 3817 3818 /* 3819 * pmap_is_referenced: 3820 * 3821 * Test if a page has the "referenced" attribute. 3822 */ 3823 /* See <arm/arm32/pmap.h> */ 3824 3825 int 3826 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 3827 { 3828 struct l2_dtable *l2; 3829 struct l2_bucket *l2b; 3830 pd_entry_t *pl1pd, l1pd; 3831 pt_entry_t *ptep, pte; 3832 paddr_t pa; 3833 u_int l1idx; 3834 int rv = 0; 3835 3836 PMAP_MAP_TO_HEAD_LOCK(); 3837 pmap_acquire_pmap_lock(pm); 3838 3839 l1idx = L1_IDX(va); 3840 3841 /* 3842 * If there is no l2_dtable for this address, then the process 3843 * has no business accessing it. 3844 * 3845 * Note: This will catch userland processes trying to access 3846 * kernel addresses. 3847 */ 3848 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3849 if (l2 == NULL) 3850 goto out; 3851 3852 /* 3853 * Likewise if there is no L2 descriptor table 3854 */ 3855 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 3856 if (l2b->l2b_kva == NULL) 3857 goto out; 3858 3859 /* 3860 * Check the PTE itself. 3861 */ 3862 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3863 pte = *ptep; 3864 if (pte == 0) 3865 goto out; 3866 3867 /* 3868 * Catch a userland access to the vector page mapped at 0x0 3869 */ 3870 if (user && (pte & L2_S_PROT_U) == 0) 3871 goto out; 3872 3873 pa = l2pte_pa(pte); 3874 3875 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(pte)) { 3876 /* 3877 * This looks like a good candidate for "page modified" 3878 * emulation... 3879 */ 3880 struct pv_entry *pv; 3881 struct vm_page *pg; 3882 3883 /* Extract the physical address of the page */ 3884 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3885 goto out; 3886 3887 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3888 3889 /* Get the current flags for this page. */ 3890 simple_lock(&md->pvh_slock); 3891 3892 pv = pmap_find_pv(md, pm, va); 3893 if (pv == NULL) { 3894 simple_unlock(&md->pvh_slock); 3895 goto out; 3896 } 3897 3898 /* 3899 * Do the flags say this page is writable? If not then it 3900 * is a genuine write fault. If yes then the write fault is 3901 * our fault as we did not reflect the write access in the 3902 * PTE. Now we know a write has occurred we can correct this 3903 * and also set the modified bit 3904 */ 3905 if ((pv->pv_flags & PVF_WRITE) == 0) { 3906 simple_unlock(&md->pvh_slock); 3907 goto out; 3908 } 3909 3910 NPDEBUG(PDB_FOLLOW, 3911 printf("pmap_fault_fixup: mod emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3912 pm, va, pa)); 3913 3914 md->pvh_attrs |= PVF_REF | PVF_MOD; 3915 pv->pv_flags |= PVF_REF | PVF_MOD; 3916 #ifdef PMAP_CACHE_VIPT 3917 /* 3918 * If there are cacheable mappings for this page, mark it dirty. 3919 */ 3920 if ((md->pvh_attrs & PVF_NC) == 0) 3921 md->pvh_attrs |= PVF_DIRTY; 3922 #endif 3923 simple_unlock(&md->pvh_slock); 3924 3925 /* 3926 * Re-enable write permissions for the page. No need to call 3927 * pmap_vac_me_harder(), since this is just a 3928 * modified-emulation fault, and the PVF_WRITE bit isn't 3929 * changing. We've already set the cacheable bits based on 3930 * the assumption that we can write to this page. 3931 */ 3932 *ptep = l2pte_set_writable((pte & ~L2_TYPE_MASK) | L2_S_PROTO); 3933 PTE_SYNC(ptep); 3934 rv = 1; 3935 } else 3936 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 3937 /* 3938 * This looks like a good candidate for "page referenced" 3939 * emulation. 3940 */ 3941 struct pv_entry *pv; 3942 struct vm_page *pg; 3943 3944 /* Extract the physical address of the page */ 3945 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 3946 goto out; 3947 3948 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3949 3950 /* Get the current flags for this page. */ 3951 simple_lock(&md->pvh_slock); 3952 3953 pv = pmap_find_pv(md, pm, va); 3954 if (pv == NULL) { 3955 simple_unlock(&md->pvh_slock); 3956 goto out; 3957 } 3958 3959 md->pvh_attrs |= PVF_REF; 3960 pv->pv_flags |= PVF_REF; 3961 simple_unlock(&md->pvh_slock); 3962 3963 NPDEBUG(PDB_FOLLOW, 3964 printf("pmap_fault_fixup: ref emul. pm %p, va 0x%08lx, pa 0x%08lx\n", 3965 pm, va, pa)); 3966 3967 *ptep = l2pte_set_readonly((pte & ~L2_TYPE_MASK) | L2_S_PROTO); 3968 PTE_SYNC(ptep); 3969 rv = 1; 3970 } 3971 3972 /* 3973 * We know there is a valid mapping here, so simply 3974 * fix up the L1 if necessary. 3975 */ 3976 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3977 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 3978 if (*pl1pd != l1pd) { 3979 *pl1pd = l1pd; 3980 PTE_SYNC(pl1pd); 3981 rv = 1; 3982 } 3983 3984 #ifdef CPU_SA110 3985 /* 3986 * There are bugs in the rev K SA110. This is a check for one 3987 * of them. 3988 */ 3989 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 3990 curcpu()->ci_arm_cpurev < 3) { 3991 /* Always current pmap */ 3992 if (l2pte_valid(pte)) { 3993 extern int kernel_debug; 3994 if (kernel_debug & 1) { 3995 struct proc *p = curlwp->l_proc; 3996 printf("prefetch_abort: page is already " 3997 "mapped - pte=%p *pte=%08x\n", ptep, pte); 3998 printf("prefetch_abort: pc=%08lx proc=%p " 3999 "process=%s\n", va, p, p->p_comm); 4000 printf("prefetch_abort: far=%08x fs=%x\n", 4001 cpu_faultaddress(), cpu_faultstatus()); 4002 } 4003 #ifdef DDB 4004 if (kernel_debug & 2) 4005 Debugger(); 4006 #endif 4007 rv = 1; 4008 } 4009 } 4010 #endif /* CPU_SA110 */ 4011 4012 #ifdef DEBUG 4013 /* 4014 * If 'rv == 0' at this point, it generally indicates that there is a 4015 * stale TLB entry for the faulting address. This happens when two or 4016 * more processes are sharing an L1. Since we don't flush the TLB on 4017 * a context switch between such processes, we can take domain faults 4018 * for mappings which exist at the same VA in both processes. EVEN IF 4019 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4020 * example. 4021 * 4022 * This is extremely likely to happen if pmap_enter() updated the L1 4023 * entry for a recently entered mapping. In this case, the TLB is 4024 * flushed for the new mapping, but there may still be TLB entries for 4025 * other mappings belonging to other processes in the 1MB range 4026 * covered by the L1 entry. 4027 * 4028 * Since 'rv == 0', we know that the L1 already contains the correct 4029 * value, so the fault must be due to a stale TLB entry. 4030 * 4031 * Since we always need to flush the TLB anyway in the case where we 4032 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4033 * stale TLB entries dynamically. 4034 * 4035 * However, the above condition can ONLY happen if the current L1 is 4036 * being shared. If it happens when the L1 is unshared, it indicates 4037 * that other parts of the pmap are not doing their job WRT managing 4038 * the TLB. 4039 */ 4040 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 4041 extern int last_fault_code; 4042 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4043 pm, va, ftype); 4044 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 4045 l2, l2b, ptep, pl1pd); 4046 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 4047 pte, l1pd, last_fault_code); 4048 #ifdef DDB 4049 Debugger(); 4050 #endif 4051 } 4052 #endif 4053 4054 cpu_tlb_flushID_SE(va); 4055 cpu_cpwait(); 4056 4057 rv = 1; 4058 4059 out: 4060 pmap_release_pmap_lock(pm); 4061 PMAP_MAP_TO_HEAD_UNLOCK(); 4062 4063 return (rv); 4064 } 4065 4066 /* 4067 * Routine: pmap_procwr 4068 * 4069 * Function: 4070 * Synchronize caches corresponding to [addr, addr+len) in p. 4071 * 4072 */ 4073 void 4074 pmap_procwr(struct proc *p, vaddr_t va, int len) 4075 { 4076 /* We only need to do anything if it is the current process. */ 4077 if (p == curproc) 4078 cpu_icache_sync_range(va, len); 4079 } 4080 4081 /* 4082 * Routine: pmap_unwire 4083 * Function: Clear the wired attribute for a map/virtual-address pair. 4084 * 4085 * In/out conditions: 4086 * The mapping must already exist in the pmap. 4087 */ 4088 void 4089 pmap_unwire(pmap_t pm, vaddr_t va) 4090 { 4091 struct l2_bucket *l2b; 4092 pt_entry_t *ptep, pte; 4093 struct vm_page *pg; 4094 paddr_t pa; 4095 4096 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4097 4098 PMAP_MAP_TO_HEAD_LOCK(); 4099 pmap_acquire_pmap_lock(pm); 4100 4101 l2b = pmap_get_l2_bucket(pm, va); 4102 KDASSERT(l2b != NULL); 4103 4104 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4105 pte = *ptep; 4106 4107 /* Extract the physical address of the page */ 4108 pa = l2pte_pa(pte); 4109 4110 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4111 /* Update the wired bit in the pv entry for this page. */ 4112 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4113 4114 simple_lock(&md->pvh_slock); 4115 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4116 simple_unlock(&md->pvh_slock); 4117 } 4118 4119 pmap_release_pmap_lock(pm); 4120 PMAP_MAP_TO_HEAD_UNLOCK(); 4121 } 4122 4123 void 4124 pmap_activate(struct lwp *l) 4125 { 4126 extern int block_userspace_access; 4127 pmap_t opm, npm, rpm; 4128 uint32_t odacr, ndacr; 4129 int oldirqstate; 4130 4131 /* 4132 * If activating a non-current lwp or the current lwp is 4133 * already active, just return. 4134 */ 4135 if (l != curlwp || 4136 l->l_proc->p_vmspace->vm_map.pmap->pm_activated == true) 4137 return; 4138 4139 npm = l->l_proc->p_vmspace->vm_map.pmap; 4140 ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4141 (DOMAIN_CLIENT << (npm->pm_domain * 2)); 4142 4143 /* 4144 * If TTB and DACR are unchanged, short-circuit all the 4145 * TLB/cache management stuff. 4146 */ 4147 if (pmap_previous_active_lwp != NULL) { 4148 opm = pmap_previous_active_lwp->l_proc->p_vmspace->vm_map.pmap; 4149 odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 4150 (DOMAIN_CLIENT << (opm->pm_domain * 2)); 4151 4152 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4153 goto all_done; 4154 } else 4155 opm = NULL; 4156 4157 PMAPCOUNT(activations); 4158 block_userspace_access = 1; 4159 4160 /* 4161 * If switching to a user vmspace which is different to the 4162 * most recent one, and the most recent one is potentially 4163 * live in the cache, we must write-back and invalidate the 4164 * entire cache. 4165 */ 4166 rpm = pmap_recent_user; 4167 4168 /* 4169 * XXXSCW: There's a corner case here which can leave turds in the cache as 4170 * reported in kern/41058. They're probably left over during tear-down and 4171 * switching away from an exiting process. Until the root cause is identified 4172 * and fixed, zap the cache when switching pmaps. This will result in a few 4173 * unnecessary cache flushes, but that's better than silently corrupting data. 4174 */ 4175 #if 0 4176 if (npm != pmap_kernel() && rpm && npm != rpm && 4177 rpm->pm_cstate.cs_cache) { 4178 rpm->pm_cstate.cs_cache = 0; 4179 #ifdef PMAP_CACHE_VIVT 4180 cpu_idcache_wbinv_all(); 4181 #endif 4182 } 4183 #else 4184 if (rpm) { 4185 rpm->pm_cstate.cs_cache = 0; 4186 if (npm == pmap_kernel()) 4187 pmap_recent_user = NULL; 4188 #ifdef PMAP_CACHE_VIVT 4189 cpu_idcache_wbinv_all(); 4190 #endif 4191 } 4192 #endif 4193 4194 /* No interrupts while we frob the TTB/DACR */ 4195 oldirqstate = disable_interrupts(IF32_bits); 4196 4197 /* 4198 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4199 * entry corresponding to 'vector_page' in the incoming L1 table 4200 * before switching to it otherwise subsequent interrupts/exceptions 4201 * (including domain faults!) will jump into hyperspace. 4202 */ 4203 if (npm->pm_pl1vec != NULL) { 4204 cpu_tlb_flushID_SE((u_int)vector_page); 4205 cpu_cpwait(); 4206 *npm->pm_pl1vec = npm->pm_l1vec; 4207 PTE_SYNC(npm->pm_pl1vec); 4208 } 4209 4210 cpu_domains(ndacr); 4211 4212 if (npm == pmap_kernel() || npm == rpm) { 4213 /* 4214 * Switching to a kernel thread, or back to the 4215 * same user vmspace as before... Simply update 4216 * the TTB (no TLB flush required) 4217 */ 4218 __asm volatile("mcr p15, 0, %0, c2, c0, 0" :: 4219 "r"(npm->pm_l1->l1_physaddr)); 4220 cpu_cpwait(); 4221 } else { 4222 /* 4223 * Otherwise, update TTB and flush TLB 4224 */ 4225 cpu_context_switch(npm->pm_l1->l1_physaddr); 4226 if (rpm != NULL) 4227 rpm->pm_cstate.cs_tlb = 0; 4228 } 4229 4230 restore_interrupts(oldirqstate); 4231 4232 block_userspace_access = 0; 4233 4234 all_done: 4235 /* 4236 * The new pmap is resident. Make sure it's marked 4237 * as resident in the cache/TLB. 4238 */ 4239 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4240 if (npm != pmap_kernel()) 4241 pmap_recent_user = npm; 4242 4243 /* The old pmap is not longer active */ 4244 if (opm != NULL) 4245 opm->pm_activated = false; 4246 4247 /* But the new one is */ 4248 npm->pm_activated = true; 4249 } 4250 4251 void 4252 pmap_deactivate(struct lwp *l) 4253 { 4254 4255 /* 4256 * If the process is exiting, make sure pmap_activate() does 4257 * a full MMU context-switch and cache flush, which we might 4258 * otherwise skip. See PR port-arm/38950. 4259 */ 4260 if (l->l_proc->p_sflag & PS_WEXIT) 4261 pmap_previous_active_lwp = NULL; 4262 4263 l->l_proc->p_vmspace->vm_map.pmap->pm_activated = false; 4264 } 4265 4266 void 4267 pmap_update(pmap_t pm) 4268 { 4269 4270 if (pm->pm_remove_all) { 4271 /* 4272 * Finish up the pmap_remove_all() optimisation by flushing 4273 * the TLB. 4274 */ 4275 pmap_tlb_flushID(pm); 4276 pm->pm_remove_all = false; 4277 } 4278 4279 if (pmap_is_current(pm)) { 4280 /* 4281 * If we're dealing with a current userland pmap, move its L1 4282 * to the end of the LRU. 4283 */ 4284 if (pm != pmap_kernel()) 4285 pmap_use_l1(pm); 4286 4287 /* 4288 * We can assume we're done with frobbing the cache/tlb for 4289 * now. Make sure any future pmap ops don't skip cache/tlb 4290 * flushes. 4291 */ 4292 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4293 } 4294 4295 PMAPCOUNT(updates); 4296 4297 /* 4298 * make sure TLB/cache operations have completed. 4299 */ 4300 cpu_cpwait(); 4301 } 4302 4303 void 4304 pmap_remove_all(pmap_t pm) 4305 { 4306 4307 /* 4308 * The vmspace described by this pmap is about to be torn down. 4309 * Until pmap_update() is called, UVM will only make calls 4310 * to pmap_remove(). We can make life much simpler by flushing 4311 * the cache now, and deferring TLB invalidation to pmap_update(). 4312 */ 4313 #ifdef PMAP_CACHE_VIVT 4314 pmap_idcache_wbinv_all(pm); 4315 #endif 4316 pm->pm_remove_all = true; 4317 } 4318 4319 /* 4320 * Retire the given physical map from service. 4321 * Should only be called if the map contains no valid mappings. 4322 */ 4323 void 4324 pmap_destroy(pmap_t pm) 4325 { 4326 u_int count; 4327 4328 if (pm == NULL) 4329 return; 4330 4331 if (pm->pm_remove_all) { 4332 pmap_tlb_flushID(pm); 4333 pm->pm_remove_all = false; 4334 } 4335 4336 /* 4337 * Drop reference count 4338 */ 4339 mutex_enter(&pm->pm_lock); 4340 count = --pm->pm_obj.uo_refs; 4341 mutex_exit(&pm->pm_lock); 4342 if (count > 0) { 4343 if (pmap_is_current(pm)) { 4344 if (pm != pmap_kernel()) 4345 pmap_use_l1(pm); 4346 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4347 } 4348 return; 4349 } 4350 4351 /* 4352 * reference count is zero, free pmap resources and then free pmap. 4353 */ 4354 4355 if (vector_page < KERNEL_BASE) { 4356 KDASSERT(!pmap_is_current(pm)); 4357 4358 /* Remove the vector page mapping */ 4359 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 4360 pmap_update(pm); 4361 } 4362 4363 LIST_REMOVE(pm, pm_list); 4364 4365 pmap_free_l1(pm); 4366 4367 if (pmap_recent_user == pm) 4368 pmap_recent_user = NULL; 4369 4370 UVM_OBJ_DESTROY(&pm->pm_obj); 4371 4372 /* return the pmap to the pool */ 4373 pool_cache_put(&pmap_cache, pm); 4374 } 4375 4376 4377 /* 4378 * void pmap_reference(pmap_t pm) 4379 * 4380 * Add a reference to the specified pmap. 4381 */ 4382 void 4383 pmap_reference(pmap_t pm) 4384 { 4385 4386 if (pm == NULL) 4387 return; 4388 4389 pmap_use_l1(pm); 4390 4391 mutex_enter(&pm->pm_lock); 4392 pm->pm_obj.uo_refs++; 4393 mutex_exit(&pm->pm_lock); 4394 } 4395 4396 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 4397 4398 static struct evcnt pmap_prefer_nochange_ev = 4399 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 4400 static struct evcnt pmap_prefer_change_ev = 4401 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 4402 4403 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 4404 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 4405 4406 void 4407 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 4408 { 4409 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 4410 vaddr_t va = *vap; 4411 vaddr_t diff = (hint - va) & mask; 4412 if (diff == 0) { 4413 pmap_prefer_nochange_ev.ev_count++; 4414 } else { 4415 pmap_prefer_change_ev.ev_count++; 4416 if (__predict_false(td)) 4417 va -= mask + 1; 4418 *vap = va + diff; 4419 } 4420 } 4421 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 4422 4423 /* 4424 * pmap_zero_page() 4425 * 4426 * Zero a given physical page by mapping it at a page hook point. 4427 * In doing the zero page op, the page we zero is mapped cachable, as with 4428 * StrongARM accesses to non-cached pages are non-burst making writing 4429 * _any_ bulk data very slow. 4430 */ 4431 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 4432 void 4433 pmap_zero_page_generic(paddr_t phys) 4434 { 4435 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4436 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4437 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4438 #endif 4439 #ifdef PMAP_CACHE_VIPT 4440 /* Choose the last page color it had, if any */ 4441 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4442 #else 4443 const vsize_t va_offset = 0; 4444 #endif 4445 pt_entry_t * const ptep = &cdst_pte[va_offset >> PGSHIFT]; 4446 4447 #ifdef DEBUG 4448 if (!SLIST_EMPTY(&md->pvh_list)) 4449 panic("pmap_zero_page: page has mappings"); 4450 #endif 4451 4452 KDASSERT((phys & PGOFSET) == 0); 4453 4454 /* 4455 * Hook in the page, zero it, and purge the cache for that 4456 * zeroed page. Invalidate the TLB as needed. 4457 */ 4458 *ptep = L2_S_PROTO | phys | 4459 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4460 PTE_SYNC(ptep); 4461 cpu_tlb_flushD_SE(cdstp + va_offset); 4462 cpu_cpwait(); 4463 bzero_page(cdstp + va_offset); 4464 /* 4465 * Unmap the page. 4466 */ 4467 *ptep = 0; 4468 PTE_SYNC(ptep); 4469 cpu_tlb_flushD_SE(cdstp + va_offset); 4470 #ifdef PMAP_CACHE_VIVT 4471 cpu_dcache_wbinv_range(cdstp + va_offset, PAGE_SIZE); 4472 #endif 4473 #ifdef PMAP_CACHE_VIPT 4474 /* 4475 * This page is now cache resident so it now has a page color. 4476 * Any contents have been obliterated so clear the EXEC flag. 4477 */ 4478 if (!pmap_is_page_colored_p(md)) { 4479 PMAPCOUNT(vac_color_new); 4480 md->pvh_attrs |= PVF_COLORED; 4481 } 4482 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4483 md->pvh_attrs &= ~PVF_EXEC; 4484 PMAPCOUNT(exec_discarded_zero); 4485 } 4486 md->pvh_attrs |= PVF_DIRTY; 4487 #endif 4488 } 4489 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4490 4491 #if ARM_MMU_XSCALE == 1 4492 void 4493 pmap_zero_page_xscale(paddr_t phys) 4494 { 4495 #ifdef DEBUG 4496 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4497 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4498 4499 if (!SLIST_EMPTY(&md->pvh_list)) 4500 panic("pmap_zero_page: page has mappings"); 4501 #endif 4502 4503 KDASSERT((phys & PGOFSET) == 0); 4504 4505 /* 4506 * Hook in the page, zero it, and purge the cache for that 4507 * zeroed page. Invalidate the TLB as needed. 4508 */ 4509 *cdst_pte = L2_S_PROTO | phys | 4510 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4511 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4512 PTE_SYNC(cdst_pte); 4513 cpu_tlb_flushD_SE(cdstp); 4514 cpu_cpwait(); 4515 bzero_page(cdstp); 4516 xscale_cache_clean_minidata(); 4517 } 4518 #endif /* ARM_MMU_XSCALE == 1 */ 4519 4520 /* pmap_pageidlezero() 4521 * 4522 * The same as above, except that we assume that the page is not 4523 * mapped. This means we never have to flush the cache first. Called 4524 * from the idle loop. 4525 */ 4526 bool 4527 pmap_pageidlezero(paddr_t phys) 4528 { 4529 unsigned int i; 4530 int *ptr; 4531 bool rv = true; 4532 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4533 struct vm_page * const pg = PHYS_TO_VM_PAGE(phys); 4534 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4535 #endif 4536 #ifdef PMAP_CACHE_VIPT 4537 /* Choose the last page color it had, if any */ 4538 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 4539 #else 4540 const vsize_t va_offset = 0; 4541 #endif 4542 pt_entry_t * const ptep = &csrc_pte[va_offset >> PGSHIFT]; 4543 4544 4545 #ifdef DEBUG 4546 if (!SLIST_EMPTY(&md->pvh_list)) 4547 panic("pmap_pageidlezero: page has mappings"); 4548 #endif 4549 4550 KDASSERT((phys & PGOFSET) == 0); 4551 4552 /* 4553 * Hook in the page, zero it, and purge the cache for that 4554 * zeroed page. Invalidate the TLB as needed. 4555 */ 4556 *ptep = L2_S_PROTO | phys | 4557 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4558 PTE_SYNC(ptep); 4559 cpu_tlb_flushD_SE(cdstp + va_offset); 4560 cpu_cpwait(); 4561 4562 for (i = 0, ptr = (int *)(cdstp + va_offset); 4563 i < (PAGE_SIZE / sizeof(int)); i++) { 4564 if (sched_curcpu_runnable_p() != 0) { 4565 /* 4566 * A process has become ready. Abort now, 4567 * so we don't keep it waiting while we 4568 * do slow memory access to finish this 4569 * page. 4570 */ 4571 rv = false; 4572 break; 4573 } 4574 *ptr++ = 0; 4575 } 4576 4577 #ifdef PMAP_CACHE_VIVT 4578 if (rv) 4579 /* 4580 * if we aborted we'll rezero this page again later so don't 4581 * purge it unless we finished it 4582 */ 4583 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4584 #elif defined(PMAP_CACHE_VIPT) 4585 /* 4586 * This page is now cache resident so it now has a page color. 4587 * Any contents have been obliterated so clear the EXEC flag. 4588 */ 4589 if (!pmap_is_page_colored_p(md)) { 4590 PMAPCOUNT(vac_color_new); 4591 md->pvh_attrs |= PVF_COLORED; 4592 } 4593 if (PV_IS_EXEC_P(md->pvh_attrs)) { 4594 md->pvh_attrs &= ~PVF_EXEC; 4595 PMAPCOUNT(exec_discarded_zero); 4596 } 4597 #endif 4598 /* 4599 * Unmap the page. 4600 */ 4601 *ptep = 0; 4602 PTE_SYNC(ptep); 4603 cpu_tlb_flushD_SE(cdstp + va_offset); 4604 4605 return (rv); 4606 } 4607 4608 /* 4609 * pmap_copy_page() 4610 * 4611 * Copy one physical page into another, by mapping the pages into 4612 * hook points. The same comment regarding cachability as in 4613 * pmap_zero_page also applies here. 4614 */ 4615 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 4616 void 4617 pmap_copy_page_generic(paddr_t src, paddr_t dst) 4618 { 4619 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 4620 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 4621 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 4622 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 4623 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 4624 #endif 4625 #ifdef PMAP_CACHE_VIPT 4626 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 4627 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 4628 #else 4629 const vsize_t src_va_offset = 0; 4630 const vsize_t dst_va_offset = 0; 4631 #endif 4632 pt_entry_t * const src_ptep = &csrc_pte[src_va_offset >> PGSHIFT]; 4633 pt_entry_t * const dst_ptep = &cdst_pte[dst_va_offset >> PGSHIFT]; 4634 4635 #ifdef DEBUG 4636 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4637 panic("pmap_copy_page: dst page has mappings"); 4638 #endif 4639 4640 #ifdef PMAP_CACHE_VIPT 4641 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 4642 #endif 4643 KDASSERT((src & PGOFSET) == 0); 4644 KDASSERT((dst & PGOFSET) == 0); 4645 4646 /* 4647 * Clean the source page. Hold the source page's lock for 4648 * the duration of the copy so that no other mappings can 4649 * be created while we have a potentially aliased mapping. 4650 */ 4651 simple_lock(&src_md->pvh_slock); 4652 #ifdef PMAP_CACHE_VIVT 4653 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4654 #endif 4655 4656 /* 4657 * Map the pages into the page hook points, copy them, and purge 4658 * the cache for the appropriate page. Invalidate the TLB 4659 * as required. 4660 */ 4661 *src_ptep = L2_S_PROTO 4662 | src 4663 #ifdef PMAP_CACHE_VIPT 4664 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 4665 #endif 4666 #ifdef PMAP_CACHE_VIVT 4667 | pte_l2_s_cache_mode 4668 #endif 4669 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 4670 *dst_ptep = L2_S_PROTO | dst | 4671 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4672 PTE_SYNC(src_ptep); 4673 PTE_SYNC(dst_ptep); 4674 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4675 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4676 cpu_cpwait(); 4677 bcopy_page(csrcp + src_va_offset, cdstp + dst_va_offset); 4678 #ifdef PMAP_CACHE_VIVT 4679 cpu_dcache_inv_range(csrcp + src_va_offset, PAGE_SIZE); 4680 #endif 4681 simple_unlock(&src_md->pvh_slock); /* cache is safe again */ 4682 #ifdef PMAP_CACHE_VIVT 4683 cpu_dcache_wbinv_range(cdstp + dst_va_offset, PAGE_SIZE); 4684 #endif 4685 /* 4686 * Unmap the pages. 4687 */ 4688 *src_ptep = 0; 4689 *dst_ptep = 0; 4690 PTE_SYNC(src_ptep); 4691 PTE_SYNC(dst_ptep); 4692 cpu_tlb_flushD_SE(csrcp + src_va_offset); 4693 cpu_tlb_flushD_SE(cdstp + dst_va_offset); 4694 #ifdef PMAP_CACHE_VIPT 4695 /* 4696 * Now that the destination page is in the cache, mark it as colored. 4697 * If this was an exec page, discard it. 4698 */ 4699 if (!pmap_is_page_colored_p(dst_md)) { 4700 PMAPCOUNT(vac_color_new); 4701 dst_md->pvh_attrs |= PVF_COLORED; 4702 } 4703 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 4704 dst_md->pvh_attrs &= ~PVF_EXEC; 4705 PMAPCOUNT(exec_discarded_copy); 4706 } 4707 dst_md->pvh_attrs |= PVF_DIRTY; 4708 #endif 4709 } 4710 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 4711 4712 #if ARM_MMU_XSCALE == 1 4713 void 4714 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 4715 { 4716 struct vm_page_md *src_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(src)); 4717 #ifdef DEBUG 4718 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 4719 4720 if (!SLIST_EMPTY(&dst_md->pvh_list)) 4721 panic("pmap_copy_page: dst page has mappings"); 4722 #endif 4723 4724 KDASSERT((src & PGOFSET) == 0); 4725 KDASSERT((dst & PGOFSET) == 0); 4726 4727 /* 4728 * Clean the source page. Hold the source page's lock for 4729 * the duration of the copy so that no other mappings can 4730 * be created while we have a potentially aliased mapping. 4731 */ 4732 simple_lock(&src_md->pvh_slock); 4733 #ifdef PMAP_CACHE_VIVT 4734 (void) pmap_clean_page(SLIST_FIRST(&src_md->pvh_list), true); 4735 #endif 4736 4737 /* 4738 * Map the pages into the page hook points, copy them, and purge 4739 * the cache for the appropriate page. Invalidate the TLB 4740 * as required. 4741 */ 4742 *csrc_pte = L2_S_PROTO | src | 4743 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4744 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4745 PTE_SYNC(csrc_pte); 4746 *cdst_pte = L2_S_PROTO | dst | 4747 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4748 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 4749 PTE_SYNC(cdst_pte); 4750 cpu_tlb_flushD_SE(csrcp); 4751 cpu_tlb_flushD_SE(cdstp); 4752 cpu_cpwait(); 4753 bcopy_page(csrcp, cdstp); 4754 simple_unlock(&src_md->pvh_slock); /* cache is safe again */ 4755 xscale_cache_clean_minidata(); 4756 } 4757 #endif /* ARM_MMU_XSCALE == 1 */ 4758 4759 /* 4760 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4761 * 4762 * Return the start and end addresses of the kernel's virtual space. 4763 * These values are setup in pmap_bootstrap and are updated as pages 4764 * are allocated. 4765 */ 4766 void 4767 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 4768 { 4769 *start = virtual_avail; 4770 *end = virtual_end; 4771 } 4772 4773 /* 4774 * Helper function for pmap_grow_l2_bucket() 4775 */ 4776 static inline int 4777 pmap_grow_map(vaddr_t va, pt_entry_t cache_mode, paddr_t *pap) 4778 { 4779 struct l2_bucket *l2b; 4780 pt_entry_t *ptep; 4781 paddr_t pa; 4782 4783 if (uvm.page_init_done == false) { 4784 #ifdef PMAP_STEAL_MEMORY 4785 pv_addr_t pv; 4786 pmap_boot_pagealloc(PAGE_SIZE, 4787 #ifdef PMAP_CACHE_VIPT 4788 arm_cache_prefer_mask, 4789 va & arm_cache_prefer_mask, 4790 #else 4791 0, 0, 4792 #endif 4793 &pv); 4794 pa = pv.pv_pa; 4795 #else 4796 if (uvm_page_physget(&pa) == false) 4797 return (1); 4798 #endif /* PMAP_STEAL_MEMORY */ 4799 } else { 4800 struct vm_page *pg; 4801 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 4802 if (pg == NULL) 4803 return (1); 4804 pa = VM_PAGE_TO_PHYS(pg); 4805 #ifdef PMAP_CACHE_VIPT 4806 #ifdef DIAGNOSTIC 4807 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4808 #endif 4809 /* 4810 * This new page must not have any mappings. Enter it via 4811 * pmap_kenter_pa and let that routine do the hard work. 4812 */ 4813 KASSERT(SLIST_EMPTY(&md->pvh_list)); 4814 pmap_kenter_pa(va, pa, 4815 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE); 4816 #endif 4817 } 4818 4819 if (pap) 4820 *pap = pa; 4821 4822 PMAPCOUNT(pt_mappings); 4823 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4824 KDASSERT(l2b != NULL); 4825 4826 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4827 *ptep = L2_S_PROTO | pa | cache_mode | 4828 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 4829 PTE_SYNC(ptep); 4830 memset((void *)va, 0, PAGE_SIZE); 4831 return (0); 4832 } 4833 4834 /* 4835 * This is the same as pmap_alloc_l2_bucket(), except that it is only 4836 * used by pmap_growkernel(). 4837 */ 4838 static inline struct l2_bucket * 4839 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 4840 { 4841 struct l2_dtable *l2; 4842 struct l2_bucket *l2b; 4843 u_short l1idx; 4844 vaddr_t nva; 4845 4846 l1idx = L1_IDX(va); 4847 4848 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 4849 /* 4850 * No mapping at this address, as there is 4851 * no entry in the L1 table. 4852 * Need to allocate a new l2_dtable. 4853 */ 4854 nva = pmap_kernel_l2dtable_kva; 4855 if ((nva & PGOFSET) == 0) { 4856 /* 4857 * Need to allocate a backing page 4858 */ 4859 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4860 return (NULL); 4861 } 4862 4863 l2 = (struct l2_dtable *)nva; 4864 nva += sizeof(struct l2_dtable); 4865 4866 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 4867 /* 4868 * The new l2_dtable straddles a page boundary. 4869 * Map in another page to cover it. 4870 */ 4871 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 4872 return (NULL); 4873 } 4874 4875 pmap_kernel_l2dtable_kva = nva; 4876 4877 /* 4878 * Link it into the parent pmap 4879 */ 4880 pm->pm_l2[L2_IDX(l1idx)] = l2; 4881 } 4882 4883 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 4884 4885 /* 4886 * Fetch pointer to the L2 page table associated with the address. 4887 */ 4888 if (l2b->l2b_kva == NULL) { 4889 pt_entry_t *ptep; 4890 4891 /* 4892 * No L2 page table has been allocated. Chances are, this 4893 * is because we just allocated the l2_dtable, above. 4894 */ 4895 nva = pmap_kernel_l2ptp_kva; 4896 ptep = (pt_entry_t *)nva; 4897 if ((nva & PGOFSET) == 0) { 4898 /* 4899 * Need to allocate a backing page 4900 */ 4901 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 4902 &pmap_kernel_l2ptp_phys)) 4903 return (NULL); 4904 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 4905 } 4906 4907 l2->l2_occupancy++; 4908 l2b->l2b_kva = ptep; 4909 l2b->l2b_l1idx = l1idx; 4910 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 4911 4912 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 4913 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 4914 } 4915 4916 return (l2b); 4917 } 4918 4919 vaddr_t 4920 pmap_growkernel(vaddr_t maxkvaddr) 4921 { 4922 pmap_t kpm = pmap_kernel(); 4923 struct l1_ttable *l1; 4924 struct l2_bucket *l2b; 4925 pd_entry_t *pl1pd; 4926 int s; 4927 4928 if (maxkvaddr <= pmap_curmaxkvaddr) 4929 goto out; /* we are OK */ 4930 4931 NPDEBUG(PDB_GROWKERN, 4932 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 4933 pmap_curmaxkvaddr, maxkvaddr)); 4934 4935 KDASSERT(maxkvaddr <= virtual_end); 4936 4937 /* 4938 * whoops! we need to add kernel PTPs 4939 */ 4940 4941 s = splhigh(); /* to be safe */ 4942 mutex_enter(&kpm->pm_lock); 4943 4944 /* Map 1MB at a time */ 4945 for (; pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE) { 4946 4947 l2b = pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 4948 KDASSERT(l2b != NULL); 4949 4950 /* Distribute new L1 entry to all other L1s */ 4951 SLIST_FOREACH(l1, &l1_list, l1_link) { 4952 pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 4953 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 4954 L1_C_PROTO; 4955 PTE_SYNC(pl1pd); 4956 } 4957 } 4958 4959 /* 4960 * flush out the cache, expensive but growkernel will happen so 4961 * rarely 4962 */ 4963 cpu_dcache_wbinv_all(); 4964 cpu_tlb_flushD(); 4965 cpu_cpwait(); 4966 4967 mutex_exit(&kpm->pm_lock); 4968 splx(s); 4969 4970 out: 4971 return (pmap_curmaxkvaddr); 4972 } 4973 4974 /************************ Utility routines ****************************/ 4975 4976 /* 4977 * vector_page_setprot: 4978 * 4979 * Manipulate the protection of the vector page. 4980 */ 4981 void 4982 vector_page_setprot(int prot) 4983 { 4984 struct l2_bucket *l2b; 4985 pt_entry_t *ptep; 4986 4987 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 4988 KDASSERT(l2b != NULL); 4989 4990 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 4991 4992 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 4993 PTE_SYNC(ptep); 4994 cpu_tlb_flushD_SE(vector_page); 4995 cpu_cpwait(); 4996 } 4997 4998 /* 4999 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 5000 * Returns true if the mapping exists, else false. 5001 * 5002 * NOTE: This function is only used by a couple of arm-specific modules. 5003 * It is not safe to take any pmap locks here, since we could be right 5004 * in the middle of debugging the pmap anyway... 5005 * 5006 * It is possible for this routine to return false even though a valid 5007 * mapping does exist. This is because we don't lock, so the metadata 5008 * state may be inconsistent. 5009 * 5010 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 5011 * a "section" mapping. 5012 */ 5013 bool 5014 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5015 { 5016 struct l2_dtable *l2; 5017 pd_entry_t *pl1pd, l1pd; 5018 pt_entry_t *ptep; 5019 u_short l1idx; 5020 5021 if (pm->pm_l1 == NULL) 5022 return false; 5023 5024 l1idx = L1_IDX(va); 5025 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 5026 l1pd = *pl1pd; 5027 5028 if (l1pte_section_p(l1pd)) { 5029 *ptp = NULL; 5030 return true; 5031 } 5032 5033 if (pm->pm_l2 == NULL) 5034 return false; 5035 5036 l2 = pm->pm_l2[L2_IDX(l1idx)]; 5037 5038 if (l2 == NULL || 5039 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 5040 return false; 5041 } 5042 5043 *ptp = &ptep[l2pte_index(va)]; 5044 return true; 5045 } 5046 5047 bool 5048 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 5049 { 5050 u_short l1idx; 5051 5052 if (pm->pm_l1 == NULL) 5053 return false; 5054 5055 l1idx = L1_IDX(va); 5056 *pdp = &pm->pm_l1->l1_kva[l1idx]; 5057 5058 return true; 5059 } 5060 5061 /************************ Bootstrapping routines ****************************/ 5062 5063 static void 5064 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 5065 { 5066 int i; 5067 5068 l1->l1_kva = l1pt; 5069 l1->l1_domain_use_count = 0; 5070 l1->l1_domain_first = 0; 5071 5072 for (i = 0; i < PMAP_DOMAINS; i++) 5073 l1->l1_domain_free[i] = i + 1; 5074 5075 /* 5076 * Copy the kernel's L1 entries to each new L1. 5077 */ 5078 if (pmap_initialized) 5079 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 5080 5081 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 5082 &l1->l1_physaddr) == false) 5083 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 5084 5085 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 5086 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 5087 } 5088 5089 /* 5090 * pmap_bootstrap() is called from the board-specific initarm() routine 5091 * once the kernel L1/L2 descriptors tables have been set up. 5092 * 5093 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 5094 * spread over a number of disparate files/functions. 5095 * 5096 * We are passed the following parameters 5097 * - kernel_l1pt 5098 * This is a pointer to the base of the kernel's L1 translation table. 5099 * - vstart 5100 * 1MB-aligned start of managed kernel virtual memory. 5101 * - vend 5102 * 1MB-aligned end of managed kernel virtual memory. 5103 * 5104 * We use the first parameter to build the metadata (struct l1_ttable and 5105 * struct l2_dtable) necessary to track kernel mappings. 5106 */ 5107 #define PMAP_STATIC_L2_SIZE 16 5108 void 5109 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 5110 { 5111 static struct l1_ttable static_l1; 5112 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 5113 struct l1_ttable *l1 = &static_l1; 5114 struct l2_dtable *l2; 5115 struct l2_bucket *l2b; 5116 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 5117 pmap_t pm = pmap_kernel(); 5118 pd_entry_t pde; 5119 pt_entry_t *ptep; 5120 paddr_t pa; 5121 vaddr_t va; 5122 vsize_t size; 5123 int nptes, l1idx, l2idx, l2next = 0; 5124 5125 /* 5126 * Initialise the kernel pmap object 5127 */ 5128 pm->pm_l1 = l1; 5129 pm->pm_domain = PMAP_DOMAIN_KERNEL; 5130 pm->pm_activated = true; 5131 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5132 UVM_OBJ_INIT(&pm->pm_obj, NULL, 1); 5133 5134 /* 5135 * Scan the L1 translation table created by initarm() and create 5136 * the required metadata for all valid mappings found in it. 5137 */ 5138 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 5139 pde = l1pt[l1idx]; 5140 5141 /* 5142 * We're only interested in Coarse mappings. 5143 * pmap_extract() can deal with section mappings without 5144 * recourse to checking L2 metadata. 5145 */ 5146 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 5147 continue; 5148 5149 /* 5150 * Lookup the KVA of this L2 descriptor table 5151 */ 5152 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5153 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5154 if (ptep == NULL) { 5155 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 5156 (u_int)l1idx << L1_S_SHIFT, pa); 5157 } 5158 5159 /* 5160 * Fetch the associated L2 metadata structure. 5161 * Allocate a new one if necessary. 5162 */ 5163 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 5164 if (l2next == PMAP_STATIC_L2_SIZE) 5165 panic("pmap_bootstrap: out of static L2s"); 5166 pm->pm_l2[L2_IDX(l1idx)] = l2 = &static_l2[l2next++]; 5167 } 5168 5169 /* 5170 * One more L1 slot tracked... 5171 */ 5172 l2->l2_occupancy++; 5173 5174 /* 5175 * Fill in the details of the L2 descriptor in the 5176 * appropriate bucket. 5177 */ 5178 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 5179 l2b->l2b_kva = ptep; 5180 l2b->l2b_phys = pa; 5181 l2b->l2b_l1idx = l1idx; 5182 5183 /* 5184 * Establish an initial occupancy count for this descriptor 5185 */ 5186 for (l2idx = 0; 5187 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 5188 l2idx++) { 5189 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 5190 l2b->l2b_occupancy++; 5191 } 5192 } 5193 5194 /* 5195 * Make sure the descriptor itself has the correct cache mode. 5196 * If not, fix it, but whine about the problem. Port-meisters 5197 * should consider this a clue to fix up their initarm() 5198 * function. :) 5199 */ 5200 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep)) { 5201 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5202 "L2 pte @ %p\n", ptep); 5203 } 5204 } 5205 5206 /* 5207 * Ensure the primary (kernel) L1 has the correct cache mode for 5208 * a page table. Bitch if it is not correctly set. 5209 */ 5210 for (va = (vaddr_t)l1pt; 5211 va < ((vaddr_t)l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 5212 if (pmap_set_pt_cache_mode(l1pt, va)) 5213 printf("pmap_bootstrap: WARNING! wrong cache mode for " 5214 "primary L1 @ 0x%lx\n", va); 5215 } 5216 5217 cpu_dcache_wbinv_all(); 5218 cpu_tlb_flushID(); 5219 cpu_cpwait(); 5220 5221 /* 5222 * now we allocate the "special" VAs which are used for tmp mappings 5223 * by the pmap (and other modules). we allocate the VAs by advancing 5224 * virtual_avail (note that there are no pages mapped at these VAs). 5225 * 5226 * Managed KVM space start from wherever initarm() tells us. 5227 */ 5228 virtual_avail = vstart; 5229 virtual_end = vend; 5230 5231 #ifdef PMAP_CACHE_VIPT 5232 /* 5233 * If we have a VIPT cache, we need one page/pte per possible alias 5234 * page so we won't violate cache aliasing rules. 5235 */ 5236 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 5237 nptes = (arm_cache_prefer_mask >> PGSHIFT) + 1; 5238 #else 5239 nptes = 1; 5240 #endif 5241 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 5242 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte); 5243 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 5244 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte); 5245 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 5246 pmap_alloc_specials(&virtual_avail, round_page(MSGBUFSIZE) / PAGE_SIZE, 5247 (void *)&msgbufaddr, NULL); 5248 5249 /* 5250 * Allocate a range of kernel virtual address space to be used 5251 * for L2 descriptor tables and metadata allocation in 5252 * pmap_growkernel(). 5253 */ 5254 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 5255 pmap_alloc_specials(&virtual_avail, 5256 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 5257 &pmap_kernel_l2ptp_kva, NULL); 5258 5259 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 5260 pmap_alloc_specials(&virtual_avail, 5261 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 5262 &pmap_kernel_l2dtable_kva, NULL); 5263 5264 /* 5265 * init the static-global locks and global pmap list. 5266 */ 5267 /* spinlockinit(&pmap_main_lock, "pmaplk", 0); */ 5268 5269 /* 5270 * We can now initialise the first L1's metadata. 5271 */ 5272 SLIST_INIT(&l1_list); 5273 TAILQ_INIT(&l1_lru_list); 5274 simple_lock_init(&l1_lru_lock); 5275 pmap_init_l1(l1, l1pt); 5276 5277 /* Set up vector page L1 details, if necessary */ 5278 if (vector_page < KERNEL_BASE) { 5279 pm->pm_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 5280 l2b = pmap_get_l2_bucket(pm, vector_page); 5281 KDASSERT(l2b != NULL); 5282 pm->pm_l1vec = l2b->l2b_phys | L1_C_PROTO | 5283 L1_C_DOM(pm->pm_domain); 5284 } else 5285 pm->pm_pl1vec = NULL; 5286 5287 /* 5288 * Initialize the pmap cache 5289 */ 5290 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 5291 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 5292 LIST_INIT(&pmap_pmaps); 5293 LIST_INSERT_HEAD(&pmap_pmaps, pm, pm_list); 5294 5295 /* 5296 * Initialize the pv pool. 5297 */ 5298 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 5299 &pmap_bootstrap_pv_allocator, IPL_NONE); 5300 5301 /* 5302 * Initialize the L2 dtable pool and cache. 5303 */ 5304 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 5305 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 5306 5307 /* 5308 * Initialise the L2 descriptor table pool and cache 5309 */ 5310 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 5311 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 5312 pmap_l2ptp_ctor, NULL, NULL); 5313 5314 cpu_dcache_wbinv_all(); 5315 } 5316 5317 static int 5318 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va) 5319 { 5320 pd_entry_t *pdep, pde; 5321 pt_entry_t *ptep, pte; 5322 vaddr_t pa; 5323 int rv = 0; 5324 5325 /* 5326 * Make sure the descriptor itself has the correct cache mode 5327 */ 5328 pdep = &kl1[L1_IDX(va)]; 5329 pde = *pdep; 5330 5331 if (l1pte_section_p(pde)) { 5332 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 5333 *pdep = (pde & ~L1_S_CACHE_MASK) | 5334 pte_l1_s_cache_mode_pt; 5335 PTE_SYNC(pdep); 5336 cpu_dcache_wbinv_range((vaddr_t)pdep, sizeof(*pdep)); 5337 rv = 1; 5338 } 5339 } else { 5340 pa = (paddr_t)(pde & L1_C_ADDR_MASK); 5341 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 5342 if (ptep == NULL) 5343 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 5344 5345 ptep = &ptep[l2pte_index(va)]; 5346 pte = *ptep; 5347 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 5348 *ptep = (pte & ~L2_S_CACHE_MASK) | 5349 pte_l2_s_cache_mode_pt; 5350 PTE_SYNC(ptep); 5351 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 5352 rv = 1; 5353 } 5354 } 5355 5356 return (rv); 5357 } 5358 5359 static void 5360 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 5361 { 5362 vaddr_t va = *availp; 5363 struct l2_bucket *l2b; 5364 5365 if (ptep) { 5366 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5367 if (l2b == NULL) 5368 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 5369 5370 if (ptep) 5371 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 5372 } 5373 5374 *vap = va; 5375 *availp = va + (PAGE_SIZE * pages); 5376 } 5377 5378 void 5379 pmap_init(void) 5380 { 5381 5382 /* 5383 * Set the available memory vars - These do not map to real memory 5384 * addresses and cannot as the physical memory is fragmented. 5385 * They are used by ps for %mem calculations. 5386 * One could argue whether this should be the entire memory or just 5387 * the memory that is useable in a user process. 5388 */ 5389 avail_start = ptoa(VM_PHYSMEM_PTR(0)->start); 5390 avail_end = ptoa(VM_PHYSMEM_PTR(vm_nphysseg - 1)->end); 5391 5392 /* 5393 * Now we need to free enough pv_entry structures to allow us to get 5394 * the kmem_map/kmem_object allocated and inited (done after this 5395 * function is finished). to do this we allocate one bootstrap page out 5396 * of kernel_map and use it to provide an initial pool of pv_entry 5397 * structures. we never free this page. 5398 */ 5399 pool_setlowat(&pmap_pv_pool, 5400 (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 5401 5402 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 5403 zeropage = (void *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5404 UVM_KMF_WIRED|UVM_KMF_ZERO); 5405 5406 pmap_initialized = true; 5407 } 5408 5409 static vaddr_t last_bootstrap_page = 0; 5410 static void *free_bootstrap_pages = NULL; 5411 5412 static void * 5413 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 5414 { 5415 extern void *pool_page_alloc(struct pool *, int); 5416 vaddr_t new_page; 5417 void *rv; 5418 5419 if (pmap_initialized) 5420 return (pool_page_alloc(pp, flags)); 5421 5422 if (free_bootstrap_pages) { 5423 rv = free_bootstrap_pages; 5424 free_bootstrap_pages = *((void **)rv); 5425 return (rv); 5426 } 5427 5428 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 5429 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 5430 5431 KASSERT(new_page > last_bootstrap_page); 5432 last_bootstrap_page = new_page; 5433 return ((void *)new_page); 5434 } 5435 5436 static void 5437 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 5438 { 5439 extern void pool_page_free(struct pool *, void *); 5440 5441 if ((vaddr_t)v <= last_bootstrap_page) { 5442 *((void **)v) = free_bootstrap_pages; 5443 free_bootstrap_pages = v; 5444 return; 5445 } 5446 5447 if (pmap_initialized) { 5448 pool_page_free(pp, v); 5449 return; 5450 } 5451 } 5452 5453 /* 5454 * pmap_postinit() 5455 * 5456 * This routine is called after the vm and kmem subsystems have been 5457 * initialised. This allows the pmap code to perform any initialisation 5458 * that can only be done one the memory allocation is in place. 5459 */ 5460 void 5461 pmap_postinit(void) 5462 { 5463 extern paddr_t physical_start, physical_end; 5464 struct l2_bucket *l2b; 5465 struct l1_ttable *l1; 5466 struct pglist plist; 5467 struct vm_page *m; 5468 pd_entry_t *pl1pt; 5469 pt_entry_t *ptep, pte; 5470 vaddr_t va, eva; 5471 u_int loop, needed; 5472 int error; 5473 5474 pool_cache_setlowat(&pmap_l2ptp_cache, 5475 (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 5476 pool_cache_setlowat(&pmap_l2dtable_cache, 5477 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 5478 5479 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 5480 needed -= 1; 5481 5482 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 5483 5484 for (loop = 0; loop < needed; loop++, l1++) { 5485 /* Allocate a L1 page table */ 5486 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 5487 if (va == 0) 5488 panic("Cannot allocate L1 KVM"); 5489 5490 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 5491 physical_end, L1_TABLE_SIZE, 0, &plist, 1, M_WAITOK); 5492 if (error) 5493 panic("Cannot allocate L1 physical pages"); 5494 5495 m = TAILQ_FIRST(&plist); 5496 eva = va + L1_TABLE_SIZE; 5497 pl1pt = (pd_entry_t *)va; 5498 5499 while (m && va < eva) { 5500 paddr_t pa = VM_PAGE_TO_PHYS(m); 5501 5502 pmap_kenter_pa(va, pa, 5503 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE); 5504 5505 /* 5506 * Make sure the L1 descriptor table is mapped 5507 * with the cache-mode set to write-through. 5508 */ 5509 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5510 KDASSERT(l2b != NULL); 5511 ptep = &l2b->l2b_kva[l2pte_index(va)]; 5512 pte = *ptep; 5513 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 5514 *ptep = pte; 5515 PTE_SYNC(ptep); 5516 cpu_tlb_flushD_SE(va); 5517 5518 va += PAGE_SIZE; 5519 m = TAILQ_NEXT(m, pageq.queue); 5520 } 5521 5522 #ifdef DIAGNOSTIC 5523 if (m) 5524 panic("pmap_alloc_l1pt: pglist not empty"); 5525 #endif /* DIAGNOSTIC */ 5526 5527 pmap_init_l1(l1, pl1pt); 5528 } 5529 5530 #ifdef DEBUG 5531 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 5532 needed); 5533 #endif 5534 } 5535 5536 /* 5537 * Note that the following routines are used by board-specific initialisation 5538 * code to configure the initial kernel page tables. 5539 * 5540 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 5541 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 5542 * behaviour of the old pmap, and provides an easy migration path for 5543 * initial bring-up of the new pmap on existing ports. Fortunately, 5544 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 5545 * will be deprecated. 5546 * 5547 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 5548 * tables. 5549 */ 5550 5551 /* 5552 * This list exists for the benefit of pmap_map_chunk(). It keeps track 5553 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 5554 * find them as necessary. 5555 * 5556 * Note that the data on this list MUST remain valid after initarm() returns, 5557 * as pmap_bootstrap() uses it to contruct L2 table metadata. 5558 */ 5559 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 5560 5561 static vaddr_t 5562 kernel_pt_lookup(paddr_t pa) 5563 { 5564 pv_addr_t *pv; 5565 5566 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 5567 #ifndef ARM32_NEW_VM_LAYOUT 5568 if (pv->pv_pa == (pa & ~PGOFSET)) 5569 return (pv->pv_va | (pa & PGOFSET)); 5570 #else 5571 if (pv->pv_pa == pa) 5572 return (pv->pv_va); 5573 #endif 5574 } 5575 return (0); 5576 } 5577 5578 /* 5579 * pmap_map_section: 5580 * 5581 * Create a single section mapping. 5582 */ 5583 void 5584 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5585 { 5586 pd_entry_t *pde = (pd_entry_t *) l1pt; 5587 pd_entry_t fl; 5588 5589 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 5590 5591 switch (cache) { 5592 case PTE_NOCACHE: 5593 default: 5594 fl = 0; 5595 break; 5596 5597 case PTE_CACHE: 5598 fl = pte_l1_s_cache_mode; 5599 break; 5600 5601 case PTE_PAGETABLE: 5602 fl = pte_l1_s_cache_mode_pt; 5603 break; 5604 } 5605 5606 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5607 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 5608 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5609 } 5610 5611 /* 5612 * pmap_map_entry: 5613 * 5614 * Create a single page mapping. 5615 */ 5616 void 5617 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 5618 { 5619 pd_entry_t *pde = (pd_entry_t *) l1pt; 5620 pt_entry_t fl; 5621 pt_entry_t *pte; 5622 5623 KASSERT(((va | pa) & PGOFSET) == 0); 5624 5625 switch (cache) { 5626 case PTE_NOCACHE: 5627 default: 5628 fl = 0; 5629 break; 5630 5631 case PTE_CACHE: 5632 fl = pte_l2_s_cache_mode; 5633 break; 5634 5635 case PTE_PAGETABLE: 5636 fl = pte_l2_s_cache_mode_pt; 5637 break; 5638 } 5639 5640 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5641 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 5642 5643 #ifndef ARM32_NEW_VM_LAYOUT 5644 pte = (pt_entry_t *) 5645 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5646 #else 5647 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5648 #endif 5649 if (pte == NULL) 5650 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 5651 5652 fl |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 5653 #ifndef ARM32_NEW_VM_LAYOUT 5654 pte += (va >> PGSHIFT) & 0x3ff; 5655 #else 5656 pte += l2pte_index(va); 5657 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 5658 #endif 5659 *pte = fl; 5660 PTE_SYNC(pte); 5661 } 5662 5663 /* 5664 * pmap_link_l2pt: 5665 * 5666 * Link the L2 page table specified by "l2pv" into the L1 5667 * page table at the slot for "va". 5668 */ 5669 void 5670 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 5671 { 5672 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 5673 u_int slot = va >> L1_S_SHIFT; 5674 5675 #ifndef ARM32_NEW_VM_LAYOUT 5676 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0); 5677 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 5678 #endif 5679 5680 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 5681 5682 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 5683 #ifdef ARM32_NEW_VM_LAYOUT 5684 PTE_SYNC(&pde[slot]); 5685 #else 5686 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 5687 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 5688 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 5689 PTE_SYNC_RANGE(&pde[slot + 0], 4); 5690 #endif 5691 5692 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 5693 } 5694 5695 /* 5696 * pmap_map_chunk: 5697 * 5698 * Map a chunk of memory using the most efficient mappings 5699 * possible (section, large page, small page) into the 5700 * provided L1 and L2 tables at the specified virtual address. 5701 */ 5702 vsize_t 5703 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 5704 int prot, int cache) 5705 { 5706 pd_entry_t *pde = (pd_entry_t *) l1pt; 5707 pt_entry_t *pte, f1, f2s, f2l; 5708 vsize_t resid; 5709 int i; 5710 5711 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 5712 5713 if (l1pt == 0) 5714 panic("pmap_map_chunk: no L1 table provided"); 5715 5716 #ifdef VERBOSE_INIT_ARM 5717 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 5718 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 5719 #endif 5720 5721 switch (cache) { 5722 case PTE_NOCACHE: 5723 default: 5724 f1 = 0; 5725 f2l = 0; 5726 f2s = 0; 5727 break; 5728 5729 case PTE_CACHE: 5730 f1 = pte_l1_s_cache_mode; 5731 f2l = pte_l2_l_cache_mode; 5732 f2s = pte_l2_s_cache_mode; 5733 break; 5734 5735 case PTE_PAGETABLE: 5736 f1 = pte_l1_s_cache_mode_pt; 5737 f2l = pte_l2_l_cache_mode_pt; 5738 f2s = pte_l2_s_cache_mode_pt; 5739 break; 5740 } 5741 5742 size = resid; 5743 5744 while (resid > 0) { 5745 /* See if we can use a section mapping. */ 5746 if (L1_S_MAPPABLE_P(va, pa, resid)) { 5747 #ifdef VERBOSE_INIT_ARM 5748 printf("S"); 5749 #endif 5750 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 5751 L1_S_PROT(PTE_KERNEL, prot) | f1 | 5752 L1_S_DOM(PMAP_DOMAIN_KERNEL); 5753 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 5754 va += L1_S_SIZE; 5755 pa += L1_S_SIZE; 5756 resid -= L1_S_SIZE; 5757 continue; 5758 } 5759 5760 /* 5761 * Ok, we're going to use an L2 table. Make sure 5762 * one is actually in the corresponding L1 slot 5763 * for the current VA. 5764 */ 5765 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 5766 panic("pmap_map_chunk: no L2 table for VA 0x%08lx", va); 5767 5768 #ifndef ARM32_NEW_VM_LAYOUT 5769 pte = (pt_entry_t *) 5770 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 5771 #else 5772 pte = (pt_entry_t *) kernel_pt_lookup( 5773 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 5774 #endif 5775 if (pte == NULL) 5776 panic("pmap_map_chunk: can't find L2 table for VA" 5777 "0x%08lx", va); 5778 5779 /* See if we can use a L2 large page mapping. */ 5780 if (L2_L_MAPPABLE_P(va, pa, resid)) { 5781 #ifdef VERBOSE_INIT_ARM 5782 printf("L"); 5783 #endif 5784 for (i = 0; i < 16; i++) { 5785 #ifndef ARM32_NEW_VM_LAYOUT 5786 pte[((va >> PGSHIFT) & 0x3f0) + i] = 5787 L2_L_PROTO | pa | 5788 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5789 PTE_SYNC(&pte[((va >> PGSHIFT) & 0x3f0) + i]); 5790 #else 5791 pte[l2pte_index(va) + i] = 5792 L2_L_PROTO | pa | 5793 L2_L_PROT(PTE_KERNEL, prot) | f2l; 5794 PTE_SYNC(&pte[l2pte_index(va) + i]); 5795 #endif 5796 } 5797 va += L2_L_SIZE; 5798 pa += L2_L_SIZE; 5799 resid -= L2_L_SIZE; 5800 continue; 5801 } 5802 5803 /* Use a small page mapping. */ 5804 #ifdef VERBOSE_INIT_ARM 5805 printf("P"); 5806 #endif 5807 #ifndef ARM32_NEW_VM_LAYOUT 5808 pte[(va >> PGSHIFT) & 0x3ff] = 5809 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5810 PTE_SYNC(&pte[(va >> PGSHIFT) & 0x3ff]); 5811 #else 5812 pte[l2pte_index(va)] = 5813 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 5814 PTE_SYNC(&pte[l2pte_index(va)]); 5815 #endif 5816 va += PAGE_SIZE; 5817 pa += PAGE_SIZE; 5818 resid -= PAGE_SIZE; 5819 } 5820 #ifdef VERBOSE_INIT_ARM 5821 printf("\n"); 5822 #endif 5823 return (size); 5824 } 5825 5826 /********************** Static device map routines ***************************/ 5827 5828 static const struct pmap_devmap *pmap_devmap_table; 5829 5830 /* 5831 * Register the devmap table. This is provided in case early console 5832 * initialization needs to register mappings created by bootstrap code 5833 * before pmap_devmap_bootstrap() is called. 5834 */ 5835 void 5836 pmap_devmap_register(const struct pmap_devmap *table) 5837 { 5838 5839 pmap_devmap_table = table; 5840 } 5841 5842 /* 5843 * Map all of the static regions in the devmap table, and remember 5844 * the devmap table so other parts of the kernel can look up entries 5845 * later. 5846 */ 5847 void 5848 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 5849 { 5850 int i; 5851 5852 pmap_devmap_table = table; 5853 5854 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5855 #ifdef VERBOSE_INIT_ARM 5856 printf("devmap: %08lx -> %08lx @ %08lx\n", 5857 pmap_devmap_table[i].pd_pa, 5858 pmap_devmap_table[i].pd_pa + 5859 pmap_devmap_table[i].pd_size - 1, 5860 pmap_devmap_table[i].pd_va); 5861 #endif 5862 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 5863 pmap_devmap_table[i].pd_pa, 5864 pmap_devmap_table[i].pd_size, 5865 pmap_devmap_table[i].pd_prot, 5866 pmap_devmap_table[i].pd_cache); 5867 } 5868 } 5869 5870 const struct pmap_devmap * 5871 pmap_devmap_find_pa(paddr_t pa, psize_t size) 5872 { 5873 uint64_t endpa; 5874 int i; 5875 5876 if (pmap_devmap_table == NULL) 5877 return (NULL); 5878 5879 endpa = (uint64_t)pa + (uint64_t)(size - 1); 5880 5881 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5882 if (pa >= pmap_devmap_table[i].pd_pa && 5883 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 5884 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 5885 return (&pmap_devmap_table[i]); 5886 } 5887 5888 return (NULL); 5889 } 5890 5891 const struct pmap_devmap * 5892 pmap_devmap_find_va(vaddr_t va, vsize_t size) 5893 { 5894 int i; 5895 5896 if (pmap_devmap_table == NULL) 5897 return (NULL); 5898 5899 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 5900 if (va >= pmap_devmap_table[i].pd_va && 5901 va + size - 1 <= pmap_devmap_table[i].pd_va + 5902 pmap_devmap_table[i].pd_size - 1) 5903 return (&pmap_devmap_table[i]); 5904 } 5905 5906 return (NULL); 5907 } 5908 5909 /********************** PTE initialization routines **************************/ 5910 5911 /* 5912 * These routines are called when the CPU type is identified to set up 5913 * the PTE prototypes, cache modes, etc. 5914 * 5915 * The variables are always here, just in case modules need to reference 5916 * them (though, they shouldn't). 5917 */ 5918 5919 pt_entry_t pte_l1_s_cache_mode; 5920 pt_entry_t pte_l1_s_cache_mode_pt; 5921 pt_entry_t pte_l1_s_cache_mask; 5922 5923 pt_entry_t pte_l2_l_cache_mode; 5924 pt_entry_t pte_l2_l_cache_mode_pt; 5925 pt_entry_t pte_l2_l_cache_mask; 5926 5927 pt_entry_t pte_l2_s_cache_mode; 5928 pt_entry_t pte_l2_s_cache_mode_pt; 5929 pt_entry_t pte_l2_s_cache_mask; 5930 5931 pt_entry_t pte_l1_s_prot_u; 5932 pt_entry_t pte_l1_s_prot_w; 5933 pt_entry_t pte_l1_s_prot_ro; 5934 pt_entry_t pte_l1_s_prot_mask; 5935 5936 pt_entry_t pte_l2_s_prot_u; 5937 pt_entry_t pte_l2_s_prot_w; 5938 pt_entry_t pte_l2_s_prot_ro; 5939 pt_entry_t pte_l2_s_prot_mask; 5940 5941 pt_entry_t pte_l2_l_prot_u; 5942 pt_entry_t pte_l2_l_prot_w; 5943 pt_entry_t pte_l2_l_prot_ro; 5944 pt_entry_t pte_l2_l_prot_mask; 5945 5946 pt_entry_t pte_l1_s_proto; 5947 pt_entry_t pte_l1_c_proto; 5948 pt_entry_t pte_l2_s_proto; 5949 5950 void (*pmap_copy_page_func)(paddr_t, paddr_t); 5951 void (*pmap_zero_page_func)(paddr_t); 5952 5953 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5954 void 5955 pmap_pte_init_generic(void) 5956 { 5957 5958 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 5959 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 5960 5961 pte_l2_l_cache_mode = L2_B|L2_C; 5962 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 5963 5964 pte_l2_s_cache_mode = L2_B|L2_C; 5965 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 5966 5967 /* 5968 * If we have a write-through cache, set B and C. If 5969 * we have a write-back cache, then we assume setting 5970 * only C will make those pages write-through. 5971 */ 5972 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 5973 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 5974 pte_l2_l_cache_mode_pt = L2_B|L2_C; 5975 pte_l2_s_cache_mode_pt = L2_B|L2_C; 5976 } else { 5977 #if ARM_MMU_V6 > 1 5978 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; /* arm116 errata 399234 */ 5979 pte_l2_l_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5980 pte_l2_s_cache_mode_pt = L2_B|L2_C; /* arm116 errata 399234 */ 5981 #else 5982 pte_l1_s_cache_mode_pt = L1_S_C; 5983 pte_l2_l_cache_mode_pt = L2_C; 5984 pte_l2_s_cache_mode_pt = L2_C; 5985 #endif 5986 } 5987 5988 pte_l1_s_prot_u = L1_S_PROT_U_generic; 5989 pte_l1_s_prot_w = L1_S_PROT_W_generic; 5990 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 5991 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 5992 5993 pte_l2_s_prot_u = L2_S_PROT_U_generic; 5994 pte_l2_s_prot_w = L2_S_PROT_W_generic; 5995 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 5996 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 5997 5998 pte_l2_l_prot_u = L2_L_PROT_U_generic; 5999 pte_l2_l_prot_w = L2_L_PROT_W_generic; 6000 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 6001 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 6002 6003 pte_l1_s_proto = L1_S_PROTO_generic; 6004 pte_l1_c_proto = L1_C_PROTO_generic; 6005 pte_l2_s_proto = L2_S_PROTO_generic; 6006 6007 pmap_copy_page_func = pmap_copy_page_generic; 6008 pmap_zero_page_func = pmap_zero_page_generic; 6009 } 6010 6011 #if defined(CPU_ARM8) 6012 void 6013 pmap_pte_init_arm8(void) 6014 { 6015 6016 /* 6017 * ARM8 is compatible with generic, but we need to use 6018 * the page tables uncached. 6019 */ 6020 pmap_pte_init_generic(); 6021 6022 pte_l1_s_cache_mode_pt = 0; 6023 pte_l2_l_cache_mode_pt = 0; 6024 pte_l2_s_cache_mode_pt = 0; 6025 } 6026 #endif /* CPU_ARM8 */ 6027 6028 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 6029 void 6030 pmap_pte_init_arm9(void) 6031 { 6032 6033 /* 6034 * ARM9 is compatible with generic, but we want to use 6035 * write-through caching for now. 6036 */ 6037 pmap_pte_init_generic(); 6038 6039 pte_l1_s_cache_mode = L1_S_C; 6040 pte_l2_l_cache_mode = L2_C; 6041 pte_l2_s_cache_mode = L2_C; 6042 6043 pte_l1_s_cache_mode_pt = L1_S_C; 6044 pte_l2_l_cache_mode_pt = L2_C; 6045 pte_l2_s_cache_mode_pt = L2_C; 6046 } 6047 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 6048 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 6049 6050 #if defined(CPU_ARM10) 6051 void 6052 pmap_pte_init_arm10(void) 6053 { 6054 6055 /* 6056 * ARM10 is compatible with generic, but we want to use 6057 * write-through caching for now. 6058 */ 6059 pmap_pte_init_generic(); 6060 6061 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 6062 pte_l2_l_cache_mode = L2_B | L2_C; 6063 pte_l2_s_cache_mode = L2_B | L2_C; 6064 6065 pte_l1_s_cache_mode_pt = L1_S_C; 6066 pte_l2_l_cache_mode_pt = L2_C; 6067 pte_l2_s_cache_mode_pt = L2_C; 6068 6069 } 6070 #endif /* CPU_ARM10 */ 6071 6072 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 6073 void 6074 pmap_pte_init_arm11(void) 6075 { 6076 6077 /* 6078 * ARM11 is compatible with generic, but we want to use 6079 * write-through caching for now. 6080 */ 6081 pmap_pte_init_generic(); 6082 6083 pte_l1_s_cache_mode = L1_S_C; 6084 pte_l2_l_cache_mode = L2_C; 6085 pte_l2_s_cache_mode = L2_C; 6086 6087 pte_l1_s_cache_mode_pt = L1_S_C; 6088 pte_l2_l_cache_mode_pt = L2_C; 6089 pte_l2_s_cache_mode_pt = L2_C; 6090 } 6091 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 6092 6093 #if ARM_MMU_SA1 == 1 6094 void 6095 pmap_pte_init_sa1(void) 6096 { 6097 6098 /* 6099 * The StrongARM SA-1 cache does not have a write-through 6100 * mode. So, do the generic initialization, then reset 6101 * the page table cache mode to B=1,C=1, and note that 6102 * the PTEs need to be sync'd. 6103 */ 6104 pmap_pte_init_generic(); 6105 6106 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 6107 pte_l2_l_cache_mode_pt = L2_B|L2_C; 6108 pte_l2_s_cache_mode_pt = L2_B|L2_C; 6109 6110 pmap_needs_pte_sync = 1; 6111 } 6112 #endif /* ARM_MMU_SA1 == 1*/ 6113 6114 #if ARM_MMU_XSCALE == 1 6115 #if (ARM_NMMUS > 1) 6116 static u_int xscale_use_minidata; 6117 #endif 6118 6119 void 6120 pmap_pte_init_xscale(void) 6121 { 6122 uint32_t auxctl; 6123 int write_through = 0; 6124 6125 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 6126 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 6127 6128 pte_l2_l_cache_mode = L2_B|L2_C; 6129 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 6130 6131 pte_l2_s_cache_mode = L2_B|L2_C; 6132 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 6133 6134 pte_l1_s_cache_mode_pt = L1_S_C; 6135 pte_l2_l_cache_mode_pt = L2_C; 6136 pte_l2_s_cache_mode_pt = L2_C; 6137 6138 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 6139 /* 6140 * The XScale core has an enhanced mode where writes that 6141 * miss the cache cause a cache line to be allocated. This 6142 * is significantly faster than the traditional, write-through 6143 * behavior of this case. 6144 */ 6145 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 6146 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 6147 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 6148 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 6149 6150 #ifdef XSCALE_CACHE_WRITE_THROUGH 6151 /* 6152 * Some versions of the XScale core have various bugs in 6153 * their cache units, the work-around for which is to run 6154 * the cache in write-through mode. Unfortunately, this 6155 * has a major (negative) impact on performance. So, we 6156 * go ahead and run fast-and-loose, in the hopes that we 6157 * don't line up the planets in a way that will trip the 6158 * bugs. 6159 * 6160 * However, we give you the option to be slow-but-correct. 6161 */ 6162 write_through = 1; 6163 #elif defined(XSCALE_CACHE_WRITE_BACK) 6164 /* force write back cache mode */ 6165 write_through = 0; 6166 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 6167 /* 6168 * Intel PXA2[15]0 processors are known to have a bug in 6169 * write-back cache on revision 4 and earlier (stepping 6170 * A[01] and B[012]). Fixed for C0 and later. 6171 */ 6172 { 6173 uint32_t id, type; 6174 6175 id = cpufunc_id(); 6176 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 6177 6178 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 6179 if ((id & CPU_ID_REVISION_MASK) < 5) { 6180 /* write through for stepping A0-1 and B0-2 */ 6181 write_through = 1; 6182 } 6183 } 6184 } 6185 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 6186 6187 if (write_through) { 6188 pte_l1_s_cache_mode = L1_S_C; 6189 pte_l2_l_cache_mode = L2_C; 6190 pte_l2_s_cache_mode = L2_C; 6191 } 6192 6193 #if (ARM_NMMUS > 1) 6194 xscale_use_minidata = 1; 6195 #endif 6196 6197 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 6198 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 6199 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 6200 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 6201 6202 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 6203 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 6204 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 6205 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 6206 6207 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 6208 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 6209 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 6210 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 6211 6212 pte_l1_s_proto = L1_S_PROTO_xscale; 6213 pte_l1_c_proto = L1_C_PROTO_xscale; 6214 pte_l2_s_proto = L2_S_PROTO_xscale; 6215 6216 pmap_copy_page_func = pmap_copy_page_xscale; 6217 pmap_zero_page_func = pmap_zero_page_xscale; 6218 6219 /* 6220 * Disable ECC protection of page table access, for now. 6221 */ 6222 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6223 auxctl &= ~XSCALE_AUXCTL_P; 6224 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6225 } 6226 6227 /* 6228 * xscale_setup_minidata: 6229 * 6230 * Set up the mini-data cache clean area. We require the 6231 * caller to allocate the right amount of physically and 6232 * virtually contiguous space. 6233 */ 6234 void 6235 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 6236 { 6237 extern vaddr_t xscale_minidata_clean_addr; 6238 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 6239 pd_entry_t *pde = (pd_entry_t *) l1pt; 6240 pt_entry_t *pte; 6241 vsize_t size; 6242 uint32_t auxctl; 6243 6244 xscale_minidata_clean_addr = va; 6245 6246 /* Round it to page size. */ 6247 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 6248 6249 for (; size != 0; 6250 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 6251 #ifndef ARM32_NEW_VM_LAYOUT 6252 pte = (pt_entry_t *) 6253 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 6254 #else 6255 pte = (pt_entry_t *) kernel_pt_lookup( 6256 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 6257 #endif 6258 if (pte == NULL) 6259 panic("xscale_setup_minidata: can't find L2 table for " 6260 "VA 0x%08lx", va); 6261 #ifndef ARM32_NEW_VM_LAYOUT 6262 pte[(va >> PGSHIFT) & 0x3ff] = 6263 #else 6264 pte[l2pte_index(va)] = 6265 #endif 6266 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 6267 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); 6268 } 6269 6270 /* 6271 * Configure the mini-data cache for write-back with 6272 * read/write-allocate. 6273 * 6274 * NOTE: In order to reconfigure the mini-data cache, we must 6275 * make sure it contains no valid data! In order to do that, 6276 * we must issue a global data cache invalidate command! 6277 * 6278 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 6279 * THIS IS VERY IMPORTANT! 6280 */ 6281 6282 /* Invalidate data and mini-data. */ 6283 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 6284 __asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 6285 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 6286 __asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 6287 } 6288 6289 /* 6290 * Change the PTEs for the specified kernel mappings such that they 6291 * will use the mini data cache instead of the main data cache. 6292 */ 6293 void 6294 pmap_uarea(vaddr_t va) 6295 { 6296 struct l2_bucket *l2b; 6297 pt_entry_t *ptep, *sptep, pte; 6298 vaddr_t next_bucket, eva; 6299 6300 #if (ARM_NMMUS > 1) 6301 if (xscale_use_minidata == 0) 6302 return; 6303 #endif 6304 6305 eva = va + USPACE; 6306 6307 while (va < eva) { 6308 next_bucket = L2_NEXT_BUCKET(va); 6309 if (next_bucket > eva) 6310 next_bucket = eva; 6311 6312 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6313 KDASSERT(l2b != NULL); 6314 6315 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 6316 6317 while (va < next_bucket) { 6318 pte = *ptep; 6319 if (!l2pte_minidata(pte)) { 6320 cpu_dcache_wbinv_range(va, PAGE_SIZE); 6321 cpu_tlb_flushD_SE(va); 6322 *ptep = pte & ~L2_B; 6323 } 6324 ptep++; 6325 va += PAGE_SIZE; 6326 } 6327 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 6328 } 6329 cpu_cpwait(); 6330 } 6331 #endif /* ARM_MMU_XSCALE == 1 */ 6332 6333 #if ARM_MMU_V7 == 1 6334 void 6335 pmap_pte_init_armv7(void) 6336 { 6337 /* 6338 * The ARMv7-A MMU is mostly compatible with generic. If the 6339 * AP field is zero, that now means "no access" rather than 6340 * read-only. The prototypes are a little different because of 6341 * the XN bit. 6342 */ 6343 pmap_pte_init_generic(); 6344 6345 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 6346 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 6347 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 6348 6349 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 6350 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 6351 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 6352 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 6353 6354 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 6355 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 6356 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 6357 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 6358 6359 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 6360 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 6361 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 6362 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 6363 6364 pte_l1_s_proto = L1_S_PROTO_armv7; 6365 pte_l1_c_proto = L1_C_PROTO_armv7; 6366 pte_l2_s_proto = L2_S_PROTO_armv7; 6367 } 6368 #endif /* ARM_MMU_V7 */ 6369 6370 /* 6371 * return the PA of the current L1 table, for use when handling a crash dump 6372 */ 6373 uint32_t pmap_kernel_L1_addr(void) 6374 { 6375 return pmap_kernel()->pm_l1->l1_physaddr; 6376 } 6377 6378 #if defined(DDB) 6379 /* 6380 * A couple of ddb-callable functions for dumping pmaps 6381 */ 6382 void pmap_dump_all(void); 6383 void pmap_dump(pmap_t); 6384 6385 void 6386 pmap_dump_all(void) 6387 { 6388 pmap_t pm; 6389 6390 LIST_FOREACH(pm, &pmap_pmaps, pm_list) { 6391 if (pm == pmap_kernel()) 6392 continue; 6393 pmap_dump(pm); 6394 printf("\n"); 6395 } 6396 } 6397 6398 static pt_entry_t ncptes[64]; 6399 static void pmap_dump_ncpg(pmap_t); 6400 6401 void 6402 pmap_dump(pmap_t pm) 6403 { 6404 struct l2_dtable *l2; 6405 struct l2_bucket *l2b; 6406 pt_entry_t *ptep, pte; 6407 vaddr_t l2_va, l2b_va, va; 6408 int i, j, k, occ, rows = 0; 6409 6410 if (pm == pmap_kernel()) 6411 printf("pmap_kernel (%p): ", pm); 6412 else 6413 printf("user pmap (%p): ", pm); 6414 6415 printf("domain %d, l1 at %p\n", pm->pm_domain, pm->pm_l1->l1_kva); 6416 6417 l2_va = 0; 6418 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 6419 l2 = pm->pm_l2[i]; 6420 6421 if (l2 == NULL || l2->l2_occupancy == 0) 6422 continue; 6423 6424 l2b_va = l2_va; 6425 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 6426 l2b = &l2->l2_bucket[j]; 6427 6428 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 6429 continue; 6430 6431 ptep = l2b->l2b_kva; 6432 6433 for (k = 0; k < 256 && ptep[k] == 0; k++) 6434 ; 6435 6436 k &= ~63; 6437 occ = l2b->l2b_occupancy; 6438 va = l2b_va + (k * 4096); 6439 for (; k < 256; k++, va += 0x1000) { 6440 char ch = ' '; 6441 if ((k % 64) == 0) { 6442 if ((rows % 8) == 0) { 6443 printf( 6444 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 6445 } 6446 printf("%08lx: ", va); 6447 } 6448 6449 ncptes[k & 63] = 0; 6450 pte = ptep[k]; 6451 if (pte == 0) { 6452 ch = '.'; 6453 } else { 6454 occ--; 6455 switch (pte & 0x0c) { 6456 case 0x00: 6457 ch = 'D'; /* No cache No buff */ 6458 break; 6459 case 0x04: 6460 ch = 'B'; /* No cache buff */ 6461 break; 6462 case 0x08: 6463 if (pte & 0x40) 6464 ch = 'm'; 6465 else 6466 ch = 'C'; /* Cache No buff */ 6467 break; 6468 case 0x0c: 6469 ch = 'F'; /* Cache Buff */ 6470 break; 6471 } 6472 6473 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 6474 ch += 0x20; 6475 6476 if ((pte & 0xc) == 0) 6477 ncptes[k & 63] = pte; 6478 } 6479 6480 if ((k % 64) == 63) { 6481 rows++; 6482 printf("%c\n", ch); 6483 pmap_dump_ncpg(pm); 6484 if (occ == 0) 6485 break; 6486 } else 6487 printf("%c", ch); 6488 } 6489 } 6490 } 6491 } 6492 6493 static void 6494 pmap_dump_ncpg(pmap_t pm) 6495 { 6496 struct vm_page *pg; 6497 struct vm_page_md *md; 6498 struct pv_entry *pv; 6499 int i; 6500 6501 for (i = 0; i < 63; i++) { 6502 if (ncptes[i] == 0) 6503 continue; 6504 6505 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 6506 if (pg == NULL) 6507 continue; 6508 md = VM_PAGE_TO_MD(pg); 6509 6510 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 6511 VM_PAGE_TO_PHYS(pg), 6512 md->krw_mappings, md->kro_mappings, 6513 md->urw_mappings, md->uro_mappings); 6514 6515 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 6516 printf(" %c va 0x%08lx, flags 0x%x\n", 6517 (pm == pv->pv_pmap) ? '*' : ' ', 6518 pv->pv_va, pv->pv_flags); 6519 } 6520 } 6521 } 6522 #endif 6523 6524 #ifdef PMAP_STEAL_MEMORY 6525 void 6526 pmap_boot_pageadd(pv_addr_t *newpv) 6527 { 6528 pv_addr_t *pv, *npv; 6529 6530 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 6531 if (newpv->pv_pa < pv->pv_va) { 6532 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 6533 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 6534 newpv->pv_size += pv->pv_size; 6535 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 6536 } 6537 pv = NULL; 6538 } else { 6539 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 6540 pv = npv) { 6541 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 6542 KASSERT(pv->pv_pa < newpv->pv_pa); 6543 if (newpv->pv_pa > npv->pv_pa) 6544 continue; 6545 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 6546 pv->pv_size += newpv->pv_size; 6547 return; 6548 } 6549 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 6550 break; 6551 newpv->pv_size += npv->pv_size; 6552 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6553 SLIST_REMOVE_AFTER(newpv, pv_list); 6554 return; 6555 } 6556 } 6557 } 6558 6559 if (pv) { 6560 SLIST_INSERT_AFTER(pv, newpv, pv_list); 6561 } else { 6562 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 6563 } 6564 } 6565 6566 void 6567 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 6568 pv_addr_t *rpv) 6569 { 6570 pv_addr_t *pv, **pvp; 6571 struct vm_physseg *ps; 6572 size_t i; 6573 6574 KASSERT(amount & PGOFSET); 6575 KASSERT((mask & PGOFSET) == 0); 6576 KASSERT((match & PGOFSET) == 0); 6577 KASSERT(amount != 0); 6578 6579 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6580 (pv = *pvp) != NULL; 6581 pvp = &SLIST_NEXT(pv, pv_list)) { 6582 pv_addr_t *newpv; 6583 psize_t off; 6584 /* 6585 * If this entry is too small to satify the request... 6586 */ 6587 KASSERT(pv->pv_size > 0); 6588 if (pv->pv_size < amount) 6589 continue; 6590 6591 for (off = 0; off <= mask; off += PAGE_SIZE) { 6592 if (((pv->pv_pa + off) & mask) == match 6593 && off + amount <= pv->pv_size) 6594 break; 6595 } 6596 if (off > mask) 6597 continue; 6598 6599 rpv->pv_va = pv->pv_va + off; 6600 rpv->pv_pa = pv->pv_pa + off; 6601 rpv->pv_size = amount; 6602 pv->pv_size -= amount; 6603 if (pv->pv_size == 0) { 6604 KASSERT(off == 0); 6605 KASSERT((vaddr_t) pv == rpv->pv_va); 6606 *pvp = SLIST_NEXT(pv, pv_list); 6607 } else if (off == 0) { 6608 KASSERT((vaddr_t) pv == rpv->pv_va); 6609 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6610 *newpv = *pv; 6611 newpv->pv_pa += amount; 6612 newpv->pv_va += amount; 6613 *pvp = newpv; 6614 } else if (off < pv->pv_size) { 6615 newpv = (pv_addr_t *) (rpv->pv_va + amount); 6616 *newpv = *pv; 6617 newpv->pv_size -= off; 6618 newpv->pv_pa += off + amount; 6619 newpv->pv_va += off + amount; 6620 6621 SLIST_NEXT(pv, pv_list) = newpv; 6622 pv->pv_size = off; 6623 } else { 6624 KASSERT((vaddr_t) pv != rpv->pv_va); 6625 } 6626 memset((void *)rpv->pv_va, 0, amount); 6627 return; 6628 } 6629 6630 if (vm_nphysseg == 0) 6631 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6632 6633 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 6634 (pv = *pvp) != NULL; 6635 pvp = &SLIST_NEXT(pv, pv_list)) { 6636 if (SLIST_NEXT(pv, pv_list) == NULL) 6637 break; 6638 } 6639 KASSERT(mask == 0); 6640 for (i = 0; i < vm_nphysseg; i++) { 6641 ps = VM_PHYSMEM_PTR(i); 6642 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 6643 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 6644 rpv->pv_va = pv->pv_va; 6645 rpv->pv_pa = pv->pv_pa; 6646 rpv->pv_size = amount; 6647 *pvp = NULL; 6648 pmap_map_chunk(kernel_l1pt.pv_va, 6649 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 6650 ptoa(ps->avail_start), 6651 amount - pv->pv_size, 6652 VM_PROT_READ|VM_PROT_WRITE, 6653 PTE_CACHE); 6654 ps->avail_start += atop(amount - pv->pv_size); 6655 /* 6656 * If we consumed the entire physseg, remove it. 6657 */ 6658 if (ps->avail_start == ps->avail_end) { 6659 for (--vm_nphysseg; i < vm_nphysseg; i++) 6660 VM_PHYSMEM_PTR_SWAP(i, i + 1); 6661 } 6662 memset((void *)rpv->pv_va, 0, rpv->pv_size); 6663 return; 6664 } 6665 } 6666 6667 panic("pmap_boot_pagealloc: couldn't allocate memory"); 6668 } 6669 6670 vaddr_t 6671 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 6672 { 6673 pv_addr_t pv; 6674 6675 pmap_boot_pagealloc(size, 0, 0, &pv); 6676 6677 return pv.pv_va; 6678 } 6679 #endif /* PMAP_STEAL_MEMORY */ 6680 6681 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 6682 { 6683 sysctl_createv(clog, 0, NULL, NULL, 6684 CTLFLAG_PERMANENT, 6685 CTLTYPE_NODE, "machdep", NULL, 6686 NULL, 0, NULL, 0, 6687 CTL_MACHDEP, CTL_EOL); 6688 6689 sysctl_createv(clog, 0, NULL, NULL, 6690 CTLFLAG_PERMANENT, 6691 CTLTYPE_INT, "kmpages", 6692 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 6693 NULL, 0, &pmap_kmpages, 0, 6694 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 6695 } 6696