1 /* $NetBSD: pmap.c,v 1.361 2017/11/01 21:13:26 skrll Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil@causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of in kernel VA space, 166 * then MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* 183 * Special compilation symbols 184 * PMAP_DEBUG - Build in pmap_debug_level code 185 */ 186 187 /* Include header files */ 188 189 #include "opt_arm_debug.h" 190 #include "opt_cpuoptions.h" 191 #include "opt_pmap_debug.h" 192 #include "opt_ddb.h" 193 #include "opt_lockdebug.h" 194 #include "opt_multiprocessor.h" 195 196 #ifdef MULTIPROCESSOR 197 #define _INTR_PRIVATE 198 #endif 199 200 #include <sys/param.h> 201 #include <sys/types.h> 202 #include <sys/kernel.h> 203 #include <sys/systm.h> 204 #include <sys/proc.h> 205 #include <sys/intr.h> 206 #include <sys/pool.h> 207 #include <sys/kmem.h> 208 #include <sys/cdefs.h> 209 #include <sys/cpu.h> 210 #include <sys/sysctl.h> 211 #include <sys/bus.h> 212 #include <sys/atomic.h> 213 #include <sys/kernhist.h> 214 215 #include <uvm/uvm.h> 216 #include <uvm/pmap/pmap_pvt.h> 217 218 #include <arm/locore.h> 219 220 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.361 2017/11/01 21:13:26 skrll Exp $"); 221 222 //#define PMAP_DEBUG 223 #ifdef PMAP_DEBUG 224 225 /* XXX need to get rid of all refs to this */ 226 int pmap_debug_level = 0; 227 228 /* 229 * for switching to potentially finer grained debugging 230 */ 231 #define PDB_FOLLOW 0x0001 232 #define PDB_INIT 0x0002 233 #define PDB_ENTER 0x0004 234 #define PDB_REMOVE 0x0008 235 #define PDB_CREATE 0x0010 236 #define PDB_PTPAGE 0x0020 237 #define PDB_GROWKERN 0x0040 238 #define PDB_BITS 0x0080 239 #define PDB_COLLECT 0x0100 240 #define PDB_PROTECT 0x0200 241 #define PDB_MAP_L1 0x0400 242 #define PDB_BOOTSTRAP 0x1000 243 #define PDB_PARANOIA 0x2000 244 #define PDB_WIRING 0x4000 245 #define PDB_PVDUMP 0x8000 246 #define PDB_VAC 0x10000 247 #define PDB_KENTER 0x20000 248 #define PDB_KREMOVE 0x40000 249 #define PDB_EXEC 0x80000 250 251 int debugmap = 1; 252 int pmapdebug = 0; 253 #define NPDEBUG(_lev_,_stat_) \ 254 if (pmapdebug & (_lev_)) \ 255 ((_stat_)) 256 257 #else /* PMAP_DEBUG */ 258 #define NPDEBUG(_lev_,_stat_) /* Nothing */ 259 #endif /* PMAP_DEBUG */ 260 261 /* 262 * pmap_kernel() points here 263 */ 264 static struct pmap kernel_pmap_store = { 265 #ifndef ARM_MMU_EXTENDED 266 .pm_activated = true, 267 .pm_domain = PMAP_DOMAIN_KERNEL, 268 .pm_cstate.cs_all = PMAP_CACHE_STATE_ALL, 269 #endif 270 }; 271 struct pmap * const kernel_pmap_ptr = &kernel_pmap_store; 272 #undef pmap_kernel 273 #define pmap_kernel() (&kernel_pmap_store) 274 #ifdef PMAP_NEED_ALLOC_POOLPAGE 275 int arm_poolpage_vmfreelist = VM_FREELIST_DEFAULT; 276 #endif 277 278 /* 279 * Pool and cache that pmap structures are allocated from. 280 * We use a cache to avoid clearing the pm_l2[] array (1KB) 281 * in pmap_create(). 282 */ 283 static struct pool_cache pmap_cache; 284 285 /* 286 * Pool of PV structures 287 */ 288 static struct pool pmap_pv_pool; 289 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 290 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 291 static struct pool_allocator pmap_bootstrap_pv_allocator = { 292 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 293 }; 294 295 /* 296 * Pool and cache of l2_dtable structures. 297 * We use a cache to avoid clearing the structures when they're 298 * allocated. (196 bytes) 299 */ 300 static struct pool_cache pmap_l2dtable_cache; 301 static vaddr_t pmap_kernel_l2dtable_kva; 302 303 /* 304 * Pool and cache of L2 page descriptors. 305 * We use a cache to avoid clearing the descriptor table 306 * when they're allocated. (1KB) 307 */ 308 static struct pool_cache pmap_l2ptp_cache; 309 static vaddr_t pmap_kernel_l2ptp_kva; 310 static paddr_t pmap_kernel_l2ptp_phys; 311 312 #ifdef PMAPCOUNTERS 313 #define PMAP_EVCNT_INITIALIZER(name) \ 314 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 315 316 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 317 static struct evcnt pmap_ev_vac_clean_one = 318 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 319 static struct evcnt pmap_ev_vac_flush_one = 320 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 321 static struct evcnt pmap_ev_vac_flush_lots = 322 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 323 static struct evcnt pmap_ev_vac_flush_lots2 = 324 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 325 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 326 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 327 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 328 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 329 330 static struct evcnt pmap_ev_vac_color_new = 331 PMAP_EVCNT_INITIALIZER("new page color"); 332 static struct evcnt pmap_ev_vac_color_reuse = 333 PMAP_EVCNT_INITIALIZER("ok first page color"); 334 static struct evcnt pmap_ev_vac_color_ok = 335 PMAP_EVCNT_INITIALIZER("ok page color"); 336 static struct evcnt pmap_ev_vac_color_blind = 337 PMAP_EVCNT_INITIALIZER("blind page color"); 338 static struct evcnt pmap_ev_vac_color_change = 339 PMAP_EVCNT_INITIALIZER("change page color"); 340 static struct evcnt pmap_ev_vac_color_erase = 341 PMAP_EVCNT_INITIALIZER("erase page color"); 342 static struct evcnt pmap_ev_vac_color_none = 343 PMAP_EVCNT_INITIALIZER("no page color"); 344 static struct evcnt pmap_ev_vac_color_restore = 345 PMAP_EVCNT_INITIALIZER("restore page color"); 346 347 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 348 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 349 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 350 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 351 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 352 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 353 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 354 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 355 #endif 356 357 static struct evcnt pmap_ev_mappings = 358 PMAP_EVCNT_INITIALIZER("pages mapped"); 359 static struct evcnt pmap_ev_unmappings = 360 PMAP_EVCNT_INITIALIZER("pages unmapped"); 361 static struct evcnt pmap_ev_remappings = 362 PMAP_EVCNT_INITIALIZER("pages remapped"); 363 364 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 365 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 366 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 367 368 static struct evcnt pmap_ev_kernel_mappings = 369 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 370 static struct evcnt pmap_ev_kernel_unmappings = 371 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 372 static struct evcnt pmap_ev_kernel_remappings = 373 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 374 375 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 376 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 377 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 378 379 static struct evcnt pmap_ev_kenter_mappings = 380 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 381 static struct evcnt pmap_ev_kenter_unmappings = 382 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 383 static struct evcnt pmap_ev_kenter_remappings = 384 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 385 static struct evcnt pmap_ev_pt_mappings = 386 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 387 388 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 389 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 390 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 391 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 392 393 static struct evcnt pmap_ev_fixup_mod = 394 PMAP_EVCNT_INITIALIZER("page modification emulations"); 395 static struct evcnt pmap_ev_fixup_ref = 396 PMAP_EVCNT_INITIALIZER("page reference emulations"); 397 static struct evcnt pmap_ev_fixup_exec = 398 PMAP_EVCNT_INITIALIZER("exec pages fixed up"); 399 static struct evcnt pmap_ev_fixup_pdes = 400 PMAP_EVCNT_INITIALIZER("pdes fixed up"); 401 #ifndef ARM_MMU_EXTENDED 402 static struct evcnt pmap_ev_fixup_ptesync = 403 PMAP_EVCNT_INITIALIZER("ptesync fixed"); 404 #endif 405 406 EVCNT_ATTACH_STATIC(pmap_ev_fixup_mod); 407 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ref); 408 EVCNT_ATTACH_STATIC(pmap_ev_fixup_exec); 409 EVCNT_ATTACH_STATIC(pmap_ev_fixup_pdes); 410 #ifndef ARM_MMU_EXTENDED 411 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ptesync); 412 #endif 413 414 #ifdef PMAP_CACHE_VIPT 415 static struct evcnt pmap_ev_exec_mappings = 416 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 417 static struct evcnt pmap_ev_exec_cached = 418 PMAP_EVCNT_INITIALIZER("exec pages cached"); 419 420 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 421 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 422 423 static struct evcnt pmap_ev_exec_synced = 424 PMAP_EVCNT_INITIALIZER("exec pages synced"); 425 static struct evcnt pmap_ev_exec_synced_map = 426 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 427 static struct evcnt pmap_ev_exec_synced_unmap = 428 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 429 static struct evcnt pmap_ev_exec_synced_remap = 430 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 431 static struct evcnt pmap_ev_exec_synced_clearbit = 432 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 433 #ifndef ARM_MMU_EXTENDED 434 static struct evcnt pmap_ev_exec_synced_kremove = 435 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 436 #endif 437 438 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 439 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 440 #ifndef ARM_MMU_EXTENDED 441 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 442 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 443 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 444 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 445 #endif 446 447 static struct evcnt pmap_ev_exec_discarded_unmap = 448 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 449 static struct evcnt pmap_ev_exec_discarded_zero = 450 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 451 static struct evcnt pmap_ev_exec_discarded_copy = 452 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 453 static struct evcnt pmap_ev_exec_discarded_page_protect = 454 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 455 static struct evcnt pmap_ev_exec_discarded_clearbit = 456 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 457 static struct evcnt pmap_ev_exec_discarded_kremove = 458 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 459 #ifdef ARM_MMU_EXTENDED 460 static struct evcnt pmap_ev_exec_discarded_modfixup = 461 PMAP_EVCNT_INITIALIZER("exec pages discarded (MF)"); 462 #endif 463 464 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 465 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 466 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 467 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 468 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 469 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 470 #ifdef ARM_MMU_EXTENDED 471 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_modfixup); 472 #endif 473 #endif /* PMAP_CACHE_VIPT */ 474 475 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 476 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 477 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 478 479 EVCNT_ATTACH_STATIC(pmap_ev_updates); 480 EVCNT_ATTACH_STATIC(pmap_ev_collects); 481 EVCNT_ATTACH_STATIC(pmap_ev_activations); 482 483 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 484 #else 485 #define PMAPCOUNT(x) ((void)0) 486 #endif 487 488 #ifdef ARM_MMU_EXTENDED 489 void pmap_md_pdetab_activate(pmap_t, struct lwp *); 490 void pmap_md_pdetab_deactivate(pmap_t pm); 491 #endif 492 493 /* 494 * pmap copy/zero page, and mem(5) hook point 495 */ 496 static pt_entry_t *csrc_pte, *cdst_pte; 497 static vaddr_t csrcp, cdstp; 498 #ifdef MULTIPROCESSOR 499 static size_t cnptes; 500 #define cpu_csrc_pte(o) (csrc_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 501 #define cpu_cdst_pte(o) (cdst_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 502 #define cpu_csrcp(o) (csrcp + L2_S_SIZE * cnptes * cpu_number() + (o)) 503 #define cpu_cdstp(o) (cdstp + L2_S_SIZE * cnptes * cpu_number() + (o)) 504 #else 505 #define cpu_csrc_pte(o) (csrc_pte + ((o) >> L2_S_SHIFT)) 506 #define cpu_cdst_pte(o) (cdst_pte + ((o) >> L2_S_SHIFT)) 507 #define cpu_csrcp(o) (csrcp + (o)) 508 #define cpu_cdstp(o) (cdstp + (o)) 509 #endif 510 vaddr_t memhook; /* used by mem.c & others */ 511 kmutex_t memlock __cacheline_aligned; /* used by mem.c & others */ 512 kmutex_t pmap_lock __cacheline_aligned; 513 extern void *msgbufaddr; 514 int pmap_kmpages; 515 /* 516 * Flag to indicate if pmap_init() has done its thing 517 */ 518 bool pmap_initialized; 519 520 #if defined(ARM_MMU_EXTENDED) && defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 521 /* 522 * Virtual end of direct-mapped memory 523 */ 524 vaddr_t pmap_directlimit; 525 #endif 526 527 /* 528 * Misc. locking data structures 529 */ 530 531 static inline void 532 pmap_acquire_pmap_lock(pmap_t pm) 533 { 534 if (pm == pmap_kernel()) { 535 #ifdef MULTIPROCESSOR 536 KERNEL_LOCK(1, NULL); 537 #endif 538 } else { 539 mutex_enter(pm->pm_lock); 540 } 541 } 542 543 static inline void 544 pmap_release_pmap_lock(pmap_t pm) 545 { 546 if (pm == pmap_kernel()) { 547 #ifdef MULTIPROCESSOR 548 KERNEL_UNLOCK_ONE(NULL); 549 #endif 550 } else { 551 mutex_exit(pm->pm_lock); 552 } 553 } 554 555 static inline void 556 pmap_acquire_page_lock(struct vm_page_md *md) 557 { 558 mutex_enter(&pmap_lock); 559 } 560 561 static inline void 562 pmap_release_page_lock(struct vm_page_md *md) 563 { 564 mutex_exit(&pmap_lock); 565 } 566 567 #ifdef DIAGNOSTIC 568 static inline int 569 pmap_page_locked_p(struct vm_page_md *md) 570 { 571 return mutex_owned(&pmap_lock); 572 } 573 #endif 574 575 576 /* 577 * Metadata for L1 translation tables. 578 */ 579 #ifndef ARM_MMU_EXTENDED 580 struct l1_ttable { 581 /* Entry on the L1 Table list */ 582 SLIST_ENTRY(l1_ttable) l1_link; 583 584 /* Entry on the L1 Least Recently Used list */ 585 TAILQ_ENTRY(l1_ttable) l1_lru; 586 587 /* Track how many domains are allocated from this L1 */ 588 volatile u_int l1_domain_use_count; 589 590 /* 591 * A free-list of domain numbers for this L1. 592 * We avoid using ffs() and a bitmap to track domains since ffs() 593 * is slow on ARM. 594 */ 595 uint8_t l1_domain_first; 596 uint8_t l1_domain_free[PMAP_DOMAINS]; 597 598 /* Physical address of this L1 page table */ 599 paddr_t l1_physaddr; 600 601 /* KVA of this L1 page table */ 602 pd_entry_t *l1_kva; 603 }; 604 605 /* 606 * L1 Page Tables are tracked using a Least Recently Used list. 607 * - New L1s are allocated from the HEAD. 608 * - Freed L1s are added to the TAIl. 609 * - Recently accessed L1s (where an 'access' is some change to one of 610 * the userland pmaps which owns this L1) are moved to the TAIL. 611 */ 612 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 613 static kmutex_t l1_lru_lock __cacheline_aligned; 614 615 /* 616 * A list of all L1 tables 617 */ 618 static SLIST_HEAD(, l1_ttable) l1_list; 619 #endif /* ARM_MMU_EXTENDED */ 620 621 /* 622 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 623 * 624 * This is normally 16MB worth L2 page descriptors for any given pmap. 625 * Reference counts are maintained for L2 descriptors so they can be 626 * freed when empty. 627 */ 628 struct l2_bucket { 629 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 630 paddr_t l2b_pa; /* Physical address of same */ 631 u_short l2b_l1slot; /* This L2 table's L1 index */ 632 u_short l2b_occupancy; /* How many active descriptors */ 633 }; 634 635 struct l2_dtable { 636 /* The number of L2 page descriptors allocated to this l2_dtable */ 637 u_int l2_occupancy; 638 639 /* List of L2 page descriptors */ 640 struct l2_bucket l2_bucket[L2_BUCKET_SIZE]; 641 }; 642 643 /* 644 * Given an L1 table index, calculate the corresponding l2_dtable index 645 * and bucket index within the l2_dtable. 646 */ 647 #define L2_BUCKET_XSHIFT (L2_BUCKET_XLOG2 - L1_S_SHIFT) 648 #define L2_BUCKET_XFRAME (~(vaddr_t)0 << L2_BUCKET_XLOG2) 649 #define L2_BUCKET_IDX(l1slot) ((l1slot) >> L2_BUCKET_XSHIFT) 650 #define L2_IDX(l1slot) (L2_BUCKET_IDX(l1slot) >> L2_BUCKET_LOG2) 651 #define L2_BUCKET(l1slot) (L2_BUCKET_IDX(l1slot) & (L2_BUCKET_SIZE - 1)) 652 653 __CTASSERT(0x100000000ULL == ((uint64_t)L2_SIZE * L2_BUCKET_SIZE * L1_S_SIZE)); 654 __CTASSERT(L2_BUCKET_XFRAME == ~(L2_BUCKET_XSIZE-1)); 655 656 /* 657 * Given a virtual address, this macro returns the 658 * virtual address required to drop into the next L2 bucket. 659 */ 660 #define L2_NEXT_BUCKET_VA(va) (((va) & L2_BUCKET_XFRAME) + L2_BUCKET_XSIZE) 661 662 /* 663 * L2 allocation. 664 */ 665 #define pmap_alloc_l2_dtable() \ 666 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 667 #define pmap_free_l2_dtable(l2) \ 668 pool_cache_put(&pmap_l2dtable_cache, (l2)) 669 #define pmap_alloc_l2_ptp(pap) \ 670 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 671 PR_NOWAIT, (pap))) 672 673 /* 674 * We try to map the page tables write-through, if possible. However, not 675 * all CPUs have a write-through cache mode, so on those we have to sync 676 * the cache when we frob page tables. 677 * 678 * We try to evaluate this at compile time, if possible. However, it's 679 * not always possible to do that, hence this run-time var. 680 */ 681 int pmap_needs_pte_sync; 682 683 /* 684 * Real definition of pv_entry. 685 */ 686 struct pv_entry { 687 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 688 pmap_t pv_pmap; /* pmap where mapping lies */ 689 vaddr_t pv_va; /* virtual address for mapping */ 690 u_int pv_flags; /* flags */ 691 }; 692 693 /* 694 * Macros to determine if a mapping might be resident in the 695 * instruction/data cache and/or TLB 696 */ 697 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED) 698 /* 699 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 700 * there are no explicit accesses, so there may be always be TLB entries to 701 * flush. If we used ASIDs then this would not be a problem. 702 */ 703 #define PV_BEEN_EXECD(f) (((f) & PVF_EXEC) == PVF_EXEC) 704 #define PV_BEEN_REFD(f) (true) 705 #else 706 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 707 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 708 #endif 709 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 710 #define PV_IS_KENTRY_P(f) (((f) & PVF_KENTRY) != 0) 711 #define PV_IS_WRITE_P(f) (((f) & PVF_WRITE) != 0) 712 713 /* 714 * Local prototypes 715 */ 716 static bool pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t, size_t); 717 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 718 pt_entry_t **); 719 static bool pmap_is_current(pmap_t) __unused; 720 static bool pmap_is_cached(pmap_t); 721 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 722 pmap_t, vaddr_t, u_int); 723 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 724 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 725 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 726 u_int, u_int); 727 728 static void pmap_pinit(pmap_t); 729 static int pmap_pmap_ctor(void *, void *, int); 730 731 static void pmap_alloc_l1(pmap_t); 732 static void pmap_free_l1(pmap_t); 733 #ifndef ARM_MMU_EXTENDED 734 static void pmap_use_l1(pmap_t); 735 #endif 736 737 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 738 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 739 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 740 static int pmap_l2ptp_ctor(void *, void *, int); 741 static int pmap_l2dtable_ctor(void *, void *, int); 742 743 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 744 #ifdef PMAP_CACHE_VIVT 745 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 746 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 747 #endif 748 749 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 750 #ifdef PMAP_CACHE_VIVT 751 static bool pmap_clean_page(struct vm_page_md *, bool); 752 #endif 753 #ifdef PMAP_CACHE_VIPT 754 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 755 enum pmap_flush_op { 756 PMAP_FLUSH_PRIMARY, 757 PMAP_FLUSH_SECONDARY, 758 PMAP_CLEAN_PRIMARY 759 }; 760 #ifndef ARM_MMU_EXTENDED 761 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 762 #endif 763 #endif 764 static void pmap_page_remove(struct vm_page_md *, paddr_t); 765 static void pmap_pv_remove(paddr_t); 766 767 #ifndef ARM_MMU_EXTENDED 768 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 769 #endif 770 static vaddr_t kernel_pt_lookup(paddr_t); 771 772 773 /* 774 * Misc variables 775 */ 776 vaddr_t virtual_avail; 777 vaddr_t virtual_end; 778 vaddr_t pmap_curmaxkvaddr; 779 780 paddr_t avail_start; 781 paddr_t avail_end; 782 783 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 784 pv_addr_t kernelpages; 785 pv_addr_t kernel_l1pt; 786 pv_addr_t systempage; 787 788 /* Function to set the debug level of the pmap code */ 789 790 #ifdef PMAP_DEBUG 791 void 792 pmap_debug(int level) 793 { 794 pmap_debug_level = level; 795 printf("pmap_debug: level=%d\n", pmap_debug_level); 796 } 797 #endif /* PMAP_DEBUG */ 798 799 #ifdef PMAP_CACHE_VIPT 800 #define PMAP_VALIDATE_MD_PAGE(md) \ 801 KASSERTMSG(arm_cache_prefer_mask == 0 || (((md)->pvh_attrs & PVF_WRITE) == 0) == ((md)->urw_mappings + (md)->krw_mappings == 0), \ 802 "(md) %p: attrs=%#x urw=%u krw=%u", (md), \ 803 (md)->pvh_attrs, (md)->urw_mappings, (md)->krw_mappings); 804 #endif /* PMAP_CACHE_VIPT */ 805 /* 806 * A bunch of routines to conditionally flush the caches/TLB depending 807 * on whether the specified pmap actually needs to be flushed at any 808 * given time. 809 */ 810 static inline void 811 pmap_tlb_flush_SE(pmap_t pm, vaddr_t va, u_int flags) 812 { 813 #ifdef ARM_MMU_EXTENDED 814 pmap_tlb_invalidate_addr(pm, va); 815 #else 816 if (pm->pm_cstate.cs_tlb_id != 0) { 817 if (PV_BEEN_EXECD(flags)) { 818 cpu_tlb_flushID_SE(va); 819 } else if (PV_BEEN_REFD(flags)) { 820 cpu_tlb_flushD_SE(va); 821 } 822 } 823 #endif /* ARM_MMU_EXTENDED */ 824 } 825 826 #ifndef ARM_MMU_EXTENDED 827 static inline void 828 pmap_tlb_flushID(pmap_t pm) 829 { 830 if (pm->pm_cstate.cs_tlb_id) { 831 cpu_tlb_flushID(); 832 #if ARM_MMU_V7 == 0 833 /* 834 * Speculative loads by Cortex cores can cause TLB entries to 835 * be filled even if there are no explicit accesses, so there 836 * may be always be TLB entries to flush. If we used ASIDs 837 * then it would not be a problem. 838 * This is not true for other CPUs. 839 */ 840 pm->pm_cstate.cs_tlb = 0; 841 #endif /* ARM_MMU_V7 */ 842 } 843 } 844 845 static inline void 846 pmap_tlb_flushD(pmap_t pm) 847 { 848 if (pm->pm_cstate.cs_tlb_d) { 849 cpu_tlb_flushD(); 850 #if ARM_MMU_V7 == 0 851 /* 852 * Speculative loads by Cortex cores can cause TLB entries to 853 * be filled even if there are no explicit accesses, so there 854 * may be always be TLB entries to flush. If we used ASIDs 855 * then it would not be a problem. 856 * This is not true for other CPUs. 857 */ 858 pm->pm_cstate.cs_tlb_d = 0; 859 #endif /* ARM_MMU_V7 */ 860 } 861 } 862 #endif /* ARM_MMU_EXTENDED */ 863 864 #ifdef PMAP_CACHE_VIVT 865 static inline void 866 pmap_cache_wbinv_page(pmap_t pm, vaddr_t va, bool do_inv, u_int flags) 867 { 868 if (PV_BEEN_EXECD(flags) && pm->pm_cstate.cs_cache_id) { 869 cpu_idcache_wbinv_range(va, PAGE_SIZE); 870 } else if (PV_BEEN_REFD(flags) && pm->pm_cstate.cs_cache_d) { 871 if (do_inv) { 872 if (flags & PVF_WRITE) 873 cpu_dcache_wbinv_range(va, PAGE_SIZE); 874 else 875 cpu_dcache_inv_range(va, PAGE_SIZE); 876 } else if (flags & PVF_WRITE) { 877 cpu_dcache_wb_range(va, PAGE_SIZE); 878 } 879 } 880 } 881 882 static inline void 883 pmap_cache_wbinv_all(pmap_t pm, u_int flags) 884 { 885 if (PV_BEEN_EXECD(flags)) { 886 if (pm->pm_cstate.cs_cache_id) { 887 cpu_idcache_wbinv_all(); 888 pm->pm_cstate.cs_cache = 0; 889 } 890 } else if (pm->pm_cstate.cs_cache_d) { 891 cpu_dcache_wbinv_all(); 892 pm->pm_cstate.cs_cache_d = 0; 893 } 894 } 895 #endif /* PMAP_CACHE_VIVT */ 896 897 static inline uint8_t 898 pmap_domain(pmap_t pm) 899 { 900 #ifdef ARM_MMU_EXTENDED 901 return pm == pmap_kernel() ? PMAP_DOMAIN_KERNEL : PMAP_DOMAIN_USER; 902 #else 903 return pm->pm_domain; 904 #endif 905 } 906 907 static inline pd_entry_t * 908 pmap_l1_kva(pmap_t pm) 909 { 910 #ifdef ARM_MMU_EXTENDED 911 return pm->pm_l1; 912 #else 913 return pm->pm_l1->l1_kva; 914 #endif 915 } 916 917 static inline bool 918 pmap_is_current(pmap_t pm) 919 { 920 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 921 return true; 922 923 return false; 924 } 925 926 static inline bool 927 pmap_is_cached(pmap_t pm) 928 { 929 #ifdef ARM_MMU_EXTENDED 930 if (pm == pmap_kernel()) 931 return true; 932 #ifdef MULTIPROCESSOR 933 // Is this pmap active on any CPU? 934 if (!kcpuset_iszero(pm->pm_active)) 935 return true; 936 #else 937 struct pmap_tlb_info * const ti = cpu_tlb_info(curcpu()); 938 // Is this pmap active? 939 if (PMAP_PAI_ASIDVALID_P(PMAP_PAI(pm, ti), ti)) 940 return true; 941 #endif 942 #else 943 struct cpu_info * const ci = curcpu(); 944 if (pm == pmap_kernel() || ci->ci_pmap_lastuser == NULL 945 || ci->ci_pmap_lastuser == pm) 946 return true; 947 #endif /* ARM_MMU_EXTENDED */ 948 949 return false; 950 } 951 952 /* 953 * PTE_SYNC_CURRENT: 954 * 955 * Make sure the pte is written out to RAM. 956 * We need to do this for one of two cases: 957 * - We're dealing with the kernel pmap 958 * - There is no pmap active in the cache/tlb. 959 * - The specified pmap is 'active' in the cache/tlb. 960 */ 961 962 #ifdef PMAP_INCLUDE_PTE_SYNC 963 static inline void 964 pmap_pte_sync_current(pmap_t pm, pt_entry_t *ptep) 965 { 966 if (PMAP_NEEDS_PTE_SYNC && pmap_is_cached(pm)) 967 PTE_SYNC(ptep); 968 arm_dsb(); 969 } 970 971 # define PTE_SYNC_CURRENT(pm, ptep) pmap_pte_sync_current(pm, ptep) 972 #else 973 # define PTE_SYNC_CURRENT(pm, ptep) __nothing 974 #endif 975 976 /* 977 * main pv_entry manipulation functions: 978 * pmap_enter_pv: enter a mapping onto a vm_page list 979 * pmap_remove_pv: remove a mapping from a vm_page list 980 * 981 * NOTE: pmap_enter_pv expects to lock the pvh itself 982 * pmap_remove_pv expects the caller to lock the pvh before calling 983 */ 984 985 /* 986 * pmap_enter_pv: enter a mapping onto a vm_page lst 987 * 988 * => caller should hold the proper lock on pmap_main_lock 989 * => caller should have pmap locked 990 * => we will gain the lock on the vm_page and allocate the new pv_entry 991 * => caller should adjust ptp's wire_count before calling 992 * => caller should not adjust pmap's wire_count 993 */ 994 static void 995 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 996 vaddr_t va, u_int flags) 997 { 998 struct pv_entry **pvp; 999 1000 NPDEBUG(PDB_PVDUMP, 1001 printf("pmap_enter_pv: pm %p, md %p, flags 0x%x\n", pm, md, flags)); 1002 1003 pv->pv_pmap = pm; 1004 pv->pv_va = va; 1005 pv->pv_flags = flags; 1006 1007 pvp = &SLIST_FIRST(&md->pvh_list); 1008 #ifdef PMAP_CACHE_VIPT 1009 /* 1010 * Insert unmanaged entries, writeable first, at the head of 1011 * the pv list. 1012 */ 1013 if (__predict_true(!PV_IS_KENTRY_P(flags))) { 1014 while (*pvp != NULL && PV_IS_KENTRY_P((*pvp)->pv_flags)) 1015 pvp = &SLIST_NEXT(*pvp, pv_link); 1016 } 1017 if (!PV_IS_WRITE_P(flags)) { 1018 while (*pvp != NULL && PV_IS_WRITE_P((*pvp)->pv_flags)) 1019 pvp = &SLIST_NEXT(*pvp, pv_link); 1020 } 1021 #endif 1022 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 1023 *pvp = pv; /* ... locked list */ 1024 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1025 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1026 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 1027 md->pvh_attrs |= PVF_KMOD; 1028 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1029 md->pvh_attrs |= PVF_DIRTY; 1030 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1031 #endif 1032 if (pm == pmap_kernel()) { 1033 PMAPCOUNT(kernel_mappings); 1034 if (flags & PVF_WRITE) 1035 md->krw_mappings++; 1036 else 1037 md->kro_mappings++; 1038 } else { 1039 if (flags & PVF_WRITE) 1040 md->urw_mappings++; 1041 else 1042 md->uro_mappings++; 1043 } 1044 1045 #ifdef PMAP_CACHE_VIPT 1046 #ifndef ARM_MMU_EXTENDED 1047 /* 1048 * Even though pmap_vac_me_harder will set PVF_WRITE for us, 1049 * do it here as well to keep the mappings & KVF_WRITE consistent. 1050 */ 1051 if (arm_cache_prefer_mask != 0 && (flags & PVF_WRITE) != 0) { 1052 md->pvh_attrs |= PVF_WRITE; 1053 } 1054 #endif 1055 /* 1056 * If this is an exec mapping and its the first exec mapping 1057 * for this page, make sure to sync the I-cache. 1058 */ 1059 if (PV_IS_EXEC_P(flags)) { 1060 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 1061 pmap_syncicache_page(md, pa); 1062 PMAPCOUNT(exec_synced_map); 1063 } 1064 PMAPCOUNT(exec_mappings); 1065 } 1066 #endif 1067 1068 PMAPCOUNT(mappings); 1069 1070 if (pv->pv_flags & PVF_WIRED) 1071 ++pm->pm_stats.wired_count; 1072 } 1073 1074 /* 1075 * 1076 * pmap_find_pv: Find a pv entry 1077 * 1078 * => caller should hold lock on vm_page 1079 */ 1080 static inline struct pv_entry * 1081 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 1082 { 1083 struct pv_entry *pv; 1084 1085 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1086 if (pm == pv->pv_pmap && va == pv->pv_va) 1087 break; 1088 } 1089 1090 return (pv); 1091 } 1092 1093 /* 1094 * pmap_remove_pv: try to remove a mapping from a pv_list 1095 * 1096 * => caller should hold proper lock on pmap_main_lock 1097 * => pmap should be locked 1098 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1099 * => caller should adjust ptp's wire_count and free PTP if needed 1100 * => caller should NOT adjust pmap's wire_count 1101 * => we return the removed pv 1102 */ 1103 static struct pv_entry * 1104 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1105 { 1106 struct pv_entry *pv, **prevptr; 1107 1108 NPDEBUG(PDB_PVDUMP, 1109 printf("pmap_remove_pv: pm %p, md %p, va 0x%08lx\n", pm, md, va)); 1110 1111 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 1112 pv = *prevptr; 1113 1114 while (pv) { 1115 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 1116 NPDEBUG(PDB_PVDUMP, printf("pmap_remove_pv: pm %p, md " 1117 "%p, flags 0x%x\n", pm, md, pv->pv_flags)); 1118 if (pv->pv_flags & PVF_WIRED) { 1119 --pm->pm_stats.wired_count; 1120 } 1121 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 1122 if (pm == pmap_kernel()) { 1123 PMAPCOUNT(kernel_unmappings); 1124 if (pv->pv_flags & PVF_WRITE) 1125 md->krw_mappings--; 1126 else 1127 md->kro_mappings--; 1128 } else { 1129 if (pv->pv_flags & PVF_WRITE) 1130 md->urw_mappings--; 1131 else 1132 md->uro_mappings--; 1133 } 1134 1135 PMAPCOUNT(unmappings); 1136 #ifdef PMAP_CACHE_VIPT 1137 /* 1138 * If this page has had an exec mapping, then if 1139 * this was the last mapping, discard the contents, 1140 * otherwise sync the i-cache for this page. 1141 */ 1142 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1143 if (SLIST_EMPTY(&md->pvh_list)) { 1144 md->pvh_attrs &= ~PVF_EXEC; 1145 PMAPCOUNT(exec_discarded_unmap); 1146 } else if (pv->pv_flags & PVF_WRITE) { 1147 pmap_syncicache_page(md, pa); 1148 PMAPCOUNT(exec_synced_unmap); 1149 } 1150 } 1151 #endif /* PMAP_CACHE_VIPT */ 1152 break; 1153 } 1154 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1155 pv = *prevptr; /* advance */ 1156 } 1157 1158 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1159 /* 1160 * If we no longer have a WRITEABLE KENTRY at the head of list, 1161 * clear the KMOD attribute from the page. 1162 */ 1163 if (SLIST_FIRST(&md->pvh_list) == NULL 1164 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1165 md->pvh_attrs &= ~PVF_KMOD; 1166 1167 /* 1168 * If this was a writeable page and there are no more writeable 1169 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1170 * the contents to memory. 1171 */ 1172 if (arm_cache_prefer_mask != 0) { 1173 if (md->krw_mappings + md->urw_mappings == 0) 1174 md->pvh_attrs &= ~PVF_WRITE; 1175 PMAP_VALIDATE_MD_PAGE(md); 1176 } 1177 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1178 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1179 1180 /* return removed pv */ 1181 return pv; 1182 } 1183 1184 /* 1185 * 1186 * pmap_modify_pv: Update pv flags 1187 * 1188 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1189 * => caller should NOT adjust pmap's wire_count 1190 * => caller must call pmap_vac_me_harder() if writable status of a page 1191 * may have changed. 1192 * => we return the old flags 1193 * 1194 * Modify a physical-virtual mapping in the pv table 1195 */ 1196 static u_int 1197 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1198 u_int clr_mask, u_int set_mask) 1199 { 1200 struct pv_entry *npv; 1201 u_int flags, oflags; 1202 1203 KASSERT(!PV_IS_KENTRY_P(clr_mask)); 1204 KASSERT(!PV_IS_KENTRY_P(set_mask)); 1205 1206 if ((npv = pmap_find_pv(md, pm, va)) == NULL) 1207 return (0); 1208 1209 NPDEBUG(PDB_PVDUMP, 1210 printf("pmap_modify_pv: pm %p, md %p, clr 0x%x, set 0x%x, flags 0x%x\n", pm, md, clr_mask, set_mask, npv->pv_flags)); 1211 1212 /* 1213 * There is at least one VA mapping this page. 1214 */ 1215 1216 if (clr_mask & (PVF_REF | PVF_MOD)) { 1217 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1218 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1219 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1220 md->pvh_attrs |= PVF_DIRTY; 1221 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1222 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1223 } 1224 1225 oflags = npv->pv_flags; 1226 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1227 1228 if ((flags ^ oflags) & PVF_WIRED) { 1229 if (flags & PVF_WIRED) 1230 ++pm->pm_stats.wired_count; 1231 else 1232 --pm->pm_stats.wired_count; 1233 } 1234 1235 if ((flags ^ oflags) & PVF_WRITE) { 1236 if (pm == pmap_kernel()) { 1237 if (flags & PVF_WRITE) { 1238 md->krw_mappings++; 1239 md->kro_mappings--; 1240 } else { 1241 md->kro_mappings++; 1242 md->krw_mappings--; 1243 } 1244 } else { 1245 if (flags & PVF_WRITE) { 1246 md->urw_mappings++; 1247 md->uro_mappings--; 1248 } else { 1249 md->uro_mappings++; 1250 md->urw_mappings--; 1251 } 1252 } 1253 } 1254 #ifdef PMAP_CACHE_VIPT 1255 if (arm_cache_prefer_mask != 0) { 1256 if (md->urw_mappings + md->krw_mappings == 0) { 1257 md->pvh_attrs &= ~PVF_WRITE; 1258 } else { 1259 md->pvh_attrs |= PVF_WRITE; 1260 } 1261 } 1262 /* 1263 * We have two cases here: the first is from enter_pv (new exec 1264 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1265 * Since in latter, pmap_enter_pv won't do anything, we just have 1266 * to do what pmap_remove_pv would do. 1267 */ 1268 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1269 || (PV_IS_EXEC_P(md->pvh_attrs) 1270 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1271 pmap_syncicache_page(md, pa); 1272 PMAPCOUNT(exec_synced_remap); 1273 } 1274 #ifndef ARM_MMU_EXTENDED 1275 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1276 #endif /* !ARM_MMU_EXTENDED */ 1277 #endif /* PMAP_CACHE_VIPT */ 1278 1279 PMAPCOUNT(remappings); 1280 1281 return (oflags); 1282 } 1283 1284 /* 1285 * Allocate an L1 translation table for the specified pmap. 1286 * This is called at pmap creation time. 1287 */ 1288 static void 1289 pmap_alloc_l1(pmap_t pm) 1290 { 1291 #ifdef ARM_MMU_EXTENDED 1292 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1293 struct vm_page *pg; 1294 bool ok __diagused; 1295 for (;;) { 1296 #ifdef PMAP_NEED_ALLOC_POOLPAGE 1297 pg = arm_pmap_alloc_poolpage(UVM_PGA_ZERO); 1298 #else 1299 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 1300 #endif 1301 if (pg != NULL) 1302 break; 1303 uvm_wait("pmapl1alloc"); 1304 } 1305 pm->pm_l1_pa = VM_PAGE_TO_PHYS(pg); 1306 vaddr_t va = pmap_direct_mapped_phys(pm->pm_l1_pa, &ok, 0); 1307 KASSERT(ok); 1308 KASSERT(va >= KERNEL_BASE); 1309 1310 #else 1311 KASSERTMSG(kernel_map != NULL, "pm %p", pm); 1312 vaddr_t va = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 1313 UVM_KMF_WIRED|UVM_KMF_ZERO); 1314 KASSERT(va); 1315 pmap_extract(pmap_kernel(), va, &pm->pm_l1_pa); 1316 #endif 1317 pm->pm_l1 = (pd_entry_t *)va; 1318 PTE_SYNC_RANGE(pm->pm_l1, PAGE_SIZE / sizeof(pt_entry_t)); 1319 #else 1320 struct l1_ttable *l1; 1321 uint8_t domain; 1322 1323 /* 1324 * Remove the L1 at the head of the LRU list 1325 */ 1326 mutex_spin_enter(&l1_lru_lock); 1327 l1 = TAILQ_FIRST(&l1_lru_list); 1328 KDASSERT(l1 != NULL); 1329 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1330 1331 /* 1332 * Pick the first available domain number, and update 1333 * the link to the next number. 1334 */ 1335 domain = l1->l1_domain_first; 1336 l1->l1_domain_first = l1->l1_domain_free[domain]; 1337 1338 /* 1339 * If there are still free domain numbers in this L1, 1340 * put it back on the TAIL of the LRU list. 1341 */ 1342 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1343 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1344 1345 mutex_spin_exit(&l1_lru_lock); 1346 1347 /* 1348 * Fix up the relevant bits in the pmap structure 1349 */ 1350 pm->pm_l1 = l1; 1351 pm->pm_domain = domain + 1; 1352 #endif 1353 } 1354 1355 /* 1356 * Free an L1 translation table. 1357 * This is called at pmap destruction time. 1358 */ 1359 static void 1360 pmap_free_l1(pmap_t pm) 1361 { 1362 #ifdef ARM_MMU_EXTENDED 1363 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 1364 struct vm_page *pg = PHYS_TO_VM_PAGE(pm->pm_l1_pa); 1365 uvm_pagefree(pg); 1366 #else 1367 uvm_km_free(kernel_map, (vaddr_t)pm->pm_l1, PAGE_SIZE, UVM_KMF_WIRED); 1368 #endif 1369 pm->pm_l1 = NULL; 1370 pm->pm_l1_pa = 0; 1371 #else 1372 struct l1_ttable *l1 = pm->pm_l1; 1373 1374 mutex_spin_enter(&l1_lru_lock); 1375 1376 /* 1377 * If this L1 is currently on the LRU list, remove it. 1378 */ 1379 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1380 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1381 1382 /* 1383 * Free up the domain number which was allocated to the pmap 1384 */ 1385 l1->l1_domain_free[pmap_domain(pm) - 1] = l1->l1_domain_first; 1386 l1->l1_domain_first = pmap_domain(pm) - 1; 1387 l1->l1_domain_use_count--; 1388 1389 /* 1390 * The L1 now must have at least 1 free domain, so add 1391 * it back to the LRU list. If the use count is zero, 1392 * put it at the head of the list, otherwise it goes 1393 * to the tail. 1394 */ 1395 if (l1->l1_domain_use_count == 0) 1396 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1397 else 1398 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1399 1400 mutex_spin_exit(&l1_lru_lock); 1401 #endif /* ARM_MMU_EXTENDED */ 1402 } 1403 1404 #ifndef ARM_MMU_EXTENDED 1405 static inline void 1406 pmap_use_l1(pmap_t pm) 1407 { 1408 struct l1_ttable *l1; 1409 1410 /* 1411 * Do nothing if we're in interrupt context. 1412 * Access to an L1 by the kernel pmap must not affect 1413 * the LRU list. 1414 */ 1415 if (cpu_intr_p() || pm == pmap_kernel()) 1416 return; 1417 1418 l1 = pm->pm_l1; 1419 1420 /* 1421 * If the L1 is not currently on the LRU list, just return 1422 */ 1423 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1424 return; 1425 1426 mutex_spin_enter(&l1_lru_lock); 1427 1428 /* 1429 * Check the use count again, now that we've acquired the lock 1430 */ 1431 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1432 mutex_spin_exit(&l1_lru_lock); 1433 return; 1434 } 1435 1436 /* 1437 * Move the L1 to the back of the LRU list 1438 */ 1439 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1440 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1441 1442 mutex_spin_exit(&l1_lru_lock); 1443 } 1444 #endif /* !ARM_MMU_EXTENDED */ 1445 1446 /* 1447 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1448 * 1449 * Free an L2 descriptor table. 1450 */ 1451 static inline void 1452 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1453 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1454 #else 1455 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1456 #endif 1457 { 1458 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1459 /* 1460 * Note: With a write-back cache, we may need to sync this 1461 * L2 table before re-using it. 1462 * This is because it may have belonged to a non-current 1463 * pmap, in which case the cache syncs would have been 1464 * skipped for the pages that were being unmapped. If the 1465 * L2 table were then to be immediately re-allocated to 1466 * the *current* pmap, it may well contain stale mappings 1467 * which have not yet been cleared by a cache write-back 1468 * and so would still be visible to the mmu. 1469 */ 1470 if (need_sync) 1471 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1472 #endif /* PMAP_INCLUDE_PTE_SYNC && PMAP_CACHE_VIVT */ 1473 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1474 } 1475 1476 /* 1477 * Returns a pointer to the L2 bucket associated with the specified pmap 1478 * and VA, or NULL if no L2 bucket exists for the address. 1479 */ 1480 static inline struct l2_bucket * 1481 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1482 { 1483 const size_t l1slot = l1pte_index(va); 1484 struct l2_dtable *l2; 1485 struct l2_bucket *l2b; 1486 1487 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL || 1488 (l2b = &l2->l2_bucket[L2_BUCKET(l1slot)])->l2b_kva == NULL) 1489 return (NULL); 1490 1491 return (l2b); 1492 } 1493 1494 /* 1495 * Returns a pointer to the L2 bucket associated with the specified pmap 1496 * and VA. 1497 * 1498 * If no L2 bucket exists, perform the necessary allocations to put an L2 1499 * bucket/page table in place. 1500 * 1501 * Note that if a new L2 bucket/page was allocated, the caller *must* 1502 * increment the bucket occupancy counter appropriately *before* 1503 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1504 * the bucket/page in the meantime. 1505 */ 1506 static struct l2_bucket * 1507 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1508 { 1509 const size_t l1slot = l1pte_index(va); 1510 struct l2_dtable *l2; 1511 1512 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 1513 /* 1514 * No mapping at this address, as there is 1515 * no entry in the L1 table. 1516 * Need to allocate a new l2_dtable. 1517 */ 1518 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1519 return (NULL); 1520 1521 /* 1522 * Link it into the parent pmap 1523 */ 1524 pm->pm_l2[L2_IDX(l1slot)] = l2; 1525 } 1526 1527 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 1528 1529 /* 1530 * Fetch pointer to the L2 page table associated with the address. 1531 */ 1532 if (l2b->l2b_kva == NULL) { 1533 pt_entry_t *ptep; 1534 1535 /* 1536 * No L2 page table has been allocated. Chances are, this 1537 * is because we just allocated the l2_dtable, above. 1538 */ 1539 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_pa)) == NULL) { 1540 /* 1541 * Oops, no more L2 page tables available at this 1542 * time. We may need to deallocate the l2_dtable 1543 * if we allocated a new one above. 1544 */ 1545 if (l2->l2_occupancy == 0) { 1546 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1547 pmap_free_l2_dtable(l2); 1548 } 1549 return (NULL); 1550 } 1551 1552 l2->l2_occupancy++; 1553 l2b->l2b_kva = ptep; 1554 l2b->l2b_l1slot = l1slot; 1555 1556 #ifdef ARM_MMU_EXTENDED 1557 /* 1558 * We know there will be a mapping here, so simply 1559 * enter this PTP into the L1 now. 1560 */ 1561 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1562 pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 1563 | L1_C_DOM(pmap_domain(pm)); 1564 KASSERT(*pdep == 0); 1565 l1pte_setone(pdep, npde); 1566 PDE_SYNC(pdep); 1567 #endif 1568 } 1569 1570 return (l2b); 1571 } 1572 1573 /* 1574 * One or more mappings in the specified L2 descriptor table have just been 1575 * invalidated. 1576 * 1577 * Garbage collect the metadata and descriptor table itself if necessary. 1578 * 1579 * The pmap lock must be acquired when this is called (not necessary 1580 * for the kernel pmap). 1581 */ 1582 static void 1583 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1584 { 1585 KDASSERT(count <= l2b->l2b_occupancy); 1586 1587 /* 1588 * Update the bucket's reference count according to how many 1589 * PTEs the caller has just invalidated. 1590 */ 1591 l2b->l2b_occupancy -= count; 1592 1593 /* 1594 * Note: 1595 * 1596 * Level 2 page tables allocated to the kernel pmap are never freed 1597 * as that would require checking all Level 1 page tables and 1598 * removing any references to the Level 2 page table. See also the 1599 * comment elsewhere about never freeing bootstrap L2 descriptors. 1600 * 1601 * We make do with just invalidating the mapping in the L2 table. 1602 * 1603 * This isn't really a big deal in practice and, in fact, leads 1604 * to a performance win over time as we don't need to continually 1605 * alloc/free. 1606 */ 1607 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1608 return; 1609 1610 /* 1611 * There are no more valid mappings in this level 2 page table. 1612 * Go ahead and NULL-out the pointer in the bucket, then 1613 * free the page table. 1614 */ 1615 const size_t l1slot = l2b->l2b_l1slot; 1616 pt_entry_t * const ptep = l2b->l2b_kva; 1617 l2b->l2b_kva = NULL; 1618 1619 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1620 pd_entry_t pde __diagused = *pdep; 1621 1622 #ifdef ARM_MMU_EXTENDED 1623 /* 1624 * Invalidate the L1 slot. 1625 */ 1626 KASSERT((pde & L1_TYPE_MASK) == L1_TYPE_C); 1627 #else 1628 /* 1629 * If the L1 slot matches the pmap's domain number, then invalidate it. 1630 */ 1631 if ((pde & (L1_C_DOM_MASK|L1_TYPE_MASK)) 1632 == (L1_C_DOM(pmap_domain(pm))|L1_TYPE_C)) { 1633 #endif 1634 l1pte_setone(pdep, 0); 1635 PDE_SYNC(pdep); 1636 #ifndef ARM_MMU_EXTENDED 1637 } 1638 #endif 1639 1640 /* 1641 * Release the L2 descriptor table back to the pool cache. 1642 */ 1643 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1644 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_pa); 1645 #else 1646 pmap_free_l2_ptp(ptep, l2b->l2b_pa); 1647 #endif 1648 1649 /* 1650 * Update the reference count in the associated l2_dtable 1651 */ 1652 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 1653 if (--l2->l2_occupancy > 0) 1654 return; 1655 1656 /* 1657 * There are no more valid mappings in any of the Level 1 1658 * slots managed by this l2_dtable. Go ahead and NULL-out 1659 * the pointer in the parent pmap and free the l2_dtable. 1660 */ 1661 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1662 pmap_free_l2_dtable(l2); 1663 } 1664 1665 /* 1666 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1667 * structures. 1668 */ 1669 static int 1670 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1671 { 1672 #ifndef PMAP_INCLUDE_PTE_SYNC 1673 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1674 1675 /* 1676 * The mappings for these page tables were initially made using 1677 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1678 * mode will not be right for page table mappings. To avoid 1679 * polluting the pmap_kenter_pa() code with a special case for 1680 * page tables, we simply fix up the cache-mode here if it's not 1681 * correct. 1682 */ 1683 if (pte_l2_s_cache_mode != pte_l2_s_cache_mode_pt) { 1684 const struct l2_bucket * const l2b = 1685 pmap_get_l2_bucket(pmap_kernel(), va); 1686 KASSERTMSG(l2b != NULL, "%#lx", va); 1687 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 1688 const pt_entry_t opte = *ptep; 1689 1690 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1691 /* 1692 * Page tables must have the cache-mode set correctly. 1693 */ 1694 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 1695 | pte_l2_s_cache_mode_pt; 1696 l2pte_set(ptep, npte, opte); 1697 PTE_SYNC(ptep); 1698 cpu_tlb_flushD_SE(va); 1699 cpu_cpwait(); 1700 } 1701 } 1702 #endif 1703 1704 memset(v, 0, L2_TABLE_SIZE_REAL); 1705 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1706 return (0); 1707 } 1708 1709 static int 1710 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1711 { 1712 1713 memset(v, 0, sizeof(struct l2_dtable)); 1714 return (0); 1715 } 1716 1717 static int 1718 pmap_pmap_ctor(void *arg, void *v, int flags) 1719 { 1720 1721 memset(v, 0, sizeof(struct pmap)); 1722 return (0); 1723 } 1724 1725 static void 1726 pmap_pinit(pmap_t pm) 1727 { 1728 #ifndef ARM_HAS_VBAR 1729 struct l2_bucket *l2b; 1730 1731 if (vector_page < KERNEL_BASE) { 1732 /* 1733 * Map the vector page. 1734 */ 1735 pmap_enter(pm, vector_page, systempage.pv_pa, 1736 VM_PROT_READ | VM_PROT_EXECUTE, 1737 VM_PROT_READ | VM_PROT_EXECUTE | PMAP_WIRED); 1738 pmap_update(pm); 1739 1740 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 1741 l2b = pmap_get_l2_bucket(pm, vector_page); 1742 KASSERTMSG(l2b != NULL, "%#lx", vector_page); 1743 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 1744 L1_C_DOM(pmap_domain(pm)); 1745 } else 1746 pm->pm_pl1vec = NULL; 1747 #endif 1748 } 1749 1750 #ifdef PMAP_CACHE_VIVT 1751 /* 1752 * Since we have a virtually indexed cache, we may need to inhibit caching if 1753 * there is more than one mapping and at least one of them is writable. 1754 * Since we purge the cache on every context switch, we only need to check for 1755 * other mappings within the same pmap, or kernel_pmap. 1756 * This function is also called when a page is unmapped, to possibly reenable 1757 * caching on any remaining mappings. 1758 * 1759 * The code implements the following logic, where: 1760 * 1761 * KW = # of kernel read/write pages 1762 * KR = # of kernel read only pages 1763 * UW = # of user read/write pages 1764 * UR = # of user read only pages 1765 * 1766 * KC = kernel mapping is cacheable 1767 * UC = user mapping is cacheable 1768 * 1769 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1770 * +--------------------------------------------- 1771 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1772 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1773 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1774 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1775 */ 1776 1777 static const int pmap_vac_flags[4][4] = { 1778 {-1, 0, 0, PVF_KNC}, 1779 {0, 0, PVF_NC, PVF_NC}, 1780 {0, PVF_NC, PVF_NC, PVF_NC}, 1781 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1782 }; 1783 1784 static inline int 1785 pmap_get_vac_flags(const struct vm_page_md *md) 1786 { 1787 int kidx, uidx; 1788 1789 kidx = 0; 1790 if (md->kro_mappings || md->krw_mappings > 1) 1791 kidx |= 1; 1792 if (md->krw_mappings) 1793 kidx |= 2; 1794 1795 uidx = 0; 1796 if (md->uro_mappings || md->urw_mappings > 1) 1797 uidx |= 1; 1798 if (md->urw_mappings) 1799 uidx |= 2; 1800 1801 return (pmap_vac_flags[uidx][kidx]); 1802 } 1803 1804 static inline void 1805 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1806 { 1807 int nattr; 1808 1809 nattr = pmap_get_vac_flags(md); 1810 1811 if (nattr < 0) { 1812 md->pvh_attrs &= ~PVF_NC; 1813 return; 1814 } 1815 1816 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1817 return; 1818 1819 if (pm == pmap_kernel()) 1820 pmap_vac_me_kpmap(md, pa, pm, va); 1821 else 1822 pmap_vac_me_user(md, pa, pm, va); 1823 1824 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1825 } 1826 1827 static void 1828 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1829 { 1830 u_int u_cacheable, u_entries; 1831 struct pv_entry *pv; 1832 pmap_t last_pmap = pm; 1833 1834 /* 1835 * Pass one, see if there are both kernel and user pmaps for 1836 * this page. Calculate whether there are user-writable or 1837 * kernel-writable pages. 1838 */ 1839 u_cacheable = 0; 1840 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1841 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1842 u_cacheable++; 1843 } 1844 1845 u_entries = md->urw_mappings + md->uro_mappings; 1846 1847 /* 1848 * We know we have just been updating a kernel entry, so if 1849 * all user pages are already cacheable, then there is nothing 1850 * further to do. 1851 */ 1852 if (md->k_mappings == 0 && u_cacheable == u_entries) 1853 return; 1854 1855 if (u_entries) { 1856 /* 1857 * Scan over the list again, for each entry, if it 1858 * might not be set correctly, call pmap_vac_me_user 1859 * to recalculate the settings. 1860 */ 1861 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1862 /* 1863 * We know kernel mappings will get set 1864 * correctly in other calls. We also know 1865 * that if the pmap is the same as last_pmap 1866 * then we've just handled this entry. 1867 */ 1868 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1869 continue; 1870 1871 /* 1872 * If there are kernel entries and this page 1873 * is writable but non-cacheable, then we can 1874 * skip this entry also. 1875 */ 1876 if (md->k_mappings && 1877 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1878 (PVF_NC | PVF_WRITE)) 1879 continue; 1880 1881 /* 1882 * Similarly if there are no kernel-writable 1883 * entries and the page is already 1884 * read-only/cacheable. 1885 */ 1886 if (md->krw_mappings == 0 && 1887 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1888 continue; 1889 1890 /* 1891 * For some of the remaining cases, we know 1892 * that we must recalculate, but for others we 1893 * can't tell if they are correct or not, so 1894 * we recalculate anyway. 1895 */ 1896 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1897 } 1898 1899 if (md->k_mappings == 0) 1900 return; 1901 } 1902 1903 pmap_vac_me_user(md, pa, pm, va); 1904 } 1905 1906 static void 1907 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1908 { 1909 pmap_t kpmap = pmap_kernel(); 1910 struct pv_entry *pv, *npv = NULL; 1911 u_int entries = 0; 1912 u_int writable = 0; 1913 u_int cacheable_entries = 0; 1914 u_int kern_cacheable = 0; 1915 u_int other_writable = 0; 1916 1917 /* 1918 * Count mappings and writable mappings in this pmap. 1919 * Include kernel mappings as part of our own. 1920 * Keep a pointer to the first one. 1921 */ 1922 npv = NULL; 1923 KASSERT(pmap_page_locked_p(md)); 1924 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1925 /* Count mappings in the same pmap */ 1926 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1927 if (entries++ == 0) 1928 npv = pv; 1929 1930 /* Cacheable mappings */ 1931 if ((pv->pv_flags & PVF_NC) == 0) { 1932 cacheable_entries++; 1933 if (kpmap == pv->pv_pmap) 1934 kern_cacheable++; 1935 } 1936 1937 /* Writable mappings */ 1938 if (pv->pv_flags & PVF_WRITE) 1939 ++writable; 1940 } else if (pv->pv_flags & PVF_WRITE) 1941 other_writable = 1; 1942 } 1943 1944 /* 1945 * Enable or disable caching as necessary. 1946 * Note: the first entry might be part of the kernel pmap, 1947 * so we can't assume this is indicative of the state of the 1948 * other (maybe non-kpmap) entries. 1949 */ 1950 if ((entries > 1 && writable) || 1951 (entries > 0 && pm == kpmap && other_writable)) { 1952 if (cacheable_entries == 0) { 1953 return; 1954 } 1955 1956 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1957 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1958 (pv->pv_flags & PVF_NC)) 1959 continue; 1960 1961 pv->pv_flags |= PVF_NC; 1962 1963 struct l2_bucket * const l2b 1964 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1965 KASSERTMSG(l2b != NULL, "%#lx", va); 1966 pt_entry_t * const ptep 1967 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1968 const pt_entry_t opte = *ptep; 1969 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 1970 1971 if ((va != pv->pv_va || pm != pv->pv_pmap) 1972 && l2pte_valid_p(opte)) { 1973 pmap_cache_wbinv_page(pv->pv_pmap, pv->pv_va, 1974 true, pv->pv_flags); 1975 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1976 pv->pv_flags); 1977 } 1978 1979 l2pte_set(ptep, npte, opte); 1980 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1981 } 1982 cpu_cpwait(); 1983 } else if (entries > cacheable_entries) { 1984 /* 1985 * Turn cacheing back on for some pages. If it is a kernel 1986 * page, only do so if there are no other writable pages. 1987 */ 1988 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1989 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1990 (kpmap != pv->pv_pmap || other_writable))) 1991 continue; 1992 1993 pv->pv_flags &= ~PVF_NC; 1994 1995 struct l2_bucket * const l2b 1996 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1997 KASSERTMSG(l2b != NULL, "%#lx", va); 1998 pt_entry_t * const ptep 1999 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2000 const pt_entry_t opte = *ptep; 2001 pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 2002 | pte_l2_s_cache_mode; 2003 2004 if (l2pte_valid_p(opte)) { 2005 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 2006 pv->pv_flags); 2007 } 2008 2009 l2pte_set(ptep, npte, opte); 2010 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2011 } 2012 } 2013 } 2014 #endif 2015 2016 #ifdef PMAP_CACHE_VIPT 2017 static void 2018 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 2019 { 2020 #ifndef ARM_MMU_EXTENDED 2021 struct pv_entry *pv; 2022 vaddr_t tst_mask; 2023 bool bad_alias; 2024 const u_int 2025 rw_mappings = md->urw_mappings + md->krw_mappings, 2026 ro_mappings = md->uro_mappings + md->kro_mappings; 2027 2028 /* do we need to do anything? */ 2029 if (arm_cache_prefer_mask == 0) 2030 return; 2031 2032 NPDEBUG(PDB_VAC, printf("pmap_vac_me_harder: md=%p, pmap=%p va=%08lx\n", 2033 md, pm, va)); 2034 2035 KASSERT(!va || pm); 2036 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2037 2038 /* Already a conflict? */ 2039 if (__predict_false(md->pvh_attrs & PVF_NC)) { 2040 /* just an add, things are already non-cached */ 2041 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 2042 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2043 bad_alias = false; 2044 if (va) { 2045 PMAPCOUNT(vac_color_none); 2046 bad_alias = true; 2047 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2048 goto fixup; 2049 } 2050 pv = SLIST_FIRST(&md->pvh_list); 2051 /* the list can't be empty because it would be cachable */ 2052 if (md->pvh_attrs & PVF_KMPAGE) { 2053 tst_mask = md->pvh_attrs; 2054 } else { 2055 KASSERT(pv); 2056 tst_mask = pv->pv_va; 2057 pv = SLIST_NEXT(pv, pv_link); 2058 } 2059 /* 2060 * Only check for a bad alias if we have writable mappings. 2061 */ 2062 tst_mask &= arm_cache_prefer_mask; 2063 if (rw_mappings > 0) { 2064 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 2065 /* if there's a bad alias, stop checking. */ 2066 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 2067 bad_alias = true; 2068 } 2069 md->pvh_attrs |= PVF_WRITE; 2070 if (!bad_alias) 2071 md->pvh_attrs |= PVF_DIRTY; 2072 } else { 2073 /* 2074 * We have only read-only mappings. Let's see if there 2075 * are multiple colors in use or if we mapped a KMPAGE. 2076 * If the latter, we have a bad alias. If the former, 2077 * we need to remember that. 2078 */ 2079 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 2080 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 2081 if (md->pvh_attrs & PVF_KMPAGE) 2082 bad_alias = true; 2083 break; 2084 } 2085 } 2086 md->pvh_attrs &= ~PVF_WRITE; 2087 /* 2088 * No KMPAGE and we exited early, so we must have 2089 * multiple color mappings. 2090 */ 2091 if (!bad_alias && pv != NULL) 2092 md->pvh_attrs |= PVF_MULTCLR; 2093 } 2094 2095 /* If no conflicting colors, set everything back to cached */ 2096 if (!bad_alias) { 2097 #ifdef DEBUG 2098 if ((md->pvh_attrs & PVF_WRITE) 2099 || ro_mappings < 2) { 2100 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2101 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2102 } 2103 #endif 2104 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 2105 md->pvh_attrs |= tst_mask | PVF_COLORED; 2106 /* 2107 * Restore DIRTY bit if page is modified 2108 */ 2109 if (md->pvh_attrs & PVF_DMOD) 2110 md->pvh_attrs |= PVF_DIRTY; 2111 PMAPCOUNT(vac_color_restore); 2112 } else { 2113 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2114 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2115 } 2116 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2117 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2118 } else if (!va) { 2119 KASSERT(pmap_is_page_colored_p(md)); 2120 KASSERT(!(md->pvh_attrs & PVF_WRITE) 2121 || (md->pvh_attrs & PVF_DIRTY)); 2122 if (rw_mappings == 0) { 2123 md->pvh_attrs &= ~PVF_WRITE; 2124 if (ro_mappings == 1 2125 && (md->pvh_attrs & PVF_MULTCLR)) { 2126 /* 2127 * If this is the last readonly mapping 2128 * but it doesn't match the current color 2129 * for the page, change the current color 2130 * to match this last readonly mapping. 2131 */ 2132 pv = SLIST_FIRST(&md->pvh_list); 2133 tst_mask = (md->pvh_attrs ^ pv->pv_va) 2134 & arm_cache_prefer_mask; 2135 if (tst_mask) { 2136 md->pvh_attrs ^= tst_mask; 2137 PMAPCOUNT(vac_color_change); 2138 } 2139 } 2140 } 2141 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2142 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2143 return; 2144 } else if (!pmap_is_page_colored_p(md)) { 2145 /* not colored so we just use its color */ 2146 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 2147 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2148 PMAPCOUNT(vac_color_new); 2149 md->pvh_attrs &= PAGE_SIZE - 1; 2150 md->pvh_attrs |= PVF_COLORED 2151 | (va & arm_cache_prefer_mask) 2152 | (rw_mappings > 0 ? PVF_WRITE : 0); 2153 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2154 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2155 return; 2156 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 2157 bad_alias = false; 2158 if (rw_mappings > 0) { 2159 /* 2160 * We now have writeable mappings and if we have 2161 * readonly mappings in more than once color, we have 2162 * an aliasing problem. Regardless mark the page as 2163 * writeable. 2164 */ 2165 if (md->pvh_attrs & PVF_MULTCLR) { 2166 if (ro_mappings < 2) { 2167 /* 2168 * If we only have less than two 2169 * read-only mappings, just flush the 2170 * non-primary colors from the cache. 2171 */ 2172 pmap_flush_page(md, pa, 2173 PMAP_FLUSH_SECONDARY); 2174 } else { 2175 bad_alias = true; 2176 } 2177 } 2178 md->pvh_attrs |= PVF_WRITE; 2179 } 2180 /* If no conflicting colors, set everything back to cached */ 2181 if (!bad_alias) { 2182 #ifdef DEBUG 2183 if (rw_mappings > 0 2184 || (md->pvh_attrs & PMAP_KMPAGE)) { 2185 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 2186 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2187 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2188 } 2189 #endif 2190 if (SLIST_EMPTY(&md->pvh_list)) 2191 PMAPCOUNT(vac_color_reuse); 2192 else 2193 PMAPCOUNT(vac_color_ok); 2194 2195 /* matching color, just return */ 2196 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2197 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2198 return; 2199 } 2200 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2201 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2202 2203 /* color conflict. evict from cache. */ 2204 2205 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2206 md->pvh_attrs &= ~PVF_COLORED; 2207 md->pvh_attrs |= PVF_NC; 2208 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2209 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2210 PMAPCOUNT(vac_color_erase); 2211 } else if (rw_mappings == 0 2212 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2213 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2214 2215 /* 2216 * If the page has dirty cache lines, clean it. 2217 */ 2218 if (md->pvh_attrs & PVF_DIRTY) 2219 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2220 2221 /* 2222 * If this is the first remapping (we know that there are no 2223 * writeable mappings), then this is a simple color change. 2224 * Otherwise this is a seconary r/o mapping, which means 2225 * we don't have to do anything. 2226 */ 2227 if (ro_mappings == 1) { 2228 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2229 md->pvh_attrs &= PAGE_SIZE - 1; 2230 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2231 PMAPCOUNT(vac_color_change); 2232 } else { 2233 PMAPCOUNT(vac_color_blind); 2234 } 2235 md->pvh_attrs |= PVF_MULTCLR; 2236 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2237 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2238 return; 2239 } else { 2240 if (rw_mappings > 0) 2241 md->pvh_attrs |= PVF_WRITE; 2242 2243 /* color conflict. evict from cache. */ 2244 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2245 2246 /* the list can't be empty because this was a enter/modify */ 2247 pv = SLIST_FIRST(&md->pvh_list); 2248 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2249 KASSERT(pv); 2250 /* 2251 * If there's only one mapped page, change color to the 2252 * page's new color and return. Restore the DIRTY bit 2253 * that was erased by pmap_flush_page. 2254 */ 2255 if (SLIST_NEXT(pv, pv_link) == NULL) { 2256 md->pvh_attrs &= PAGE_SIZE - 1; 2257 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2258 if (md->pvh_attrs & PVF_DMOD) 2259 md->pvh_attrs |= PVF_DIRTY; 2260 PMAPCOUNT(vac_color_change); 2261 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2262 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2263 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2264 return; 2265 } 2266 } 2267 bad_alias = true; 2268 md->pvh_attrs &= ~PVF_COLORED; 2269 md->pvh_attrs |= PVF_NC; 2270 PMAPCOUNT(vac_color_erase); 2271 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2272 } 2273 2274 fixup: 2275 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2276 2277 /* 2278 * Turn cacheing on/off for all pages. 2279 */ 2280 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2281 struct l2_bucket * const l2b = pmap_get_l2_bucket(pv->pv_pmap, 2282 pv->pv_va); 2283 KASSERTMSG(l2b != NULL, "%#lx", va); 2284 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2285 const pt_entry_t opte = *ptep; 2286 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 2287 if (bad_alias) { 2288 pv->pv_flags |= PVF_NC; 2289 } else { 2290 pv->pv_flags &= ~PVF_NC; 2291 npte |= pte_l2_s_cache_mode; 2292 } 2293 2294 if (opte == npte) /* only update is there's a change */ 2295 continue; 2296 2297 if (l2pte_valid_p(opte)) { 2298 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, pv->pv_flags); 2299 } 2300 2301 l2pte_set(ptep, npte, opte); 2302 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2303 } 2304 #endif /* !ARM_MMU_EXTENDED */ 2305 } 2306 #endif /* PMAP_CACHE_VIPT */ 2307 2308 2309 /* 2310 * Modify pte bits for all ptes corresponding to the given physical address. 2311 * We use `maskbits' rather than `clearbits' because we're always passing 2312 * constants and the latter would require an extra inversion at run-time. 2313 */ 2314 static void 2315 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2316 { 2317 struct pv_entry *pv; 2318 #ifdef PMAP_CACHE_VIPT 2319 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2320 bool need_syncicache = false; 2321 #ifdef ARM_MMU_EXTENDED 2322 const u_int execbits = (maskbits & PVF_EXEC) ? L2_XS_XN : 0; 2323 #else 2324 const u_int execbits = 0; 2325 bool need_vac_me_harder = false; 2326 #endif 2327 #else 2328 const u_int execbits = 0; 2329 #endif 2330 2331 NPDEBUG(PDB_BITS, 2332 printf("pmap_clearbit: md %p mask 0x%x\n", 2333 md, maskbits)); 2334 2335 #ifdef PMAP_CACHE_VIPT 2336 /* 2337 * If we might want to sync the I-cache and we've modified it, 2338 * then we know we definitely need to sync or discard it. 2339 */ 2340 if (want_syncicache) { 2341 if (md->pvh_attrs & PVF_MOD) { 2342 need_syncicache = true; 2343 } 2344 } 2345 #endif 2346 KASSERT(pmap_page_locked_p(md)); 2347 2348 /* 2349 * Clear saved attributes (modify, reference) 2350 */ 2351 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2352 2353 if (SLIST_EMPTY(&md->pvh_list)) { 2354 #if defined(PMAP_CACHE_VIPT) 2355 if (need_syncicache) { 2356 /* 2357 * No one has it mapped, so just discard it. The next 2358 * exec remapping will cause it to be synced. 2359 */ 2360 md->pvh_attrs &= ~PVF_EXEC; 2361 PMAPCOUNT(exec_discarded_clearbit); 2362 } 2363 #endif 2364 return; 2365 } 2366 2367 /* 2368 * Loop over all current mappings setting/clearing as appropos 2369 */ 2370 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2371 pmap_t pm = pv->pv_pmap; 2372 const vaddr_t va = pv->pv_va; 2373 const u_int oflags = pv->pv_flags; 2374 #ifndef ARM_MMU_EXTENDED 2375 /* 2376 * Kernel entries are unmanaged and as such not to be changed. 2377 */ 2378 if (PV_IS_KENTRY_P(oflags)) 2379 continue; 2380 #endif 2381 pv->pv_flags &= ~maskbits; 2382 2383 pmap_release_page_lock(md); 2384 pmap_acquire_pmap_lock(pm); 2385 2386 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, va); 2387 if (l2b == NULL) { 2388 pmap_release_pmap_lock(pm); 2389 pmap_acquire_page_lock(md); 2390 continue; 2391 } 2392 KASSERTMSG(l2b != NULL, "%#lx", va); 2393 2394 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 2395 const pt_entry_t opte = *ptep; 2396 pt_entry_t npte = opte | execbits; 2397 2398 #ifdef ARM_MMU_EXTENDED 2399 KASSERT((opte & L2_XS_nG) == (pm == pmap_kernel() ? 0 : L2_XS_nG)); 2400 #endif 2401 2402 NPDEBUG(PDB_BITS, 2403 printf( "%s: pv %p, pm %p, va 0x%08lx, flag 0x%x\n", 2404 __func__, pv, pm, va, oflags)); 2405 2406 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2407 #ifdef PMAP_CACHE_VIVT 2408 if ((oflags & PVF_NC)) { 2409 /* 2410 * Entry is not cacheable: 2411 * 2412 * Don't turn caching on again if this is a 2413 * modified emulation. This would be 2414 * inconsitent with the settings created by 2415 * pmap_vac_me_harder(). Otherwise, it's safe 2416 * to re-enable cacheing. 2417 * 2418 * There's no need to call pmap_vac_me_harder() 2419 * here: all pages are losing their write 2420 * permission. 2421 */ 2422 if (maskbits & PVF_WRITE) { 2423 npte |= pte_l2_s_cache_mode; 2424 pv->pv_flags &= ~PVF_NC; 2425 } 2426 } else if (l2pte_writable_p(opte)) { 2427 /* 2428 * Entry is writable/cacheable: check if pmap 2429 * is current if it is flush it, otherwise it 2430 * won't be in the cache 2431 */ 2432 pmap_cache_wbinv_page(pm, va, 2433 (maskbits & PVF_REF) != 0, 2434 oflags|PVF_WRITE); 2435 } 2436 #endif 2437 2438 /* make the pte read only */ 2439 npte = l2pte_set_readonly(npte); 2440 2441 pmap_acquire_page_lock(md); 2442 #ifdef MULTIPROCESSOR 2443 pv = pmap_find_pv(md, pm, va); 2444 #endif 2445 if (pv != NULL && (maskbits & oflags & PVF_WRITE)) { 2446 /* 2447 * Keep alias accounting up to date 2448 */ 2449 if (pm == pmap_kernel()) { 2450 md->krw_mappings--; 2451 md->kro_mappings++; 2452 } else { 2453 md->urw_mappings--; 2454 md->uro_mappings++; 2455 } 2456 #ifdef PMAP_CACHE_VIPT 2457 if (arm_cache_prefer_mask != 0) { 2458 if (md->urw_mappings + md->krw_mappings == 0) { 2459 md->pvh_attrs &= ~PVF_WRITE; 2460 } else { 2461 PMAP_VALIDATE_MD_PAGE(md); 2462 } 2463 } 2464 if (want_syncicache) 2465 need_syncicache = true; 2466 #ifndef ARM_MMU_EXTENDED 2467 need_vac_me_harder = true; 2468 #endif 2469 #endif /* PMAP_CACHE_VIPT */ 2470 } 2471 pmap_release_page_lock(md); 2472 } 2473 2474 if (maskbits & PVF_REF) { 2475 if (true 2476 #ifndef ARM_MMU_EXTENDED 2477 && (oflags & PVF_NC) == 0 2478 #endif 2479 && (maskbits & (PVF_WRITE|PVF_MOD)) == 0 2480 && l2pte_valid_p(npte)) { 2481 #ifdef PMAP_CACHE_VIVT 2482 /* 2483 * Check npte here; we may have already 2484 * done the wbinv above, and the validity 2485 * of the PTE is the same for opte and 2486 * npte. 2487 */ 2488 pmap_cache_wbinv_page(pm, va, true, oflags); 2489 #endif 2490 } 2491 2492 /* 2493 * Make the PTE invalid so that we will take a 2494 * page fault the next time the mapping is 2495 * referenced. 2496 */ 2497 npte &= ~L2_TYPE_MASK; 2498 npte |= L2_TYPE_INV; 2499 } 2500 2501 if (npte != opte) { 2502 l2pte_reset(ptep); 2503 PTE_SYNC(ptep); 2504 2505 /* Flush the TLB entry if a current pmap. */ 2506 pmap_tlb_flush_SE(pm, va, oflags); 2507 2508 l2pte_set(ptep, npte, 0); 2509 PTE_SYNC(ptep); 2510 } 2511 2512 pmap_release_pmap_lock(pm); 2513 pmap_acquire_page_lock(md); 2514 2515 NPDEBUG(PDB_BITS, 2516 printf("pmap_clearbit: pm %p va 0x%lx opte 0x%08x npte 0x%08x\n", 2517 pm, va, opte, npte)); 2518 } 2519 2520 #if defined(PMAP_CACHE_VIPT) 2521 /* 2522 * If we need to sync the I-cache and we haven't done it yet, do it. 2523 */ 2524 if (need_syncicache) { 2525 pmap_release_page_lock(md); 2526 pmap_syncicache_page(md, pa); 2527 pmap_acquire_page_lock(md); 2528 PMAPCOUNT(exec_synced_clearbit); 2529 } 2530 #ifndef ARM_MMU_EXTENDED 2531 /* 2532 * If we are changing this to read-only, we need to call vac_me_harder 2533 * so we can change all the read-only pages to cacheable. We pretend 2534 * this as a page deletion. 2535 */ 2536 if (need_vac_me_harder) { 2537 if (md->pvh_attrs & PVF_NC) 2538 pmap_vac_me_harder(md, pa, NULL, 0); 2539 } 2540 #endif /* !ARM_MMU_EXTENDED */ 2541 #endif /* PMAP_CACHE_VIPT */ 2542 } 2543 2544 /* 2545 * pmap_clean_page() 2546 * 2547 * This is a local function used to work out the best strategy to clean 2548 * a single page referenced by its entry in the PV table. It's used by 2549 * pmap_copy_page, pmap_zero_page and maybe some others later on. 2550 * 2551 * Its policy is effectively: 2552 * o If there are no mappings, we don't bother doing anything with the cache. 2553 * o If there is one mapping, we clean just that page. 2554 * o If there are multiple mappings, we clean the entire cache. 2555 * 2556 * So that some functions can be further optimised, it returns 0 if it didn't 2557 * clean the entire cache, or 1 if it did. 2558 * 2559 * XXX One bug in this routine is that if the pv_entry has a single page 2560 * mapped at 0x00000000 a whole cache clean will be performed rather than 2561 * just the 1 page. Since this should not occur in everyday use and if it does 2562 * it will just result in not the most efficient clean for the page. 2563 */ 2564 #ifdef PMAP_CACHE_VIVT 2565 static bool 2566 pmap_clean_page(struct vm_page_md *md, bool is_src) 2567 { 2568 struct pv_entry *pv; 2569 pmap_t pm_to_clean = NULL; 2570 bool cache_needs_cleaning = false; 2571 vaddr_t page_to_clean = 0; 2572 u_int flags = 0; 2573 2574 /* 2575 * Since we flush the cache each time we change to a different 2576 * user vmspace, we only need to flush the page if it is in the 2577 * current pmap. 2578 */ 2579 KASSERT(pmap_page_locked_p(md)); 2580 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2581 if (pmap_is_current(pv->pv_pmap)) { 2582 flags |= pv->pv_flags; 2583 /* 2584 * The page is mapped non-cacheable in 2585 * this map. No need to flush the cache. 2586 */ 2587 if (pv->pv_flags & PVF_NC) { 2588 #ifdef DIAGNOSTIC 2589 KASSERT(!cache_needs_cleaning); 2590 #endif 2591 break; 2592 } else if (is_src && (pv->pv_flags & PVF_WRITE) == 0) 2593 continue; 2594 if (cache_needs_cleaning) { 2595 page_to_clean = 0; 2596 break; 2597 } else { 2598 page_to_clean = pv->pv_va; 2599 pm_to_clean = pv->pv_pmap; 2600 } 2601 cache_needs_cleaning = true; 2602 } 2603 } 2604 2605 if (page_to_clean) { 2606 pmap_cache_wbinv_page(pm_to_clean, page_to_clean, 2607 !is_src, flags | PVF_REF); 2608 } else if (cache_needs_cleaning) { 2609 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2610 2611 pmap_cache_wbinv_all(pm, flags); 2612 return true; 2613 } 2614 return false; 2615 } 2616 #endif 2617 2618 #ifdef PMAP_CACHE_VIPT 2619 /* 2620 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2621 * right cache alias to make sure we flush the right stuff. 2622 */ 2623 void 2624 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2625 { 2626 pmap_t kpm = pmap_kernel(); 2627 const size_t way_size = arm_pcache.icache_type == CACHE_TYPE_PIPT 2628 ? PAGE_SIZE 2629 : arm_pcache.icache_way_size; 2630 2631 NPDEBUG(PDB_EXEC, printf("pmap_syncicache_page: md=%p (attrs=%#x)\n", 2632 md, md->pvh_attrs)); 2633 /* 2634 * No need to clean the page if it's non-cached. 2635 */ 2636 #ifndef ARM_MMU_EXTENDED 2637 if (md->pvh_attrs & PVF_NC) 2638 return; 2639 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2640 #endif 2641 2642 pt_entry_t * const ptep = cpu_cdst_pte(0); 2643 const vaddr_t dstp = cpu_cdstp(0); 2644 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 2645 if (way_size <= PAGE_SIZE) { 2646 bool ok = false; 2647 vaddr_t vdstp = pmap_direct_mapped_phys(pa, &ok, dstp); 2648 if (ok) { 2649 cpu_icache_sync_range(vdstp, way_size); 2650 return; 2651 } 2652 } 2653 #endif 2654 2655 /* 2656 * We don't worry about the color of the exec page, we map the 2657 * same page to pages in the way and then do the icache_sync on 2658 * the entire way making sure we are cleaned. 2659 */ 2660 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 2661 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE); 2662 2663 for (size_t i = 0, j = 0; i < way_size; 2664 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2665 l2pte_reset(ptep + j); 2666 PTE_SYNC(ptep + j); 2667 2668 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2669 /* 2670 * Set up a PTE with to flush these cache lines. 2671 */ 2672 l2pte_set(ptep + j, npte, 0); 2673 } 2674 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2675 2676 /* 2677 * Flush it. 2678 */ 2679 cpu_icache_sync_range(dstp, way_size); 2680 2681 for (size_t i = 0, j = 0; i < way_size; 2682 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2683 /* 2684 * Unmap the page(s). 2685 */ 2686 l2pte_reset(ptep + j); 2687 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2688 } 2689 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2690 2691 md->pvh_attrs |= PVF_EXEC; 2692 PMAPCOUNT(exec_synced); 2693 } 2694 2695 #ifndef ARM_MMU_EXTENDED 2696 void 2697 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2698 { 2699 vsize_t va_offset, end_va; 2700 bool wbinv_p; 2701 2702 if (arm_cache_prefer_mask == 0) 2703 return; 2704 2705 switch (flush) { 2706 case PMAP_FLUSH_PRIMARY: 2707 if (md->pvh_attrs & PVF_MULTCLR) { 2708 va_offset = 0; 2709 end_va = arm_cache_prefer_mask; 2710 md->pvh_attrs &= ~PVF_MULTCLR; 2711 PMAPCOUNT(vac_flush_lots); 2712 } else { 2713 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2714 end_va = va_offset; 2715 PMAPCOUNT(vac_flush_one); 2716 } 2717 /* 2718 * Mark that the page is no longer dirty. 2719 */ 2720 md->pvh_attrs &= ~PVF_DIRTY; 2721 wbinv_p = true; 2722 break; 2723 case PMAP_FLUSH_SECONDARY: 2724 va_offset = 0; 2725 end_va = arm_cache_prefer_mask; 2726 wbinv_p = true; 2727 md->pvh_attrs &= ~PVF_MULTCLR; 2728 PMAPCOUNT(vac_flush_lots); 2729 break; 2730 case PMAP_CLEAN_PRIMARY: 2731 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2732 end_va = va_offset; 2733 wbinv_p = false; 2734 /* 2735 * Mark that the page is no longer dirty. 2736 */ 2737 if ((md->pvh_attrs & PVF_DMOD) == 0) 2738 md->pvh_attrs &= ~PVF_DIRTY; 2739 PMAPCOUNT(vac_clean_one); 2740 break; 2741 default: 2742 return; 2743 } 2744 2745 KASSERT(!(md->pvh_attrs & PVF_NC)); 2746 2747 NPDEBUG(PDB_VAC, printf("pmap_flush_page: md=%p (attrs=%#x)\n", 2748 md, md->pvh_attrs)); 2749 2750 const size_t scache_line_size = arm_scache.dcache_line_size; 2751 2752 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2753 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 2754 const vaddr_t dstp = cpu_cdstp(va_offset); 2755 const pt_entry_t opte = *ptep; 2756 2757 if (flush == PMAP_FLUSH_SECONDARY 2758 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2759 continue; 2760 2761 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2762 /* 2763 * Set up a PTE with the right coloring to flush 2764 * existing cache entries. 2765 */ 2766 const pt_entry_t npte = L2_S_PROTO 2767 | pa 2768 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2769 | pte_l2_s_cache_mode; 2770 l2pte_set(ptep, npte, opte); 2771 PTE_SYNC(ptep); 2772 2773 /* 2774 * Flush it. Make sure to flush secondary cache too since 2775 * bus_dma will ignore uncached pages. 2776 */ 2777 if (scache_line_size != 0) { 2778 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2779 if (wbinv_p) { 2780 cpu_sdcache_wbinv_range(dstp, pa, PAGE_SIZE); 2781 cpu_dcache_inv_range(dstp, PAGE_SIZE); 2782 } else { 2783 cpu_sdcache_wb_range(dstp, pa, PAGE_SIZE); 2784 } 2785 } else { 2786 if (wbinv_p) { 2787 cpu_dcache_wbinv_range(dstp, PAGE_SIZE); 2788 } else { 2789 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2790 } 2791 } 2792 2793 /* 2794 * Restore the page table entry since we might have interrupted 2795 * pmap_zero_page or pmap_copy_page which was already using 2796 * this pte. 2797 */ 2798 if (opte) { 2799 l2pte_set(ptep, opte, npte); 2800 } else { 2801 l2pte_reset(ptep); 2802 } 2803 PTE_SYNC(ptep); 2804 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2805 } 2806 } 2807 #endif /* ARM_MMU_EXTENDED */ 2808 #endif /* PMAP_CACHE_VIPT */ 2809 2810 /* 2811 * Routine: pmap_page_remove 2812 * Function: 2813 * Removes this physical page from 2814 * all physical maps in which it resides. 2815 * Reflects back modify bits to the pager. 2816 */ 2817 static void 2818 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2819 { 2820 struct l2_bucket *l2b; 2821 struct pv_entry *pv; 2822 pt_entry_t *ptep; 2823 #ifndef ARM_MMU_EXTENDED 2824 bool flush = false; 2825 #endif 2826 u_int flags = 0; 2827 2828 NPDEBUG(PDB_FOLLOW, 2829 printf("pmap_page_remove: md %p (0x%08lx)\n", md, 2830 pa)); 2831 2832 struct pv_entry **pvp = &SLIST_FIRST(&md->pvh_list); 2833 pmap_acquire_page_lock(md); 2834 if (*pvp == NULL) { 2835 #ifdef PMAP_CACHE_VIPT 2836 /* 2837 * We *know* the page contents are about to be replaced. 2838 * Discard the exec contents 2839 */ 2840 if (PV_IS_EXEC_P(md->pvh_attrs)) 2841 PMAPCOUNT(exec_discarded_page_protect); 2842 md->pvh_attrs &= ~PVF_EXEC; 2843 PMAP_VALIDATE_MD_PAGE(md); 2844 #endif 2845 pmap_release_page_lock(md); 2846 return; 2847 } 2848 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2849 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2850 #endif 2851 2852 /* 2853 * Clear alias counts 2854 */ 2855 #ifdef PMAP_CACHE_VIVT 2856 md->k_mappings = 0; 2857 #endif 2858 md->urw_mappings = md->uro_mappings = 0; 2859 2860 #ifdef PMAP_CACHE_VIVT 2861 pmap_clean_page(md, false); 2862 #endif 2863 2864 while ((pv = *pvp) != NULL) { 2865 pmap_t pm = pv->pv_pmap; 2866 #ifndef ARM_MMU_EXTENDED 2867 if (flush == false && pmap_is_current(pm)) 2868 flush = true; 2869 #endif 2870 2871 if (pm == pmap_kernel()) { 2872 #ifdef PMAP_CACHE_VIPT 2873 /* 2874 * If this was unmanaged mapping, it must be preserved. 2875 * Move it back on the list and advance the end-of-list 2876 * pointer. 2877 */ 2878 if (PV_IS_KENTRY_P(pv->pv_flags)) { 2879 *pvp = pv; 2880 pvp = &SLIST_NEXT(pv, pv_link); 2881 continue; 2882 } 2883 if (pv->pv_flags & PVF_WRITE) 2884 md->krw_mappings--; 2885 else 2886 md->kro_mappings--; 2887 #endif 2888 PMAPCOUNT(kernel_unmappings); 2889 } 2890 *pvp = SLIST_NEXT(pv, pv_link); /* remove from list */ 2891 PMAPCOUNT(unmappings); 2892 2893 pmap_release_page_lock(md); 2894 pmap_acquire_pmap_lock(pm); 2895 2896 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2897 KASSERTMSG(l2b != NULL, "%#lx", pv->pv_va); 2898 2899 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2900 2901 /* 2902 * Update statistics 2903 */ 2904 --pm->pm_stats.resident_count; 2905 2906 /* Wired bit */ 2907 if (pv->pv_flags & PVF_WIRED) 2908 --pm->pm_stats.wired_count; 2909 2910 flags |= pv->pv_flags; 2911 2912 /* 2913 * Invalidate the PTEs. 2914 */ 2915 l2pte_reset(ptep); 2916 PTE_SYNC_CURRENT(pm, ptep); 2917 2918 #ifdef ARM_MMU_EXTENDED 2919 pmap_tlb_invalidate_addr(pm, pv->pv_va); 2920 #endif 2921 2922 pmap_free_l2_bucket(pm, l2b, PAGE_SIZE / L2_S_SIZE); 2923 2924 pmap_release_pmap_lock(pm); 2925 2926 pool_put(&pmap_pv_pool, pv); 2927 pmap_acquire_page_lock(md); 2928 #ifdef MULTIPROCESSOR 2929 /* 2930 * Restart of the beginning of the list. 2931 */ 2932 pvp = &SLIST_FIRST(&md->pvh_list); 2933 #endif 2934 } 2935 /* 2936 * if we reach the end of the list and there are still mappings, they 2937 * might be able to be cached now. And they must be kernel mappings. 2938 */ 2939 if (!SLIST_EMPTY(&md->pvh_list)) { 2940 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 2941 } 2942 2943 #ifdef PMAP_CACHE_VIPT 2944 /* 2945 * Its EXEC cache is now gone. 2946 */ 2947 if (PV_IS_EXEC_P(md->pvh_attrs)) 2948 PMAPCOUNT(exec_discarded_page_protect); 2949 md->pvh_attrs &= ~PVF_EXEC; 2950 KASSERT(md->urw_mappings == 0); 2951 KASSERT(md->uro_mappings == 0); 2952 #ifndef ARM_MMU_EXTENDED 2953 if (arm_cache_prefer_mask != 0) { 2954 if (md->krw_mappings == 0) 2955 md->pvh_attrs &= ~PVF_WRITE; 2956 PMAP_VALIDATE_MD_PAGE(md); 2957 } 2958 #endif /* ARM_MMU_EXTENDED */ 2959 #endif /* PMAP_CACHE_VIPT */ 2960 pmap_release_page_lock(md); 2961 2962 #ifndef ARM_MMU_EXTENDED 2963 if (flush) { 2964 /* 2965 * Note: We can't use pmap_tlb_flush{I,D}() here since that 2966 * would need a subsequent call to pmap_update() to ensure 2967 * curpm->pm_cstate.cs_all is reset. Our callers are not 2968 * required to do that (see pmap(9)), so we can't modify 2969 * the current pmap's state. 2970 */ 2971 if (PV_BEEN_EXECD(flags)) 2972 cpu_tlb_flushID(); 2973 else 2974 cpu_tlb_flushD(); 2975 } 2976 cpu_cpwait(); 2977 #endif /* ARM_MMU_EXTENDED */ 2978 } 2979 2980 /* 2981 * pmap_t pmap_create(void) 2982 * 2983 * Create a new pmap structure from scratch. 2984 */ 2985 pmap_t 2986 pmap_create(void) 2987 { 2988 pmap_t pm; 2989 2990 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 2991 2992 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 2993 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 2994 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 2995 2996 pm->pm_stats.wired_count = 0; 2997 pm->pm_stats.resident_count = 1; 2998 #ifdef ARM_MMU_EXTENDED 2999 #ifdef MULTIPROCESSOR 3000 kcpuset_create(&pm->pm_active, true); 3001 kcpuset_create(&pm->pm_onproc, true); 3002 #endif 3003 #else 3004 pm->pm_cstate.cs_all = 0; 3005 #endif 3006 pmap_alloc_l1(pm); 3007 3008 /* 3009 * Note: The pool cache ensures that the pm_l2[] array is already 3010 * initialised to zero. 3011 */ 3012 3013 pmap_pinit(pm); 3014 3015 return (pm); 3016 } 3017 3018 u_int 3019 arm32_mmap_flags(paddr_t pa) 3020 { 3021 /* 3022 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 3023 * and we're using the upper bits in page numbers to pass flags around 3024 * so we might as well use the same bits 3025 */ 3026 return (u_int)pa & PMAP_MD_MASK; 3027 } 3028 /* 3029 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 3030 * u_int flags) 3031 * 3032 * Insert the given physical page (p) at 3033 * the specified virtual address (v) in the 3034 * target physical map with the protection requested. 3035 * 3036 * NB: This is the only routine which MAY NOT lazy-evaluate 3037 * or lose information. That is, this routine must actually 3038 * insert this page into the given map NOW. 3039 */ 3040 int 3041 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3042 { 3043 struct l2_bucket *l2b; 3044 struct vm_page *pg, *opg; 3045 u_int nflags; 3046 u_int oflags; 3047 const bool kpm_p = (pm == pmap_kernel()); 3048 #ifdef ARM_HAS_VBAR 3049 const bool vector_page_p = false; 3050 #else 3051 const bool vector_page_p = (va == vector_page); 3052 #endif 3053 3054 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3055 3056 UVMHIST_LOG(maphist, " (pm %#jx va %#jx pa %#jx prot %#jx", 3057 (uintptr_t)pm, va, pa, prot); 3058 UVMHIST_LOG(maphist, " flag %#jx", flags, 0, 0, 0); 3059 3060 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 3061 KDASSERT(((va | pa) & PGOFSET) == 0); 3062 3063 /* 3064 * Get a pointer to the page. Later on in this function, we 3065 * test for a managed page by checking pg != NULL. 3066 */ 3067 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 3068 3069 nflags = 0; 3070 if (prot & VM_PROT_WRITE) 3071 nflags |= PVF_WRITE; 3072 if (prot & VM_PROT_EXECUTE) 3073 nflags |= PVF_EXEC; 3074 if (flags & PMAP_WIRED) 3075 nflags |= PVF_WIRED; 3076 3077 pmap_acquire_pmap_lock(pm); 3078 3079 /* 3080 * Fetch the L2 bucket which maps this page, allocating one if 3081 * necessary for user pmaps. 3082 */ 3083 if (kpm_p) { 3084 l2b = pmap_get_l2_bucket(pm, va); 3085 } else { 3086 l2b = pmap_alloc_l2_bucket(pm, va); 3087 } 3088 if (l2b == NULL) { 3089 if (flags & PMAP_CANFAIL) { 3090 pmap_release_pmap_lock(pm); 3091 return (ENOMEM); 3092 } 3093 panic("pmap_enter: failed to allocate L2 bucket"); 3094 } 3095 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(va)]; 3096 const pt_entry_t opte = *ptep; 3097 pt_entry_t npte = pa; 3098 oflags = 0; 3099 3100 if (opte) { 3101 /* 3102 * There is already a mapping at this address. 3103 * If the physical address is different, lookup the 3104 * vm_page. 3105 */ 3106 if (l2pte_pa(opte) != pa) { 3107 KASSERT(!pmap_pv_tracked(pa)); 3108 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3109 } else 3110 opg = pg; 3111 } else 3112 opg = NULL; 3113 3114 struct pmap_page *pp = pmap_pv_tracked(pa); 3115 3116 if (pg || pp) { 3117 KASSERT((pg != NULL) != (pp != NULL)); 3118 struct vm_page_md *md = (pg != NULL) ? VM_PAGE_TO_MD(pg) : 3119 PMAP_PAGE_TO_MD(pp); 3120 3121 /* 3122 * This is to be a managed mapping. 3123 */ 3124 pmap_acquire_page_lock(md); 3125 if ((flags & VM_PROT_ALL) || (md->pvh_attrs & PVF_REF)) { 3126 /* 3127 * - The access type indicates that we don't need 3128 * to do referenced emulation. 3129 * OR 3130 * - The physical page has already been referenced 3131 * so no need to re-do referenced emulation here. 3132 */ 3133 npte |= l2pte_set_readonly(L2_S_PROTO); 3134 3135 nflags |= PVF_REF; 3136 3137 if ((prot & VM_PROT_WRITE) != 0 && 3138 ((flags & VM_PROT_WRITE) != 0 || 3139 (md->pvh_attrs & PVF_MOD) != 0)) { 3140 /* 3141 * This is a writable mapping, and the 3142 * page's mod state indicates it has 3143 * already been modified. Make it 3144 * writable from the outset. 3145 */ 3146 npte = l2pte_set_writable(npte); 3147 nflags |= PVF_MOD; 3148 } 3149 3150 #ifdef ARM_MMU_EXTENDED 3151 /* 3152 * If the page has been cleaned, then the pvh_attrs 3153 * will have PVF_EXEC set, so mark it execute so we 3154 * don't get an access fault when trying to execute 3155 * from it. 3156 */ 3157 if (md->pvh_attrs & nflags & PVF_EXEC) { 3158 npte &= ~L2_XS_XN; 3159 } 3160 #endif 3161 } else { 3162 /* 3163 * Need to do page referenced emulation. 3164 */ 3165 npte |= L2_TYPE_INV; 3166 } 3167 3168 if (flags & ARM32_MMAP_WRITECOMBINE) { 3169 npte |= pte_l2_s_wc_mode; 3170 } else 3171 npte |= pte_l2_s_cache_mode; 3172 3173 if (pg != NULL && pg == opg) { 3174 /* 3175 * We're changing the attrs of an existing mapping. 3176 */ 3177 oflags = pmap_modify_pv(md, pa, pm, va, 3178 PVF_WRITE | PVF_EXEC | PVF_WIRED | 3179 PVF_MOD | PVF_REF, nflags); 3180 3181 #ifdef PMAP_CACHE_VIVT 3182 /* 3183 * We may need to flush the cache if we're 3184 * doing rw-ro... 3185 */ 3186 if (pm->pm_cstate.cs_cache_d && 3187 (oflags & PVF_NC) == 0 && 3188 l2pte_writable_p(opte) && 3189 (prot & VM_PROT_WRITE) == 0) 3190 cpu_dcache_wb_range(va, PAGE_SIZE); 3191 #endif 3192 } else { 3193 struct pv_entry *pv; 3194 /* 3195 * New mapping, or changing the backing page 3196 * of an existing mapping. 3197 */ 3198 if (opg) { 3199 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3200 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3201 3202 /* 3203 * Replacing an existing mapping with a new one. 3204 * It is part of our managed memory so we 3205 * must remove it from the PV list 3206 */ 3207 pv = pmap_remove_pv(omd, opa, pm, va); 3208 pmap_vac_me_harder(omd, opa, pm, 0); 3209 oflags = pv->pv_flags; 3210 3211 #ifdef PMAP_CACHE_VIVT 3212 /* 3213 * If the old mapping was valid (ref/mod 3214 * emulation creates 'invalid' mappings 3215 * initially) then make sure to frob 3216 * the cache. 3217 */ 3218 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3219 pmap_cache_wbinv_page(pm, va, true, 3220 oflags); 3221 } 3222 #endif 3223 } else { 3224 pmap_release_page_lock(md); 3225 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3226 if (pv == NULL) { 3227 pmap_release_pmap_lock(pm); 3228 if ((flags & PMAP_CANFAIL) == 0) 3229 panic("pmap_enter: " 3230 "no pv entries"); 3231 3232 pmap_free_l2_bucket(pm, l2b, 0); 3233 UVMHIST_LOG(maphist, " <-- done (ENOMEM)", 3234 0, 0, 0, 0); 3235 return (ENOMEM); 3236 } 3237 pmap_acquire_page_lock(md); 3238 } 3239 3240 pmap_enter_pv(md, pa, pv, pm, va, nflags); 3241 } 3242 pmap_release_page_lock(md); 3243 } else { 3244 /* 3245 * We're mapping an unmanaged page. 3246 * These are always readable, and possibly writable, from 3247 * the get go as we don't need to track ref/mod status. 3248 */ 3249 npte |= l2pte_set_readonly(L2_S_PROTO); 3250 if (prot & VM_PROT_WRITE) 3251 npte = l2pte_set_writable(npte); 3252 3253 /* 3254 * Make sure the vector table is mapped cacheable 3255 */ 3256 if ((vector_page_p && !kpm_p) 3257 || (flags & ARM32_MMAP_CACHEABLE)) { 3258 npte |= pte_l2_s_cache_mode; 3259 #ifdef ARM_MMU_EXTENDED 3260 npte &= ~L2_XS_XN; /* and executable */ 3261 #endif 3262 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 3263 npte |= pte_l2_s_wc_mode; 3264 } 3265 if (opg) { 3266 /* 3267 * Looks like there's an existing 'managed' mapping 3268 * at this address. 3269 */ 3270 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3271 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3272 3273 pmap_acquire_page_lock(omd); 3274 struct pv_entry *pv = pmap_remove_pv(omd, opa, pm, va); 3275 pmap_vac_me_harder(omd, opa, pm, 0); 3276 oflags = pv->pv_flags; 3277 pmap_release_page_lock(omd); 3278 3279 #ifdef PMAP_CACHE_VIVT 3280 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3281 pmap_cache_wbinv_page(pm, va, true, oflags); 3282 } 3283 #endif 3284 pool_put(&pmap_pv_pool, pv); 3285 } 3286 } 3287 3288 /* 3289 * Make sure userland mappings get the right permissions 3290 */ 3291 if (!vector_page_p && !kpm_p) { 3292 npte |= L2_S_PROT_U; 3293 #ifdef ARM_MMU_EXTENDED 3294 npte |= L2_XS_nG; /* user pages are not global */ 3295 #endif 3296 } 3297 3298 /* 3299 * Keep the stats up to date 3300 */ 3301 if (opte == 0) { 3302 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3303 pm->pm_stats.resident_count++; 3304 } 3305 3306 UVMHIST_LOG(maphist, " opte %#jx npte %#jx", opte, npte, 0, 0); 3307 3308 #if defined(ARM_MMU_EXTENDED) 3309 /* 3310 * If exec protection was requested but the page hasn't been synced, 3311 * sync it now and allow execution from it. 3312 */ 3313 if ((nflags & PVF_EXEC) && (npte & L2_XS_XN)) { 3314 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3315 npte &= ~L2_XS_XN; 3316 pmap_syncicache_page(md, pa); 3317 PMAPCOUNT(exec_synced_map); 3318 } 3319 #endif 3320 /* 3321 * If this is just a wiring change, the two PTEs will be 3322 * identical, so there's no need to update the page table. 3323 */ 3324 if (npte != opte) { 3325 l2pte_reset(ptep); 3326 PTE_SYNC(ptep); 3327 if (l2pte_valid_p(opte)) { 3328 pmap_tlb_flush_SE(pm, va, oflags); 3329 } 3330 l2pte_set(ptep, npte, 0); 3331 PTE_SYNC(ptep); 3332 #ifndef ARM_MMU_EXTENDED 3333 bool is_cached = pmap_is_cached(pm); 3334 if (is_cached) { 3335 /* 3336 * We only need to frob the cache/tlb if this pmap 3337 * is current 3338 */ 3339 if (!vector_page_p && l2pte_valid_p(npte)) { 3340 /* 3341 * This mapping is likely to be accessed as 3342 * soon as we return to userland. Fix up the 3343 * L1 entry to avoid taking another 3344 * page/domain fault. 3345 */ 3346 pd_entry_t *pdep = pmap_l1_kva(pm) 3347 + l1pte_index(va); 3348 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa 3349 | L1_C_DOM(pmap_domain(pm)); 3350 if (*pdep != pde) { 3351 l1pte_setone(pdep, pde); 3352 PDE_SYNC(pdep); 3353 } 3354 } 3355 } 3356 #endif /* !ARM_MMU_EXTENDED */ 3357 3358 #ifndef ARM_MMU_EXTENDED 3359 UVMHIST_LOG(maphist, " is_cached %jd cs 0x%08jx", 3360 is_cached, pm->pm_cstate.cs_all, 0, 0); 3361 3362 if (pg != NULL) { 3363 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3364 3365 pmap_acquire_page_lock(md); 3366 pmap_vac_me_harder(md, pa, pm, va); 3367 pmap_release_page_lock(md); 3368 } 3369 #endif 3370 } 3371 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3372 if (pg) { 3373 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3374 3375 pmap_acquire_page_lock(md); 3376 #ifndef ARM_MMU_EXTENDED 3377 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3378 #endif 3379 PMAP_VALIDATE_MD_PAGE(md); 3380 pmap_release_page_lock(md); 3381 } 3382 #endif 3383 3384 pmap_release_pmap_lock(pm); 3385 3386 return (0); 3387 } 3388 3389 /* 3390 * pmap_remove() 3391 * 3392 * pmap_remove is responsible for nuking a number of mappings for a range 3393 * of virtual address space in the current pmap. To do this efficiently 3394 * is interesting, because in a number of cases a wide virtual address 3395 * range may be supplied that contains few actual mappings. So, the 3396 * optimisations are: 3397 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3398 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3399 * maybe do just a partial cache clean. This path of execution is 3400 * complicated by the fact that the cache must be flushed _before_ 3401 * the PTE is nuked, being a VAC :-) 3402 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3403 * all invalidations until pmap_update(), since pmap_remove_all() has 3404 * already flushed the cache. 3405 * 4. Maybe later fast-case a single page, but I don't think this is 3406 * going to make _that_ much difference overall. 3407 */ 3408 3409 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3410 3411 void 3412 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3413 { 3414 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3415 UVMHIST_LOG(maphist, " (pm=%#jx, sva=%#jx, eva=%#jx)", 3416 (uintptr_t)pm, sva, eva, 0); 3417 3418 /* 3419 * we lock in the pmap => pv_head direction 3420 */ 3421 pmap_acquire_pmap_lock(pm); 3422 3423 #ifndef ARM_MMU_EXTENDED 3424 u_int cleanlist_idx, total, cnt; 3425 struct { 3426 vaddr_t va; 3427 pt_entry_t *ptep; 3428 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3429 3430 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3431 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3432 if (pm->pm_cstate.cs_tlb == 0) 3433 pm->pm_remove_all = true; 3434 } else 3435 cleanlist_idx = 0; 3436 total = 0; 3437 #endif 3438 3439 while (sva < eva) { 3440 /* 3441 * Do one L2 bucket's worth at a time. 3442 */ 3443 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(sva); 3444 if (next_bucket > eva) 3445 next_bucket = eva; 3446 3447 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, sva); 3448 if (l2b == NULL) { 3449 sva = next_bucket; 3450 continue; 3451 } 3452 3453 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3454 u_int mappings = 0; 3455 3456 for (;sva < next_bucket; 3457 sva += PAGE_SIZE, ptep += PAGE_SIZE / L2_S_SIZE) { 3458 pt_entry_t opte = *ptep; 3459 3460 if (opte == 0) { 3461 /* Nothing here, move along */ 3462 continue; 3463 } 3464 3465 u_int flags = PVF_REF; 3466 paddr_t pa = l2pte_pa(opte); 3467 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 3468 3469 /* 3470 * Update flags. In a number of circumstances, 3471 * we could cluster a lot of these and do a 3472 * number of sequential pages in one go. 3473 */ 3474 if (pg != NULL) { 3475 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3476 struct pv_entry *pv; 3477 3478 pmap_acquire_page_lock(md); 3479 pv = pmap_remove_pv(md, pa, pm, sva); 3480 pmap_vac_me_harder(md, pa, pm, 0); 3481 pmap_release_page_lock(md); 3482 if (pv != NULL) { 3483 if (pm->pm_remove_all == false) { 3484 flags = pv->pv_flags; 3485 } 3486 pool_put(&pmap_pv_pool, pv); 3487 } 3488 } 3489 mappings += PAGE_SIZE / L2_S_SIZE; 3490 3491 if (!l2pte_valid_p(opte)) { 3492 /* 3493 * Ref/Mod emulation is still active for this 3494 * mapping, therefore it is has not yet been 3495 * accessed. No need to frob the cache/tlb. 3496 */ 3497 l2pte_reset(ptep); 3498 PTE_SYNC_CURRENT(pm, ptep); 3499 continue; 3500 } 3501 3502 #ifdef ARM_MMU_EXTENDED 3503 l2pte_reset(ptep); 3504 PTE_SYNC(ptep); 3505 if (__predict_false(pm->pm_remove_all == false)) { 3506 pmap_tlb_flush_SE(pm, sva, flags); 3507 } 3508 #else 3509 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3510 /* Add to the clean list. */ 3511 cleanlist[cleanlist_idx].ptep = ptep; 3512 cleanlist[cleanlist_idx].va = 3513 sva | (flags & PVF_EXEC); 3514 cleanlist_idx++; 3515 } else if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3516 /* Nuke everything if needed. */ 3517 #ifdef PMAP_CACHE_VIVT 3518 pmap_cache_wbinv_all(pm, PVF_EXEC); 3519 #endif 3520 /* 3521 * Roll back the previous PTE list, 3522 * and zero out the current PTE. 3523 */ 3524 for (cnt = 0; 3525 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3526 l2pte_reset(cleanlist[cnt].ptep); 3527 PTE_SYNC(cleanlist[cnt].ptep); 3528 } 3529 l2pte_reset(ptep); 3530 PTE_SYNC(ptep); 3531 cleanlist_idx++; 3532 pm->pm_remove_all = true; 3533 } else { 3534 l2pte_reset(ptep); 3535 PTE_SYNC(ptep); 3536 if (pm->pm_remove_all == false) { 3537 pmap_tlb_flush_SE(pm, sva, flags); 3538 } 3539 } 3540 #endif 3541 } 3542 3543 #ifndef ARM_MMU_EXTENDED 3544 /* 3545 * Deal with any left overs 3546 */ 3547 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3548 total += cleanlist_idx; 3549 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3550 l2pte_reset(cleanlist[cnt].ptep); 3551 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3552 vaddr_t va = cleanlist[cnt].va; 3553 if (pm->pm_cstate.cs_all != 0) { 3554 vaddr_t clva = va & ~PAGE_MASK; 3555 u_int flags = va & PVF_EXEC; 3556 #ifdef PMAP_CACHE_VIVT 3557 pmap_cache_wbinv_page(pm, clva, true, 3558 PVF_REF | PVF_WRITE | flags); 3559 #endif 3560 pmap_tlb_flush_SE(pm, clva, 3561 PVF_REF | flags); 3562 } 3563 } 3564 3565 /* 3566 * If it looks like we're removing a whole bunch 3567 * of mappings, it's faster to just write-back 3568 * the whole cache now and defer TLB flushes until 3569 * pmap_update() is called. 3570 */ 3571 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3572 cleanlist_idx = 0; 3573 else { 3574 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3575 #ifdef PMAP_CACHE_VIVT 3576 pmap_cache_wbinv_all(pm, PVF_EXEC); 3577 #endif 3578 pm->pm_remove_all = true; 3579 } 3580 } 3581 #endif /* ARM_MMU_EXTENDED */ 3582 3583 pmap_free_l2_bucket(pm, l2b, mappings); 3584 pm->pm_stats.resident_count -= mappings / (PAGE_SIZE/L2_S_SIZE); 3585 } 3586 3587 pmap_release_pmap_lock(pm); 3588 } 3589 3590 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3591 static struct pv_entry * 3592 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3593 { 3594 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3595 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3596 struct pv_entry *pv; 3597 3598 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3599 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3600 KASSERT(pmap_page_locked_p(md)); 3601 3602 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3603 KASSERTMSG(pv, "pg %p (pa #%lx) va %#lx", pg, pa, va); 3604 KASSERT(PV_IS_KENTRY_P(pv->pv_flags)); 3605 3606 /* 3607 * If we are removing a writeable mapping to a cached exec page, 3608 * if it's the last mapping then clear it execness other sync 3609 * the page to the icache. 3610 */ 3611 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3612 && (pv->pv_flags & PVF_WRITE) != 0) { 3613 if (SLIST_EMPTY(&md->pvh_list)) { 3614 md->pvh_attrs &= ~PVF_EXEC; 3615 PMAPCOUNT(exec_discarded_kremove); 3616 } else { 3617 pmap_syncicache_page(md, pa); 3618 PMAPCOUNT(exec_synced_kremove); 3619 } 3620 } 3621 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3622 3623 return pv; 3624 } 3625 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 3626 3627 /* 3628 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3629 * 3630 * We assume there is already sufficient KVM space available 3631 * to do this, as we can't allocate L2 descriptor tables/metadata 3632 * from here. 3633 */ 3634 void 3635 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3636 { 3637 #ifdef PMAP_CACHE_VIVT 3638 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3639 #endif 3640 #ifdef PMAP_CACHE_VIPT 3641 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3642 struct vm_page *opg; 3643 #ifndef ARM_MMU_EXTENDED 3644 struct pv_entry *pv = NULL; 3645 #endif 3646 #endif 3647 struct vm_page_md *md = pg != NULL ? VM_PAGE_TO_MD(pg) : NULL; 3648 3649 UVMHIST_FUNC(__func__); 3650 3651 if (pmap_initialized) { 3652 UVMHIST_CALLED(maphist); 3653 UVMHIST_LOG(maphist, " (va=%#jx, pa=%#jx, prot=%#jx, flags=%#jx", 3654 va, pa, prot, flags); 3655 } 3656 3657 pmap_t kpm = pmap_kernel(); 3658 pmap_acquire_pmap_lock(kpm); 3659 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3660 const size_t l1slot __diagused = l1pte_index(va); 3661 KASSERTMSG(l2b != NULL, 3662 "va %#lx pa %#lx prot %d maxkvaddr %#lx: l2 %p l2b %p kva %p", 3663 va, pa, prot, pmap_curmaxkvaddr, kpm->pm_l2[L2_IDX(l1slot)], 3664 kpm->pm_l2[L2_IDX(l1slot)] 3665 ? &kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)] 3666 : NULL, 3667 kpm->pm_l2[L2_IDX(l1slot)] 3668 ? kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)].l2b_kva 3669 : NULL); 3670 KASSERT(l2b->l2b_kva != NULL); 3671 3672 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 3673 const pt_entry_t opte = *ptep; 3674 3675 if (opte == 0) { 3676 PMAPCOUNT(kenter_mappings); 3677 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3678 } else { 3679 PMAPCOUNT(kenter_remappings); 3680 #ifdef PMAP_CACHE_VIPT 3681 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3682 #if !defined(ARM_MMU_EXTENDED) || defined(DIAGNOSTIC) 3683 struct vm_page_md *omd __diagused = VM_PAGE_TO_MD(opg); 3684 #endif 3685 if (opg && arm_cache_prefer_mask != 0) { 3686 KASSERT(opg != pg); 3687 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3688 KASSERT((flags & PMAP_KMPAGE) == 0); 3689 #ifndef ARM_MMU_EXTENDED 3690 pmap_acquire_page_lock(omd); 3691 pv = pmap_kremove_pg(opg, va); 3692 pmap_release_page_lock(omd); 3693 #endif 3694 } 3695 #endif 3696 if (l2pte_valid_p(opte)) { 3697 l2pte_reset(ptep); 3698 PTE_SYNC(ptep); 3699 #ifdef PMAP_CACHE_VIVT 3700 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3701 #endif 3702 cpu_tlb_flushD_SE(va); 3703 cpu_cpwait(); 3704 } 3705 } 3706 pmap_release_pmap_lock(kpm); 3707 3708 pt_entry_t npte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) 3709 | ((flags & PMAP_NOCACHE) 3710 ? 0 3711 : ((flags & PMAP_PTE) 3712 ? pte_l2_s_cache_mode_pt : pte_l2_s_cache_mode)); 3713 #ifdef ARM_MMU_EXTENDED 3714 if (prot & VM_PROT_EXECUTE) 3715 npte &= ~L2_XS_XN; 3716 #endif 3717 l2pte_set(ptep, npte, 0); 3718 PTE_SYNC(ptep); 3719 3720 if (pg) { 3721 if (flags & PMAP_KMPAGE) { 3722 KASSERT(md->urw_mappings == 0); 3723 KASSERT(md->uro_mappings == 0); 3724 KASSERT(md->krw_mappings == 0); 3725 KASSERT(md->kro_mappings == 0); 3726 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3727 KASSERT(pv == NULL); 3728 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3729 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3730 /* if there is a color conflict, evict from cache. */ 3731 if (pmap_is_page_colored_p(md) 3732 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3733 PMAPCOUNT(vac_color_change); 3734 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3735 } else if (md->pvh_attrs & PVF_MULTCLR) { 3736 /* 3737 * If this page has multiple colors, expunge 3738 * them. 3739 */ 3740 PMAPCOUNT(vac_flush_lots2); 3741 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3742 } 3743 /* 3744 * Since this is a KMPAGE, there can be no contention 3745 * for this page so don't lock it. 3746 */ 3747 md->pvh_attrs &= PAGE_SIZE - 1; 3748 md->pvh_attrs |= PVF_KMPAGE | PVF_COLORED | PVF_DIRTY 3749 | (va & arm_cache_prefer_mask); 3750 #else /* !PMAP_CACHE_VIPT || ARM_MMU_EXTENDED */ 3751 md->pvh_attrs |= PVF_KMPAGE; 3752 #endif 3753 atomic_inc_32(&pmap_kmpages); 3754 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3755 } else if (arm_cache_prefer_mask != 0) { 3756 if (pv == NULL) { 3757 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3758 KASSERT(pv != NULL); 3759 } 3760 pmap_acquire_page_lock(md); 3761 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3762 PVF_WIRED | PVF_KENTRY 3763 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3764 if ((prot & VM_PROT_WRITE) 3765 && !(md->pvh_attrs & PVF_NC)) 3766 md->pvh_attrs |= PVF_DIRTY; 3767 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3768 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3769 pmap_release_page_lock(md); 3770 #endif 3771 } 3772 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3773 } else { 3774 if (pv != NULL) 3775 pool_put(&pmap_pv_pool, pv); 3776 #endif 3777 } 3778 if (pmap_initialized) { 3779 UVMHIST_LOG(maphist, " <-- done (ptep %#jx: %#jx -> %#jx)", 3780 (uintptr_t)ptep, opte, npte, 0); 3781 } 3782 3783 } 3784 3785 void 3786 pmap_kremove(vaddr_t va, vsize_t len) 3787 { 3788 #ifdef UVMHIST 3789 u_int total_mappings = 0; 3790 #endif 3791 3792 PMAPCOUNT(kenter_unmappings); 3793 3794 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 3795 3796 UVMHIST_LOG(maphist, " (va=%#jx, len=%#jx)", va, len, 0, 0); 3797 3798 const vaddr_t eva = va + len; 3799 3800 pmap_acquire_pmap_lock(pmap_kernel()); 3801 3802 while (va < eva) { 3803 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(va); 3804 if (next_bucket > eva) 3805 next_bucket = eva; 3806 3807 pmap_t kpm = pmap_kernel(); 3808 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3809 KDASSERT(l2b != NULL); 3810 3811 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 3812 pt_entry_t *ptep = sptep; 3813 u_int mappings = 0; 3814 3815 while (va < next_bucket) { 3816 const pt_entry_t opte = *ptep; 3817 struct vm_page *opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3818 if (opg != NULL) { 3819 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3820 3821 if (omd->pvh_attrs & PVF_KMPAGE) { 3822 KASSERT(omd->urw_mappings == 0); 3823 KASSERT(omd->uro_mappings == 0); 3824 KASSERT(omd->krw_mappings == 0); 3825 KASSERT(omd->kro_mappings == 0); 3826 omd->pvh_attrs &= ~PVF_KMPAGE; 3827 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3828 if (arm_cache_prefer_mask != 0) { 3829 omd->pvh_attrs &= ~PVF_WRITE; 3830 } 3831 #endif 3832 atomic_dec_32(&pmap_kmpages); 3833 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3834 } else if (arm_cache_prefer_mask != 0) { 3835 pmap_acquire_page_lock(omd); 3836 pool_put(&pmap_pv_pool, 3837 pmap_kremove_pg(opg, va)); 3838 pmap_release_page_lock(omd); 3839 #endif 3840 } 3841 } 3842 if (l2pte_valid_p(opte)) { 3843 l2pte_reset(ptep); 3844 PTE_SYNC(ptep); 3845 #ifdef PMAP_CACHE_VIVT 3846 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3847 #endif 3848 cpu_tlb_flushD_SE(va); 3849 3850 mappings += PAGE_SIZE / L2_S_SIZE; 3851 } 3852 va += PAGE_SIZE; 3853 ptep += PAGE_SIZE / L2_S_SIZE; 3854 } 3855 KDASSERTMSG(mappings <= l2b->l2b_occupancy, "%u %u", 3856 mappings, l2b->l2b_occupancy); 3857 l2b->l2b_occupancy -= mappings; 3858 //PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3859 #ifdef UVMHIST 3860 total_mappings += mappings; 3861 #endif 3862 } 3863 pmap_release_pmap_lock(pmap_kernel()); 3864 cpu_cpwait(); 3865 UVMHIST_LOG(maphist, " <--- done (%ju mappings removed)", 3866 total_mappings, 0, 0, 0); 3867 } 3868 3869 bool 3870 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3871 { 3872 struct l2_dtable *l2; 3873 pd_entry_t *pdep, pde; 3874 pt_entry_t *ptep, pte; 3875 paddr_t pa; 3876 u_int l1slot; 3877 3878 pmap_acquire_pmap_lock(pm); 3879 3880 l1slot = l1pte_index(va); 3881 pdep = pmap_l1_kva(pm) + l1slot; 3882 pde = *pdep; 3883 3884 if (l1pte_section_p(pde)) { 3885 /* 3886 * These should only happen for pmap_kernel() 3887 */ 3888 KDASSERT(pm == pmap_kernel()); 3889 pmap_release_pmap_lock(pm); 3890 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 3891 if (l1pte_supersection_p(pde)) { 3892 pa = (pde & L1_SS_FRAME) | (va & L1_SS_OFFSET); 3893 } else 3894 #endif 3895 pa = (pde & L1_S_FRAME) | (va & L1_S_OFFSET); 3896 } else { 3897 /* 3898 * Note that we can't rely on the validity of the L1 3899 * descriptor as an indication that a mapping exists. 3900 * We have to look it up in the L2 dtable. 3901 */ 3902 l2 = pm->pm_l2[L2_IDX(l1slot)]; 3903 3904 if (l2 == NULL || 3905 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 3906 pmap_release_pmap_lock(pm); 3907 return false; 3908 } 3909 3910 pte = ptep[l2pte_index(va)]; 3911 pmap_release_pmap_lock(pm); 3912 3913 if (pte == 0) 3914 return false; 3915 3916 switch (pte & L2_TYPE_MASK) { 3917 case L2_TYPE_L: 3918 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3919 break; 3920 3921 default: 3922 pa = (pte & ~PAGE_MASK) | (va & PAGE_MASK); 3923 break; 3924 } 3925 } 3926 3927 if (pap != NULL) 3928 *pap = pa; 3929 3930 return true; 3931 } 3932 3933 /* 3934 * pmap_pv_remove: remove an unmanaged pv-tracked page from all pmaps 3935 * that map it 3936 */ 3937 3938 static void 3939 pmap_pv_remove(paddr_t pa) 3940 { 3941 struct pmap_page *pp; 3942 3943 pp = pmap_pv_tracked(pa); 3944 if (pp == NULL) 3945 panic("pmap_pv_protect: page not pv-tracked: 0x%"PRIxPADDR, 3946 pa); 3947 3948 struct vm_page_md *md = PMAP_PAGE_TO_MD(pp); 3949 pmap_page_remove(md, pa); 3950 } 3951 3952 void 3953 pmap_pv_protect(paddr_t pa, vm_prot_t prot) 3954 { 3955 3956 /* the only case is remove at the moment */ 3957 KASSERT(prot == VM_PROT_NONE); 3958 pmap_pv_remove(pa); 3959 } 3960 3961 void 3962 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 3963 { 3964 struct l2_bucket *l2b; 3965 vaddr_t next_bucket; 3966 3967 NPDEBUG(PDB_PROTECT, 3968 printf("pmap_protect: pm %p sva 0x%lx eva 0x%lx prot 0x%x\n", 3969 pm, sva, eva, prot)); 3970 3971 if ((prot & VM_PROT_READ) == 0) { 3972 pmap_remove(pm, sva, eva); 3973 return; 3974 } 3975 3976 if (prot & VM_PROT_WRITE) { 3977 /* 3978 * If this is a read->write transition, just ignore it and let 3979 * uvm_fault() take care of it later. 3980 */ 3981 return; 3982 } 3983 3984 pmap_acquire_pmap_lock(pm); 3985 3986 #ifndef ARM_MMU_EXTENDED 3987 const bool flush = eva - sva >= PAGE_SIZE * 4; 3988 u_int flags = 0; 3989 #endif 3990 u_int clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 3991 3992 while (sva < eva) { 3993 next_bucket = L2_NEXT_BUCKET_VA(sva); 3994 if (next_bucket > eva) 3995 next_bucket = eva; 3996 3997 l2b = pmap_get_l2_bucket(pm, sva); 3998 if (l2b == NULL) { 3999 sva = next_bucket; 4000 continue; 4001 } 4002 4003 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4004 4005 while (sva < next_bucket) { 4006 const pt_entry_t opte = *ptep; 4007 if (l2pte_valid_p(opte) && l2pte_writable_p(opte)) { 4008 struct vm_page *pg; 4009 #ifndef ARM_MMU_EXTENDED 4010 u_int f; 4011 #endif 4012 4013 #ifdef PMAP_CACHE_VIVT 4014 /* 4015 * OK, at this point, we know we're doing 4016 * write-protect operation. If the pmap is 4017 * active, write-back the page. 4018 */ 4019 pmap_cache_wbinv_page(pm, sva, false, 4020 PVF_REF | PVF_WRITE); 4021 #endif 4022 4023 pg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 4024 pt_entry_t npte = l2pte_set_readonly(opte); 4025 l2pte_reset(ptep); 4026 PTE_SYNC(ptep); 4027 #ifdef ARM_MMU_EXTENDED 4028 pmap_tlb_flush_SE(pm, sva, PVF_REF); 4029 #endif 4030 l2pte_set(ptep, npte, 0); 4031 PTE_SYNC(ptep); 4032 4033 if (pg != NULL) { 4034 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4035 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4036 4037 pmap_acquire_page_lock(md); 4038 #ifndef ARM_MMU_EXTENDED 4039 f = 4040 #endif 4041 pmap_modify_pv(md, pa, pm, sva, 4042 clr_mask, 0); 4043 pmap_vac_me_harder(md, pa, pm, sva); 4044 pmap_release_page_lock(md); 4045 #ifndef ARM_MMU_EXTENDED 4046 } else { 4047 f = PVF_REF | PVF_EXEC; 4048 } 4049 4050 if (flush) { 4051 flags |= f; 4052 } else { 4053 pmap_tlb_flush_SE(pm, sva, f); 4054 #endif 4055 } 4056 } 4057 4058 sva += PAGE_SIZE; 4059 ptep += PAGE_SIZE / L2_S_SIZE; 4060 } 4061 } 4062 4063 #ifndef ARM_MMU_EXTENDED 4064 if (flush) { 4065 if (PV_BEEN_EXECD(flags)) { 4066 pmap_tlb_flushID(pm); 4067 } else if (PV_BEEN_REFD(flags)) { 4068 pmap_tlb_flushD(pm); 4069 } 4070 } 4071 #endif 4072 4073 pmap_release_pmap_lock(pm); 4074 } 4075 4076 void 4077 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 4078 { 4079 struct l2_bucket *l2b; 4080 pt_entry_t *ptep; 4081 vaddr_t next_bucket; 4082 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 4083 4084 NPDEBUG(PDB_EXEC, 4085 printf("pmap_icache_sync_range: pm %p sva 0x%lx eva 0x%lx\n", 4086 pm, sva, eva)); 4087 4088 pmap_acquire_pmap_lock(pm); 4089 4090 while (sva < eva) { 4091 next_bucket = L2_NEXT_BUCKET_VA(sva); 4092 if (next_bucket > eva) 4093 next_bucket = eva; 4094 4095 l2b = pmap_get_l2_bucket(pm, sva); 4096 if (l2b == NULL) { 4097 sva = next_bucket; 4098 continue; 4099 } 4100 4101 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4102 sva < next_bucket; 4103 sva += page_size, 4104 ptep += PAGE_SIZE / L2_S_SIZE, 4105 page_size = PAGE_SIZE) { 4106 if (l2pte_valid_p(*ptep)) { 4107 cpu_icache_sync_range(sva, 4108 min(page_size, eva - sva)); 4109 } 4110 } 4111 } 4112 4113 pmap_release_pmap_lock(pm); 4114 } 4115 4116 void 4117 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 4118 { 4119 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4120 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4121 4122 NPDEBUG(PDB_PROTECT, 4123 printf("pmap_page_protect: md %p (0x%08lx), prot 0x%x\n", 4124 md, pa, prot)); 4125 4126 switch(prot) { 4127 case VM_PROT_READ|VM_PROT_WRITE: 4128 #if defined(ARM_MMU_EXTENDED) 4129 pmap_acquire_page_lock(md); 4130 pmap_clearbit(md, pa, PVF_EXEC); 4131 pmap_release_page_lock(md); 4132 break; 4133 #endif 4134 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 4135 break; 4136 4137 case VM_PROT_READ: 4138 #if defined(ARM_MMU_EXTENDED) 4139 pmap_acquire_page_lock(md); 4140 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 4141 pmap_release_page_lock(md); 4142 break; 4143 #endif 4144 case VM_PROT_READ|VM_PROT_EXECUTE: 4145 pmap_acquire_page_lock(md); 4146 pmap_clearbit(md, pa, PVF_WRITE); 4147 pmap_release_page_lock(md); 4148 break; 4149 4150 default: 4151 pmap_page_remove(md, pa); 4152 break; 4153 } 4154 } 4155 4156 /* 4157 * pmap_clear_modify: 4158 * 4159 * Clear the "modified" attribute for a page. 4160 */ 4161 bool 4162 pmap_clear_modify(struct vm_page *pg) 4163 { 4164 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4165 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4166 bool rv; 4167 4168 pmap_acquire_page_lock(md); 4169 4170 if (md->pvh_attrs & PVF_MOD) { 4171 rv = true; 4172 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4173 /* 4174 * If we are going to clear the modified bit and there are 4175 * no other modified bits set, flush the page to memory and 4176 * mark it clean. 4177 */ 4178 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 4179 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 4180 #endif 4181 pmap_clearbit(md, pa, PVF_MOD); 4182 } else { 4183 rv = false; 4184 } 4185 pmap_release_page_lock(md); 4186 4187 return rv; 4188 } 4189 4190 /* 4191 * pmap_clear_reference: 4192 * 4193 * Clear the "referenced" attribute for a page. 4194 */ 4195 bool 4196 pmap_clear_reference(struct vm_page *pg) 4197 { 4198 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4199 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4200 bool rv; 4201 4202 pmap_acquire_page_lock(md); 4203 4204 if (md->pvh_attrs & PVF_REF) { 4205 rv = true; 4206 pmap_clearbit(md, pa, PVF_REF); 4207 } else { 4208 rv = false; 4209 } 4210 pmap_release_page_lock(md); 4211 4212 return rv; 4213 } 4214 4215 /* 4216 * pmap_is_modified: 4217 * 4218 * Test if a page has the "modified" attribute. 4219 */ 4220 /* See <arm/arm32/pmap.h> */ 4221 4222 /* 4223 * pmap_is_referenced: 4224 * 4225 * Test if a page has the "referenced" attribute. 4226 */ 4227 /* See <arm/arm32/pmap.h> */ 4228 4229 #if defined(ARM_MMU_EXTENDED) && 0 4230 int 4231 pmap_prefetchabt_fixup(void *v) 4232 { 4233 struct trapframe * const tf = v; 4234 vaddr_t va = trunc_page(tf->tf_pc); 4235 int rv = ABORT_FIXUP_FAILED; 4236 4237 if (!TRAP_USERMODE(tf) && va < VM_MAXUSER_ADDRESS) 4238 return rv; 4239 4240 kpreempt_disable(); 4241 pmap_t pm = curcpu()->ci_pmap_cur; 4242 const size_t l1slot = l1pte_index(va); 4243 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 4244 if (l2 == NULL) 4245 goto out; 4246 4247 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4248 if (l2b->l2b_kva == NULL) 4249 goto out; 4250 4251 /* 4252 * Check the PTE itself. 4253 */ 4254 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4255 const pt_entry_t opte = *ptep; 4256 if ((opte & L2_S_PROT_U) == 0 || (opte & L2_XS_XN) == 0) 4257 goto out; 4258 4259 paddr_t pa = l2pte_pa(opte); 4260 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4261 KASSERT(pg != NULL); 4262 4263 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4264 4265 pmap_acquire_page_lock(md); 4266 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4267 KASSERT(pv != NULL); 4268 4269 if (PV_IS_EXEC_P(pv->pv_flags)) { 4270 l2pte_reset(ptep); 4271 PTE_SYNC(ptep); 4272 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4273 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 4274 pmap_syncicache_page(md, pa); 4275 } 4276 rv = ABORT_FIXUP_RETURN; 4277 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4278 PTE_SYNC(ptep); 4279 } 4280 pmap_release_page_lock(md); 4281 4282 out: 4283 kpreempt_enable(); 4284 return rv; 4285 } 4286 #endif 4287 4288 int 4289 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 4290 { 4291 struct l2_dtable *l2; 4292 struct l2_bucket *l2b; 4293 paddr_t pa; 4294 const size_t l1slot = l1pte_index(va); 4295 int rv = 0; 4296 4297 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4298 4299 va = trunc_page(va); 4300 4301 KASSERT(!user || (pm != pmap_kernel())); 4302 4303 UVMHIST_LOG(maphist, " (pm=%#jx, va=%#jx, ftype=%#jx, user=%jd)", 4304 (uintptr_t)pm, va, ftype, user); 4305 #ifdef ARM_MMU_EXTENDED 4306 UVMHIST_LOG(maphist, " ti=%#jx pai=%#jx asid=%#jx", 4307 (uintptr_t)cpu_tlb_info(curcpu()), 4308 (uintptr_t)PMAP_PAI(pm, cpu_tlb_info(curcpu())), 4309 (uintptr_t)PMAP_PAI(pm, cpu_tlb_info(curcpu()))->pai_asid, 0); 4310 #endif 4311 4312 pmap_acquire_pmap_lock(pm); 4313 4314 /* 4315 * If there is no l2_dtable for this address, then the process 4316 * has no business accessing it. 4317 * 4318 * Note: This will catch userland processes trying to access 4319 * kernel addresses. 4320 */ 4321 l2 = pm->pm_l2[L2_IDX(l1slot)]; 4322 if (l2 == NULL) { 4323 UVMHIST_LOG(maphist, " no l2 for l1slot %#jx", l1slot, 0, 0, 0); 4324 goto out; 4325 } 4326 4327 /* 4328 * Likewise if there is no L2 descriptor table 4329 */ 4330 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4331 if (l2b->l2b_kva == NULL) { 4332 UVMHIST_LOG(maphist, " <-- done (no ptep for l1slot %#jx)", 4333 l1slot, 0, 0, 0); 4334 goto out; 4335 } 4336 4337 /* 4338 * Check the PTE itself. 4339 */ 4340 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4341 pt_entry_t const opte = *ptep; 4342 if (opte == 0 || (opte & L2_TYPE_MASK) == L2_TYPE_L) { 4343 UVMHIST_LOG(maphist, " <-- done (empty pde for l1slot %#jx)", 4344 l1slot, 0, 0, 0); 4345 goto out; 4346 } 4347 4348 #ifndef ARM_HAS_VBAR 4349 /* 4350 * Catch a userland access to the vector page mapped at 0x0 4351 */ 4352 if (user && (opte & L2_S_PROT_U) == 0) { 4353 UVMHIST_LOG(maphist, " <-- done (vector_page)", 0, 0, 0, 0); 4354 goto out; 4355 } 4356 #endif 4357 4358 pa = l2pte_pa(opte); 4359 4360 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(opte)) { 4361 /* 4362 * This looks like a good candidate for "page modified" 4363 * emulation... 4364 */ 4365 struct pv_entry *pv; 4366 struct vm_page *pg; 4367 4368 /* Extract the physical address of the page */ 4369 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4370 UVMHIST_LOG(maphist, " <-- done (mod/ref unmanaged page)", 0, 0, 0, 0); 4371 goto out; 4372 } 4373 4374 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4375 4376 /* Get the current flags for this page. */ 4377 pmap_acquire_page_lock(md); 4378 pv = pmap_find_pv(md, pm, va); 4379 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4380 pmap_release_page_lock(md); 4381 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: no PV)", 0, 0, 0, 0); 4382 goto out; 4383 } 4384 4385 /* 4386 * Do the flags say this page is writable? If not then it 4387 * is a genuine write fault. If yes then the write fault is 4388 * our fault as we did not reflect the write access in the 4389 * PTE. Now we know a write has occurred we can correct this 4390 * and also set the modified bit 4391 */ 4392 if ((pv->pv_flags & PVF_WRITE) == 0) { 4393 pmap_release_page_lock(md); 4394 goto out; 4395 } 4396 4397 md->pvh_attrs |= PVF_REF | PVF_MOD; 4398 pv->pv_flags |= PVF_REF | PVF_MOD; 4399 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4400 /* 4401 * If there are cacheable mappings for this page, mark it dirty. 4402 */ 4403 if ((md->pvh_attrs & PVF_NC) == 0) 4404 md->pvh_attrs |= PVF_DIRTY; 4405 #endif 4406 #ifdef ARM_MMU_EXTENDED 4407 if (md->pvh_attrs & PVF_EXEC) { 4408 md->pvh_attrs &= ~PVF_EXEC; 4409 PMAPCOUNT(exec_discarded_modfixup); 4410 } 4411 #endif 4412 pmap_release_page_lock(md); 4413 4414 /* 4415 * Re-enable write permissions for the page. No need to call 4416 * pmap_vac_me_harder(), since this is just a 4417 * modified-emulation fault, and the PVF_WRITE bit isn't 4418 * changing. We've already set the cacheable bits based on 4419 * the assumption that we can write to this page. 4420 */ 4421 const pt_entry_t npte = 4422 l2pte_set_writable((opte & ~L2_TYPE_MASK) | L2_S_PROTO) 4423 #ifdef ARM_MMU_EXTENDED 4424 | (pm != pmap_kernel() ? L2_XS_nG : 0) 4425 #endif 4426 | 0; 4427 l2pte_reset(ptep); 4428 PTE_SYNC(ptep); 4429 pmap_tlb_flush_SE(pm, va, 4430 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4431 l2pte_set(ptep, npte, 0); 4432 PTE_SYNC(ptep); 4433 PMAPCOUNT(fixup_mod); 4434 rv = 1; 4435 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: changed pte " 4436 "from %#jx to %#jx)", opte, npte, 0, 0); 4437 } else if ((opte & L2_TYPE_MASK) == L2_TYPE_INV) { 4438 /* 4439 * This looks like a good candidate for "page referenced" 4440 * emulation. 4441 */ 4442 struct vm_page *pg; 4443 4444 /* Extract the physical address of the page */ 4445 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4446 UVMHIST_LOG(maphist, " <-- done (ref emul: unmanaged page)", 0, 0, 0, 0); 4447 goto out; 4448 } 4449 4450 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4451 4452 /* Get the current flags for this page. */ 4453 pmap_acquire_page_lock(md); 4454 struct pv_entry *pv = pmap_find_pv(md, pm, va); 4455 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4456 pmap_release_page_lock(md); 4457 UVMHIST_LOG(maphist, " <-- done (ref emul no PV)", 0, 0, 0, 0); 4458 goto out; 4459 } 4460 4461 md->pvh_attrs |= PVF_REF; 4462 pv->pv_flags |= PVF_REF; 4463 4464 pt_entry_t npte = 4465 l2pte_set_readonly((opte & ~L2_TYPE_MASK) | L2_S_PROTO); 4466 #ifdef ARM_MMU_EXTENDED 4467 if (pm != pmap_kernel()) { 4468 npte |= L2_XS_nG; 4469 } 4470 /* 4471 * If we got called from prefetch abort, then ftype will have 4472 * VM_PROT_EXECUTE set. Now see if we have no-execute set in 4473 * the PTE. 4474 */ 4475 if (user && (ftype & VM_PROT_EXECUTE) && (npte & L2_XS_XN)) { 4476 /* 4477 * Is this a mapping of an executable page? 4478 */ 4479 if ((pv->pv_flags & PVF_EXEC) == 0) { 4480 pmap_release_page_lock(md); 4481 UVMHIST_LOG(maphist, " <-- done (ref emul: no exec)", 4482 0, 0, 0, 0); 4483 goto out; 4484 } 4485 /* 4486 * If we haven't synced the page, do so now. 4487 */ 4488 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4489 UVMHIST_LOG(maphist, " ref emul: syncicache " 4490 "page #%#jx", pa, 0, 0, 0); 4491 pmap_syncicache_page(md, pa); 4492 PMAPCOUNT(fixup_exec); 4493 } 4494 npte &= ~L2_XS_XN; 4495 } 4496 #endif /* ARM_MMU_EXTENDED */ 4497 pmap_release_page_lock(md); 4498 l2pte_reset(ptep); 4499 PTE_SYNC(ptep); 4500 pmap_tlb_flush_SE(pm, va, 4501 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4502 l2pte_set(ptep, npte, 0); 4503 PTE_SYNC(ptep); 4504 PMAPCOUNT(fixup_ref); 4505 rv = 1; 4506 UVMHIST_LOG(maphist, " <-- done (ref emul: changed pte from " 4507 "%#jx to %#jx)", opte, npte, 0, 0); 4508 #ifdef ARM_MMU_EXTENDED 4509 } else if (user && (ftype & VM_PROT_EXECUTE) && (opte & L2_XS_XN)) { 4510 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4511 if (pg == NULL) { 4512 UVMHIST_LOG(maphist, " <-- done (unmanaged page)", 0, 0, 0, 0); 4513 goto out; 4514 } 4515 4516 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4517 4518 /* Get the current flags for this page. */ 4519 pmap_acquire_page_lock(md); 4520 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4521 if (pv == NULL || (pv->pv_flags & PVF_EXEC) == 0) { 4522 pmap_release_page_lock(md); 4523 UVMHIST_LOG(maphist, " <-- done (no PV or not EXEC)", 0, 0, 0, 0); 4524 goto out; 4525 } 4526 4527 /* 4528 * If we haven't synced the page, do so now. 4529 */ 4530 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4531 UVMHIST_LOG(maphist, "syncicache page #%#jx", 4532 pa, 0, 0, 0); 4533 pmap_syncicache_page(md, pa); 4534 } 4535 pmap_release_page_lock(md); 4536 /* 4537 * Turn off no-execute. 4538 */ 4539 KASSERT(opte & L2_XS_nG); 4540 l2pte_reset(ptep); 4541 PTE_SYNC(ptep); 4542 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4543 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4544 PTE_SYNC(ptep); 4545 rv = 1; 4546 PMAPCOUNT(fixup_exec); 4547 UVMHIST_LOG(maphist, "exec: changed pte from %#jx to %#jx", 4548 opte, opte & ~L2_XS_XN, 0, 0); 4549 #endif 4550 } 4551 4552 #ifndef ARM_MMU_EXTENDED 4553 /* 4554 * We know there is a valid mapping here, so simply 4555 * fix up the L1 if necessary. 4556 */ 4557 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 4558 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa | L1_C_DOM(pmap_domain(pm)); 4559 if (*pdep != pde) { 4560 l1pte_setone(pdep, pde); 4561 PDE_SYNC(pdep); 4562 rv = 1; 4563 PMAPCOUNT(fixup_pdes); 4564 } 4565 #endif 4566 4567 #ifdef CPU_SA110 4568 /* 4569 * There are bugs in the rev K SA110. This is a check for one 4570 * of them. 4571 */ 4572 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 4573 curcpu()->ci_arm_cpurev < 3) { 4574 /* Always current pmap */ 4575 if (l2pte_valid_p(opte)) { 4576 extern int kernel_debug; 4577 if (kernel_debug & 1) { 4578 struct proc *p = curlwp->l_proc; 4579 printf("prefetch_abort: page is already " 4580 "mapped - pte=%p *pte=%08x\n", ptep, opte); 4581 printf("prefetch_abort: pc=%08lx proc=%p " 4582 "process=%s\n", va, p, p->p_comm); 4583 printf("prefetch_abort: far=%08x fs=%x\n", 4584 cpu_faultaddress(), cpu_faultstatus()); 4585 } 4586 #ifdef DDB 4587 if (kernel_debug & 2) 4588 Debugger(); 4589 #endif 4590 rv = 1; 4591 } 4592 } 4593 #endif /* CPU_SA110 */ 4594 4595 #ifndef ARM_MMU_EXTENDED 4596 /* 4597 * If 'rv == 0' at this point, it generally indicates that there is a 4598 * stale TLB entry for the faulting address. That might be due to a 4599 * wrong setting of pmap_needs_pte_sync. So set it and retry. 4600 */ 4601 if (rv == 0 4602 && pm->pm_l1->l1_domain_use_count == 1 4603 && pmap_needs_pte_sync == 0) { 4604 pmap_needs_pte_sync = 1; 4605 PTE_SYNC(ptep); 4606 PMAPCOUNT(fixup_ptesync); 4607 rv = 1; 4608 } 4609 #endif 4610 4611 #ifndef MULTIPROCESSOR 4612 #if defined(DEBUG) || 1 4613 /* 4614 * If 'rv == 0' at this point, it generally indicates that there is a 4615 * stale TLB entry for the faulting address. This happens when two or 4616 * more processes are sharing an L1. Since we don't flush the TLB on 4617 * a context switch between such processes, we can take domain faults 4618 * for mappings which exist at the same VA in both processes. EVEN IF 4619 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4620 * example. 4621 * 4622 * This is extremely likely to happen if pmap_enter() updated the L1 4623 * entry for a recently entered mapping. In this case, the TLB is 4624 * flushed for the new mapping, but there may still be TLB entries for 4625 * other mappings belonging to other processes in the 1MB range 4626 * covered by the L1 entry. 4627 * 4628 * Since 'rv == 0', we know that the L1 already contains the correct 4629 * value, so the fault must be due to a stale TLB entry. 4630 * 4631 * Since we always need to flush the TLB anyway in the case where we 4632 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4633 * stale TLB entries dynamically. 4634 * 4635 * However, the above condition can ONLY happen if the current L1 is 4636 * being shared. If it happens when the L1 is unshared, it indicates 4637 * that other parts of the pmap are not doing their job WRT managing 4638 * the TLB. 4639 */ 4640 if (rv == 0 4641 #ifndef ARM_MMU_EXTENDED 4642 && pm->pm_l1->l1_domain_use_count == 1 4643 #endif 4644 && true) { 4645 #ifdef DEBUG 4646 extern int last_fault_code; 4647 #else 4648 int last_fault_code = ftype & VM_PROT_EXECUTE 4649 ? armreg_ifsr_read() 4650 : armreg_dfsr_read(); 4651 #endif 4652 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4653 pm, va, ftype); 4654 printf("fixup: l2 %p, l2b %p, ptep %p, pte %#x\n", 4655 l2, l2b, ptep, opte); 4656 4657 #ifndef ARM_MMU_EXTENDED 4658 printf("fixup: pdep %p, pde %#x, fsr %#x\n", 4659 pdep, pde, last_fault_code); 4660 #else 4661 printf("fixup: pdep %p, pde %#x, ttbcr %#x\n", 4662 &pmap_l1_kva(pm)[l1slot], pmap_l1_kva(pm)[l1slot], 4663 armreg_ttbcr_read()); 4664 printf("fixup: fsr %#x cpm %p casid %#x contextidr %#x dacr %#x\n", 4665 last_fault_code, curcpu()->ci_pmap_cur, 4666 curcpu()->ci_pmap_asid_cur, 4667 armreg_contextidr_read(), armreg_dacr_read()); 4668 #ifdef _ARM_ARCH_7 4669 if (ftype & VM_PROT_WRITE) 4670 armreg_ats1cuw_write(va); 4671 else 4672 armreg_ats1cur_write(va); 4673 arm_isb(); 4674 printf("fixup: par %#x\n", armreg_par_read()); 4675 #endif 4676 #endif 4677 #ifdef DDB 4678 extern int kernel_debug; 4679 4680 if (kernel_debug & 2) { 4681 pmap_release_pmap_lock(pm); 4682 #ifdef UVMHIST 4683 KERNHIST_DUMP(maphist); 4684 #endif 4685 cpu_Debugger(); 4686 pmap_acquire_pmap_lock(pm); 4687 } 4688 #endif 4689 } 4690 #endif 4691 #endif 4692 4693 #ifndef ARM_MMU_EXTENDED 4694 /* Flush the TLB in the shared L1 case - see comment above */ 4695 pmap_tlb_flush_SE(pm, va, 4696 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4697 #endif 4698 4699 rv = 1; 4700 4701 out: 4702 pmap_release_pmap_lock(pm); 4703 4704 return (rv); 4705 } 4706 4707 /* 4708 * Routine: pmap_procwr 4709 * 4710 * Function: 4711 * Synchronize caches corresponding to [addr, addr+len) in p. 4712 * 4713 */ 4714 void 4715 pmap_procwr(struct proc *p, vaddr_t va, int len) 4716 { 4717 #ifndef ARM_MMU_EXTENDED 4718 4719 /* We only need to do anything if it is the current process. */ 4720 if (p == curproc) 4721 cpu_icache_sync_range(va, len); 4722 #endif 4723 } 4724 4725 /* 4726 * Routine: pmap_unwire 4727 * Function: Clear the wired attribute for a map/virtual-address pair. 4728 * 4729 * In/out conditions: 4730 * The mapping must already exist in the pmap. 4731 */ 4732 void 4733 pmap_unwire(pmap_t pm, vaddr_t va) 4734 { 4735 struct l2_bucket *l2b; 4736 pt_entry_t *ptep, pte; 4737 struct vm_page *pg; 4738 paddr_t pa; 4739 4740 NPDEBUG(PDB_WIRING, printf("pmap_unwire: pm %p, va 0x%08lx\n", pm, va)); 4741 4742 pmap_acquire_pmap_lock(pm); 4743 4744 l2b = pmap_get_l2_bucket(pm, va); 4745 KDASSERT(l2b != NULL); 4746 4747 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4748 pte = *ptep; 4749 4750 /* Extract the physical address of the page */ 4751 pa = l2pte_pa(pte); 4752 4753 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4754 /* Update the wired bit in the pv entry for this page. */ 4755 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4756 4757 pmap_acquire_page_lock(md); 4758 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4759 pmap_release_page_lock(md); 4760 } 4761 4762 pmap_release_pmap_lock(pm); 4763 } 4764 4765 #ifdef ARM_MMU_EXTENDED 4766 void 4767 pmap_md_pdetab_activate(pmap_t pm, struct lwp *l) 4768 { 4769 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4770 4771 /* 4772 * Assume that TTBR1 has only global mappings and TTBR0 only 4773 * has non-global mappings. To prevent speculation from doing 4774 * evil things we disable translation table walks using TTBR0 4775 * before setting the CONTEXTIDR (ASID) or new TTBR0 value. 4776 * Once both are set, table walks are reenabled. 4777 */ 4778 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4779 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4780 arm_isb(); 4781 4782 pmap_tlb_asid_acquire(pm, l); 4783 4784 struct cpu_info * const ci = curcpu(); 4785 struct pmap_asid_info * const pai = PMAP_PAI(pm, cpu_tlb_info(ci)); 4786 4787 cpu_setttb(pm->pm_l1_pa, pai->pai_asid); 4788 /* 4789 * Now we can reenable tablewalks since the CONTEXTIDR and TTRB0 4790 * have been updated. 4791 */ 4792 arm_isb(); 4793 4794 if (pm != pmap_kernel()) { 4795 armreg_ttbcr_write(old_ttbcr & ~TTBCR_S_PD0); 4796 } 4797 cpu_cpwait(); 4798 4799 UVMHIST_LOG(maphist, " pm %#jx pm->pm_l1_pa %08jx asid %ju... done", 4800 (uintptr_t)pm, pm->pm_l1_pa, pai->pai_asid, 0); 4801 4802 KASSERTMSG(ci->ci_pmap_asid_cur == pai->pai_asid, "%u vs %u", 4803 ci->ci_pmap_asid_cur, pai->pai_asid); 4804 ci->ci_pmap_cur = pm; 4805 } 4806 4807 void 4808 pmap_md_pdetab_deactivate(pmap_t pm) 4809 { 4810 4811 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4812 4813 kpreempt_disable(); 4814 struct cpu_info * const ci = curcpu(); 4815 /* 4816 * Disable translation table walks from TTBR0 while no pmap has been 4817 * activated. 4818 */ 4819 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4820 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4821 arm_isb(); 4822 pmap_tlb_asid_deactivate(pm); 4823 cpu_setttb(pmap_kernel()->pm_l1_pa, KERNEL_PID); 4824 arm_isb(); 4825 4826 ci->ci_pmap_cur = pmap_kernel(); 4827 KASSERTMSG(ci->ci_pmap_asid_cur == KERNEL_PID, "ci_pmap_asid_cur %u", 4828 ci->ci_pmap_asid_cur); 4829 kpreempt_enable(); 4830 } 4831 #endif 4832 4833 void 4834 pmap_activate(struct lwp *l) 4835 { 4836 extern int block_userspace_access; 4837 pmap_t npm = l->l_proc->p_vmspace->vm_map.pmap; 4838 4839 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4840 4841 UVMHIST_LOG(maphist, "(l=%#jx) pm=%#jx", (uintptr_t)l, (uintptr_t)npm, 4842 0, 0); 4843 4844 struct cpu_info * const ci = curcpu(); 4845 4846 /* 4847 * If activating a non-current lwp or the current lwp is 4848 * already active, just return. 4849 */ 4850 if (false 4851 || l != curlwp 4852 #ifdef ARM_MMU_EXTENDED 4853 || (ci->ci_pmap_cur == npm && 4854 (npm == pmap_kernel() 4855 /* || PMAP_PAI_ASIDVALID_P(pai, cpu_tlb_info(ci)) */)) 4856 #else 4857 || npm->pm_activated == true 4858 #endif 4859 || false) { 4860 UVMHIST_LOG(maphist, " <-- (same pmap)", (uintptr_t)curlwp, 4861 (uintptr_t)l, 0, 0); 4862 return; 4863 } 4864 4865 #ifndef ARM_MMU_EXTENDED 4866 const uint32_t ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4867 | (DOMAIN_CLIENT << (pmap_domain(npm) * 2)); 4868 4869 /* 4870 * If TTB and DACR are unchanged, short-circuit all the 4871 * TLB/cache management stuff. 4872 */ 4873 pmap_t opm = ci->ci_lastlwp 4874 ? ci->ci_lastlwp->l_proc->p_vmspace->vm_map.pmap 4875 : NULL; 4876 if (opm != NULL) { 4877 uint32_t odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 4878 | (DOMAIN_CLIENT << (pmap_domain(opm) * 2)); 4879 4880 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 4881 goto all_done; 4882 } 4883 #endif /* !ARM_MMU_EXTENDED */ 4884 4885 PMAPCOUNT(activations); 4886 block_userspace_access = 1; 4887 4888 #ifndef ARM_MMU_EXTENDED 4889 /* 4890 * If switching to a user vmspace which is different to the 4891 * most recent one, and the most recent one is potentially 4892 * live in the cache, we must write-back and invalidate the 4893 * entire cache. 4894 */ 4895 pmap_t rpm = ci->ci_pmap_lastuser; 4896 4897 /* 4898 * XXXSCW: There's a corner case here which can leave turds in the 4899 * cache as reported in kern/41058. They're probably left over during 4900 * tear-down and switching away from an exiting process. Until the root 4901 * cause is identified and fixed, zap the cache when switching pmaps. 4902 * This will result in a few unnecessary cache flushes, but that's 4903 * better than silently corrupting data. 4904 */ 4905 #if 0 4906 if (npm != pmap_kernel() && rpm && npm != rpm && 4907 rpm->pm_cstate.cs_cache) { 4908 rpm->pm_cstate.cs_cache = 0; 4909 #ifdef PMAP_CACHE_VIVT 4910 cpu_idcache_wbinv_all(); 4911 #endif 4912 } 4913 #else 4914 if (rpm) { 4915 rpm->pm_cstate.cs_cache = 0; 4916 if (npm == pmap_kernel()) 4917 ci->ci_pmap_lastuser = NULL; 4918 #ifdef PMAP_CACHE_VIVT 4919 cpu_idcache_wbinv_all(); 4920 #endif 4921 } 4922 #endif 4923 4924 /* No interrupts while we frob the TTB/DACR */ 4925 uint32_t oldirqstate = disable_interrupts(IF32_bits); 4926 #endif /* !ARM_MMU_EXTENDED */ 4927 4928 #ifndef ARM_HAS_VBAR 4929 /* 4930 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 4931 * entry corresponding to 'vector_page' in the incoming L1 table 4932 * before switching to it otherwise subsequent interrupts/exceptions 4933 * (including domain faults!) will jump into hyperspace. 4934 */ 4935 if (npm->pm_pl1vec != NULL) { 4936 cpu_tlb_flushID_SE((u_int)vector_page); 4937 cpu_cpwait(); 4938 *npm->pm_pl1vec = npm->pm_l1vec; 4939 PTE_SYNC(npm->pm_pl1vec); 4940 } 4941 #endif 4942 4943 #ifdef ARM_MMU_EXTENDED 4944 pmap_md_pdetab_activate(npm, l); 4945 #else 4946 cpu_domains(ndacr); 4947 if (npm == pmap_kernel() || npm == rpm) { 4948 /* 4949 * Switching to a kernel thread, or back to the 4950 * same user vmspace as before... Simply update 4951 * the TTB (no TLB flush required) 4952 */ 4953 cpu_setttb(npm->pm_l1->l1_physaddr, false); 4954 cpu_cpwait(); 4955 } else { 4956 /* 4957 * Otherwise, update TTB and flush TLB 4958 */ 4959 cpu_context_switch(npm->pm_l1->l1_physaddr); 4960 if (rpm != NULL) 4961 rpm->pm_cstate.cs_tlb = 0; 4962 } 4963 4964 restore_interrupts(oldirqstate); 4965 #endif /* ARM_MMU_EXTENDED */ 4966 4967 block_userspace_access = 0; 4968 4969 #ifndef ARM_MMU_EXTENDED 4970 all_done: 4971 /* 4972 * The new pmap is resident. Make sure it's marked 4973 * as resident in the cache/TLB. 4974 */ 4975 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 4976 if (npm != pmap_kernel()) 4977 ci->ci_pmap_lastuser = npm; 4978 4979 /* The old pmap is not longer active */ 4980 if (opm != npm) { 4981 if (opm != NULL) 4982 opm->pm_activated = false; 4983 4984 /* But the new one is */ 4985 npm->pm_activated = true; 4986 } 4987 ci->ci_pmap_cur = npm; 4988 #endif 4989 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4990 } 4991 4992 void 4993 pmap_deactivate(struct lwp *l) 4994 { 4995 pmap_t pm = l->l_proc->p_vmspace->vm_map.pmap; 4996 4997 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 4998 4999 UVMHIST_LOG(maphist, "(l=%#jx) pm=%#jx", (uintptr_t)l, (uintptr_t)pm, 5000 0, 0); 5001 5002 #ifdef ARM_MMU_EXTENDED 5003 pmap_md_pdetab_deactivate(pm); 5004 #else 5005 /* 5006 * If the process is exiting, make sure pmap_activate() does 5007 * a full MMU context-switch and cache flush, which we might 5008 * otherwise skip. See PR port-arm/38950. 5009 */ 5010 if (l->l_proc->p_sflag & PS_WEXIT) 5011 curcpu()->ci_lastlwp = NULL; 5012 5013 pm->pm_activated = false; 5014 #endif 5015 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5016 } 5017 5018 void 5019 pmap_update(pmap_t pm) 5020 { 5021 5022 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 5023 5024 UVMHIST_LOG(maphist, "pm=%#jx remove_all %jd", (uintptr_t)pm, 5025 pm->pm_remove_all, 0, 0); 5026 5027 #ifndef ARM_MMU_EXTENDED 5028 if (pm->pm_remove_all) { 5029 /* 5030 * Finish up the pmap_remove_all() optimisation by flushing 5031 * the TLB. 5032 */ 5033 pmap_tlb_flushID(pm); 5034 pm->pm_remove_all = false; 5035 } 5036 5037 if (pmap_is_current(pm)) { 5038 /* 5039 * If we're dealing with a current userland pmap, move its L1 5040 * to the end of the LRU. 5041 */ 5042 if (pm != pmap_kernel()) 5043 pmap_use_l1(pm); 5044 5045 /* 5046 * We can assume we're done with frobbing the cache/tlb for 5047 * now. Make sure any future pmap ops don't skip cache/tlb 5048 * flushes. 5049 */ 5050 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5051 } 5052 #else 5053 5054 kpreempt_disable(); 5055 #if defined(MULTIPROCESSOR) && PMAP_TLB_MAX > 1 5056 u_int pending = atomic_swap_uint(&pmap->pm_shootdown_pending, 0); 5057 if (pending && pmap_tlb_shootdown_bystanders(pmap)) { 5058 PMAP_COUNT(shootdown_ipis); 5059 } 5060 #endif 5061 5062 /* 5063 * If pmap_remove_all was called, we deactivated ourselves and released 5064 * our ASID. Now we have to reactivate ourselves. 5065 */ 5066 if (__predict_false(pm->pm_remove_all)) { 5067 pm->pm_remove_all = false; 5068 5069 KASSERT(pm != pmap_kernel()); 5070 pmap_md_pdetab_activate(pm, curlwp); 5071 } 5072 5073 if (arm_has_mpext_p) 5074 armreg_bpiallis_write(0); 5075 else 5076 armreg_bpiall_write(0); 5077 5078 kpreempt_enable(); 5079 5080 KASSERTMSG(pm == pmap_kernel() 5081 || curcpu()->ci_pmap_cur != pm 5082 || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, 5083 "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, 5084 pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, 5085 curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 5086 #endif 5087 5088 PMAPCOUNT(updates); 5089 5090 /* 5091 * make sure TLB/cache operations have completed. 5092 */ 5093 cpu_cpwait(); 5094 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5095 } 5096 5097 void 5098 pmap_remove_all(pmap_t pm) 5099 { 5100 5101 /* 5102 * The vmspace described by this pmap is about to be torn down. 5103 * Until pmap_update() is called, UVM will only make calls 5104 * to pmap_remove(). We can make life much simpler by flushing 5105 * the cache now, and deferring TLB invalidation to pmap_update(). 5106 */ 5107 #ifdef PMAP_CACHE_VIVT 5108 pmap_cache_wbinv_all(pm, PVF_EXEC); 5109 #endif 5110 #ifdef ARM_MMU_EXTENDED 5111 #ifdef MULTIPROCESSOR 5112 struct cpu_info * const ci = curcpu(); 5113 // This should be the last CPU with this pmap onproc 5114 KASSERT(!kcpuset_isotherset(pm->pm_onproc, cpu_index(ci))); 5115 if (kcpuset_isset(pm->pm_onproc, cpu_index(ci))) 5116 #endif 5117 pmap_tlb_asid_deactivate(pm); 5118 #ifdef MULTIPROCESSOR 5119 KASSERT(kcpuset_iszero(pm->pm_onproc)); 5120 #endif 5121 5122 pmap_tlb_asid_release_all(pm); 5123 #endif 5124 pm->pm_remove_all = true; 5125 } 5126 5127 /* 5128 * Retire the given physical map from service. 5129 * Should only be called if the map contains no valid mappings. 5130 */ 5131 void 5132 pmap_destroy(pmap_t pm) 5133 { 5134 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 5135 5136 u_int count; 5137 5138 if (pm == NULL) 5139 return; 5140 5141 UVMHIST_LOG(maphist, "pm=%#jx remove_all %jd", (uintptr_t)pm, 5142 pm->pm_remove_all, 0, 0); 5143 5144 if (pm->pm_remove_all) { 5145 #ifdef ARM_MMU_EXTENDED 5146 pmap_tlb_asid_release_all(pm); 5147 #else 5148 pmap_tlb_flushID(pm); 5149 #endif 5150 pm->pm_remove_all = false; 5151 } 5152 5153 /* 5154 * Drop reference count 5155 */ 5156 mutex_enter(pm->pm_lock); 5157 count = --pm->pm_obj.uo_refs; 5158 mutex_exit(pm->pm_lock); 5159 if (count > 0) { 5160 #ifndef ARM_MMU_EXTENDED 5161 if (pmap_is_current(pm)) { 5162 if (pm != pmap_kernel()) 5163 pmap_use_l1(pm); 5164 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5165 } 5166 #endif 5167 return; 5168 } 5169 5170 /* 5171 * reference count is zero, free pmap resources and then free pmap. 5172 */ 5173 5174 #ifndef ARM_HAS_VBAR 5175 if (vector_page < KERNEL_BASE) { 5176 KDASSERT(!pmap_is_current(pm)); 5177 5178 /* Remove the vector page mapping */ 5179 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 5180 pmap_update(pm); 5181 } 5182 #endif 5183 5184 pmap_free_l1(pm); 5185 5186 #ifdef ARM_MMU_EXTENDED 5187 #ifdef MULTIPROCESSOR 5188 kcpuset_destroy(pm->pm_active); 5189 kcpuset_destroy(pm->pm_onproc); 5190 #endif 5191 #else 5192 struct cpu_info * const ci = curcpu(); 5193 if (ci->ci_pmap_lastuser == pm) 5194 ci->ci_pmap_lastuser = NULL; 5195 #endif 5196 5197 uvm_obj_destroy(&pm->pm_obj, false); 5198 mutex_destroy(&pm->pm_obj_lock); 5199 pool_cache_put(&pmap_cache, pm); 5200 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5201 } 5202 5203 5204 /* 5205 * void pmap_reference(pmap_t pm) 5206 * 5207 * Add a reference to the specified pmap. 5208 */ 5209 void 5210 pmap_reference(pmap_t pm) 5211 { 5212 5213 if (pm == NULL) 5214 return; 5215 5216 #ifndef ARM_MMU_EXTENDED 5217 pmap_use_l1(pm); 5218 #endif 5219 5220 mutex_enter(pm->pm_lock); 5221 pm->pm_obj.uo_refs++; 5222 mutex_exit(pm->pm_lock); 5223 } 5224 5225 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 5226 5227 static struct evcnt pmap_prefer_nochange_ev = 5228 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 5229 static struct evcnt pmap_prefer_change_ev = 5230 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 5231 5232 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 5233 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 5234 5235 void 5236 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 5237 { 5238 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 5239 vaddr_t va = *vap; 5240 vaddr_t diff = (hint - va) & mask; 5241 if (diff == 0) { 5242 pmap_prefer_nochange_ev.ev_count++; 5243 } else { 5244 pmap_prefer_change_ev.ev_count++; 5245 if (__predict_false(td)) 5246 va -= mask + 1; 5247 *vap = va + diff; 5248 } 5249 } 5250 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 5251 5252 /* 5253 * pmap_zero_page() 5254 * 5255 * Zero a given physical page by mapping it at a page hook point. 5256 * In doing the zero page op, the page we zero is mapped cachable, as with 5257 * StrongARM accesses to non-cached pages are non-burst making writing 5258 * _any_ bulk data very slow. 5259 */ 5260 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5261 void 5262 pmap_zero_page_generic(paddr_t pa) 5263 { 5264 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5265 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5266 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5267 #endif 5268 #if defined(PMAP_CACHE_VIPT) 5269 /* Choose the last page color it had, if any */ 5270 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5271 #else 5272 const vsize_t va_offset = 0; 5273 #endif 5274 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5275 /* 5276 * Is this page mapped at its natural color? 5277 * If we have all of memory mapped, then just convert PA to VA. 5278 */ 5279 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5280 || va_offset == (pa & arm_cache_prefer_mask); 5281 const vaddr_t vdstp = okcolor 5282 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5283 : cpu_cdstp(va_offset); 5284 #else 5285 const bool okcolor = false; 5286 const vaddr_t vdstp = cpu_cdstp(va_offset); 5287 #endif 5288 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5289 5290 5291 #ifdef DEBUG 5292 if (!SLIST_EMPTY(&md->pvh_list)) 5293 panic("pmap_zero_page: page has mappings"); 5294 #endif 5295 5296 KDASSERT((pa & PGOFSET) == 0); 5297 5298 if (!okcolor) { 5299 /* 5300 * Hook in the page, zero it, and purge the cache for that 5301 * zeroed page. Invalidate the TLB as needed. 5302 */ 5303 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 5304 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE); 5305 l2pte_set(ptep, npte, 0); 5306 PTE_SYNC(ptep); 5307 cpu_tlb_flushD_SE(vdstp); 5308 cpu_cpwait(); 5309 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) \ 5310 && !defined(ARM_MMU_EXTENDED) 5311 /* 5312 * If we are direct-mapped and our color isn't ok, then before 5313 * we bzero the page invalidate its contents from the cache and 5314 * reset the color to its natural color. 5315 */ 5316 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5317 md->pvh_attrs &= ~arm_cache_prefer_mask; 5318 md->pvh_attrs |= (pa & arm_cache_prefer_mask); 5319 #endif 5320 } 5321 bzero_page(vdstp); 5322 if (!okcolor) { 5323 /* 5324 * Unmap the page. 5325 */ 5326 l2pte_reset(ptep); 5327 PTE_SYNC(ptep); 5328 cpu_tlb_flushD_SE(vdstp); 5329 #ifdef PMAP_CACHE_VIVT 5330 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5331 #endif 5332 } 5333 #ifdef PMAP_CACHE_VIPT 5334 /* 5335 * This page is now cache resident so it now has a page color. 5336 * Any contents have been obliterated so clear the EXEC flag. 5337 */ 5338 #ifndef ARM_MMU_EXTENDED 5339 if (!pmap_is_page_colored_p(md)) { 5340 PMAPCOUNT(vac_color_new); 5341 md->pvh_attrs |= PVF_COLORED; 5342 } 5343 md->pvh_attrs |= PVF_DIRTY; 5344 #endif 5345 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5346 md->pvh_attrs &= ~PVF_EXEC; 5347 PMAPCOUNT(exec_discarded_zero); 5348 } 5349 #endif 5350 } 5351 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5352 5353 #if ARM_MMU_XSCALE == 1 5354 void 5355 pmap_zero_page_xscale(paddr_t pa) 5356 { 5357 #ifdef DEBUG 5358 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5359 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5360 5361 if (!SLIST_EMPTY(&md->pvh_list)) 5362 panic("pmap_zero_page: page has mappings"); 5363 #endif 5364 5365 KDASSERT((pa & PGOFSET) == 0); 5366 5367 /* 5368 * Hook in the page, zero it, and purge the cache for that 5369 * zeroed page. Invalidate the TLB as needed. 5370 */ 5371 5372 pt_entry_t npte = L2_S_PROTO | pa | 5373 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 5374 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5375 l2pte_set(cdst_pte, npte, 0); 5376 PTE_SYNC(cdst_pte); 5377 cpu_tlb_flushD_SE(cdstp); 5378 cpu_cpwait(); 5379 bzero_page(cdstp); 5380 xscale_cache_clean_minidata(); 5381 l2pte_reset(cdst_pte); 5382 PTE_SYNC(cdst_pte); 5383 } 5384 #endif /* ARM_MMU_XSCALE == 1 */ 5385 5386 /* pmap_pageidlezero() 5387 * 5388 * The same as above, except that we assume that the page is not 5389 * mapped. This means we never have to flush the cache first. Called 5390 * from the idle loop. 5391 */ 5392 bool 5393 pmap_pageidlezero(paddr_t pa) 5394 { 5395 bool rv = true; 5396 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5397 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 5398 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5399 #endif 5400 #ifdef PMAP_CACHE_VIPT 5401 /* Choose the last page color it had, if any */ 5402 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5403 #else 5404 const vsize_t va_offset = 0; 5405 #endif 5406 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 5407 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5408 || va_offset == (pa & arm_cache_prefer_mask); 5409 const vaddr_t vdstp = okcolor 5410 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5411 : cpu_cdstp(va_offset); 5412 #else 5413 const bool okcolor = false; 5414 const vaddr_t vdstp = cpu_cdstp(va_offset); 5415 #endif 5416 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5417 5418 5419 #ifdef DEBUG 5420 if (!SLIST_EMPTY(&md->pvh_list)) 5421 panic("pmap_pageidlezero: page has mappings"); 5422 #endif 5423 5424 KDASSERT((pa & PGOFSET) == 0); 5425 5426 if (!okcolor) { 5427 /* 5428 * Hook in the page, zero it, and purge the cache for that 5429 * zeroed page. Invalidate the TLB as needed. 5430 */ 5431 const pt_entry_t npte = L2_S_PROTO | pa | 5432 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5433 l2pte_set(ptep, npte, 0); 5434 PTE_SYNC(ptep); 5435 cpu_tlb_flushD_SE(vdstp); 5436 cpu_cpwait(); 5437 } 5438 5439 uint64_t *ptr = (uint64_t *)vdstp; 5440 for (size_t i = 0; i < PAGE_SIZE / sizeof(*ptr); i++) { 5441 if (sched_curcpu_runnable_p() != 0) { 5442 /* 5443 * A process has become ready. Abort now, 5444 * so we don't keep it waiting while we 5445 * do slow memory access to finish this 5446 * page. 5447 */ 5448 rv = false; 5449 break; 5450 } 5451 *ptr++ = 0; 5452 } 5453 5454 #ifdef PMAP_CACHE_VIVT 5455 if (rv) 5456 /* 5457 * if we aborted we'll rezero this page again later so don't 5458 * purge it unless we finished it 5459 */ 5460 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5461 #elif defined(PMAP_CACHE_VIPT) 5462 /* 5463 * This page is now cache resident so it now has a page color. 5464 * Any contents have been obliterated so clear the EXEC flag. 5465 */ 5466 #ifndef ARM_MMU_EXTENDED 5467 if (!pmap_is_page_colored_p(md)) { 5468 PMAPCOUNT(vac_color_new); 5469 md->pvh_attrs |= PVF_COLORED; 5470 } 5471 #endif 5472 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5473 md->pvh_attrs &= ~PVF_EXEC; 5474 PMAPCOUNT(exec_discarded_zero); 5475 } 5476 #endif 5477 /* 5478 * Unmap the page. 5479 */ 5480 if (!okcolor) { 5481 l2pte_reset(ptep); 5482 PTE_SYNC(ptep); 5483 cpu_tlb_flushD_SE(vdstp); 5484 } 5485 5486 return rv; 5487 } 5488 5489 /* 5490 * pmap_copy_page() 5491 * 5492 * Copy one physical page into another, by mapping the pages into 5493 * hook points. The same comment regarding cachability as in 5494 * pmap_zero_page also applies here. 5495 */ 5496 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5497 void 5498 pmap_copy_page_generic(paddr_t src, paddr_t dst) 5499 { 5500 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 5501 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5502 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5503 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 5504 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 5505 #endif 5506 #ifdef PMAP_CACHE_VIPT 5507 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 5508 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 5509 #else 5510 const vsize_t src_va_offset = 0; 5511 const vsize_t dst_va_offset = 0; 5512 #endif 5513 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5514 /* 5515 * Is this page mapped at its natural color? 5516 * If we have all of memory mapped, then just convert PA to VA. 5517 */ 5518 bool src_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5519 || src_va_offset == (src & arm_cache_prefer_mask); 5520 bool dst_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5521 || dst_va_offset == (dst & arm_cache_prefer_mask); 5522 const vaddr_t vsrcp = src_okcolor 5523 ? pmap_direct_mapped_phys(src, &src_okcolor, 5524 cpu_csrcp(src_va_offset)) 5525 : cpu_csrcp(src_va_offset); 5526 const vaddr_t vdstp = pmap_direct_mapped_phys(dst, &dst_okcolor, 5527 cpu_cdstp(dst_va_offset)); 5528 #else 5529 const bool src_okcolor = false; 5530 const bool dst_okcolor = false; 5531 const vaddr_t vsrcp = cpu_csrcp(src_va_offset); 5532 const vaddr_t vdstp = cpu_cdstp(dst_va_offset); 5533 #endif 5534 pt_entry_t * const src_ptep = cpu_csrc_pte(src_va_offset); 5535 pt_entry_t * const dst_ptep = cpu_cdst_pte(dst_va_offset); 5536 5537 #ifdef DEBUG 5538 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5539 panic("pmap_copy_page: dst page has mappings"); 5540 #endif 5541 5542 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5543 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 5544 #endif 5545 KDASSERT((src & PGOFSET) == 0); 5546 KDASSERT((dst & PGOFSET) == 0); 5547 5548 /* 5549 * Clean the source page. Hold the source page's lock for 5550 * the duration of the copy so that no other mappings can 5551 * be created while we have a potentially aliased mapping. 5552 */ 5553 #ifdef PMAP_CACHE_VIVT 5554 pmap_acquire_page_lock(src_md); 5555 (void) pmap_clean_page(src_md, true); 5556 pmap_release_page_lock(src_md); 5557 #endif 5558 5559 /* 5560 * Map the pages into the page hook points, copy them, and purge 5561 * the cache for the appropriate page. Invalidate the TLB 5562 * as required. 5563 */ 5564 if (!src_okcolor) { 5565 const pt_entry_t nsrc_pte = L2_S_PROTO 5566 | src 5567 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5568 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 5569 #else // defined(PMAP_CACHE_VIVT) || defined(ARM_MMU_EXTENDED) 5570 | pte_l2_s_cache_mode 5571 #endif 5572 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 5573 l2pte_set(src_ptep, nsrc_pte, 0); 5574 PTE_SYNC(src_ptep); 5575 cpu_tlb_flushD_SE(vsrcp); 5576 cpu_cpwait(); 5577 } 5578 if (!dst_okcolor) { 5579 const pt_entry_t ndst_pte = L2_S_PROTO | dst | 5580 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5581 l2pte_set(dst_ptep, ndst_pte, 0); 5582 PTE_SYNC(dst_ptep); 5583 cpu_tlb_flushD_SE(vdstp); 5584 cpu_cpwait(); 5585 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 5586 /* 5587 * If we are direct-mapped and our color isn't ok, then before 5588 * we bcopy to the new page invalidate its contents from the 5589 * cache and reset its color to its natural color. 5590 */ 5591 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5592 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5593 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5594 #endif 5595 } 5596 bcopy_page(vsrcp, vdstp); 5597 #ifdef PMAP_CACHE_VIVT 5598 cpu_dcache_inv_range(vsrcp, PAGE_SIZE); 5599 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5600 #endif 5601 /* 5602 * Unmap the pages. 5603 */ 5604 if (!src_okcolor) { 5605 l2pte_reset(src_ptep); 5606 PTE_SYNC(src_ptep); 5607 cpu_tlb_flushD_SE(vsrcp); 5608 cpu_cpwait(); 5609 } 5610 if (!dst_okcolor) { 5611 l2pte_reset(dst_ptep); 5612 PTE_SYNC(dst_ptep); 5613 cpu_tlb_flushD_SE(vdstp); 5614 cpu_cpwait(); 5615 } 5616 #ifdef PMAP_CACHE_VIPT 5617 /* 5618 * Now that the destination page is in the cache, mark it as colored. 5619 * If this was an exec page, discard it. 5620 */ 5621 pmap_acquire_page_lock(dst_md); 5622 #ifndef ARM_MMU_EXTENDED 5623 if (arm_pcache.cache_type == CACHE_TYPE_PIPT) { 5624 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5625 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5626 } 5627 if (!pmap_is_page_colored_p(dst_md)) { 5628 PMAPCOUNT(vac_color_new); 5629 dst_md->pvh_attrs |= PVF_COLORED; 5630 } 5631 dst_md->pvh_attrs |= PVF_DIRTY; 5632 #endif 5633 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 5634 dst_md->pvh_attrs &= ~PVF_EXEC; 5635 PMAPCOUNT(exec_discarded_copy); 5636 } 5637 pmap_release_page_lock(dst_md); 5638 #endif 5639 } 5640 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5641 5642 #if ARM_MMU_XSCALE == 1 5643 void 5644 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 5645 { 5646 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 5647 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5648 #ifdef DEBUG 5649 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 5650 5651 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5652 panic("pmap_copy_page: dst page has mappings"); 5653 #endif 5654 5655 KDASSERT((src & PGOFSET) == 0); 5656 KDASSERT((dst & PGOFSET) == 0); 5657 5658 /* 5659 * Clean the source page. Hold the source page's lock for 5660 * the duration of the copy so that no other mappings can 5661 * be created while we have a potentially aliased mapping. 5662 */ 5663 #ifdef PMAP_CACHE_VIVT 5664 pmap_acquire_page_lock(src_md); 5665 (void) pmap_clean_page(src_md, true); 5666 pmap_release_page_lock(src_md); 5667 #endif 5668 5669 /* 5670 * Map the pages into the page hook points, copy them, and purge 5671 * the cache for the appropriate page. Invalidate the TLB 5672 * as required. 5673 */ 5674 const pt_entry_t nsrc_pte = L2_S_PROTO | src 5675 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 5676 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5677 l2pte_set(csrc_pte, nsrc_pte, 0); 5678 PTE_SYNC(csrc_pte); 5679 5680 const pt_entry_t ndst_pte = L2_S_PROTO | dst 5681 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) 5682 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5683 l2pte_set(cdst_pte, ndst_pte, 0); 5684 PTE_SYNC(cdst_pte); 5685 5686 cpu_tlb_flushD_SE(csrcp); 5687 cpu_tlb_flushD_SE(cdstp); 5688 cpu_cpwait(); 5689 bcopy_page(csrcp, cdstp); 5690 xscale_cache_clean_minidata(); 5691 l2pte_reset(csrc_pte); 5692 l2pte_reset(cdst_pte); 5693 PTE_SYNC(csrc_pte); 5694 PTE_SYNC(cdst_pte); 5695 } 5696 #endif /* ARM_MMU_XSCALE == 1 */ 5697 5698 /* 5699 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5700 * 5701 * Return the start and end addresses of the kernel's virtual space. 5702 * These values are setup in pmap_bootstrap and are updated as pages 5703 * are allocated. 5704 */ 5705 void 5706 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5707 { 5708 *start = virtual_avail; 5709 *end = virtual_end; 5710 } 5711 5712 /* 5713 * Helper function for pmap_grow_l2_bucket() 5714 */ 5715 static inline int 5716 pmap_grow_map(vaddr_t va, paddr_t *pap) 5717 { 5718 paddr_t pa; 5719 5720 if (uvm.page_init_done == false) { 5721 #ifdef PMAP_STEAL_MEMORY 5722 pv_addr_t pv; 5723 pmap_boot_pagealloc(PAGE_SIZE, 5724 #ifdef PMAP_CACHE_VIPT 5725 arm_cache_prefer_mask, 5726 va & arm_cache_prefer_mask, 5727 #else 5728 0, 0, 5729 #endif 5730 &pv); 5731 pa = pv.pv_pa; 5732 #else 5733 if (uvm_page_physget(&pa) == false) 5734 return (1); 5735 #endif /* PMAP_STEAL_MEMORY */ 5736 } else { 5737 struct vm_page *pg; 5738 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 5739 if (pg == NULL) 5740 return (1); 5741 pa = VM_PAGE_TO_PHYS(pg); 5742 /* 5743 * This new page must not have any mappings. Enter it via 5744 * pmap_kenter_pa and let that routine do the hard work. 5745 */ 5746 struct vm_page_md *md __diagused = VM_PAGE_TO_MD(pg); 5747 KASSERT(SLIST_EMPTY(&md->pvh_list)); 5748 pmap_kenter_pa(va, pa, 5749 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 5750 } 5751 5752 if (pap) 5753 *pap = pa; 5754 5755 PMAPCOUNT(pt_mappings); 5756 #ifdef DEBUG 5757 struct l2_bucket * const l2b = pmap_get_l2_bucket(pmap_kernel(), va); 5758 KDASSERT(l2b != NULL); 5759 5760 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 5761 const pt_entry_t opte = *ptep; 5762 KDASSERT((opte & L2_S_CACHE_MASK) == pte_l2_s_cache_mode_pt); 5763 #endif 5764 memset((void *)va, 0, PAGE_SIZE); 5765 return (0); 5766 } 5767 5768 /* 5769 * This is the same as pmap_alloc_l2_bucket(), except that it is only 5770 * used by pmap_growkernel(). 5771 */ 5772 static inline struct l2_bucket * 5773 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 5774 { 5775 struct l2_dtable *l2; 5776 struct l2_bucket *l2b; 5777 u_short l1slot; 5778 vaddr_t nva; 5779 5780 l1slot = l1pte_index(va); 5781 5782 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 5783 /* 5784 * No mapping at this address, as there is 5785 * no entry in the L1 table. 5786 * Need to allocate a new l2_dtable. 5787 */ 5788 nva = pmap_kernel_l2dtable_kva; 5789 if ((nva & PGOFSET) == 0) { 5790 /* 5791 * Need to allocate a backing page 5792 */ 5793 if (pmap_grow_map(nva, NULL)) 5794 return (NULL); 5795 } 5796 5797 l2 = (struct l2_dtable *)nva; 5798 nva += sizeof(struct l2_dtable); 5799 5800 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 5801 /* 5802 * The new l2_dtable straddles a page boundary. 5803 * Map in another page to cover it. 5804 */ 5805 if (pmap_grow_map(nva, NULL)) 5806 return (NULL); 5807 } 5808 5809 pmap_kernel_l2dtable_kva = nva; 5810 5811 /* 5812 * Link it into the parent pmap 5813 */ 5814 pm->pm_l2[L2_IDX(l1slot)] = l2; 5815 } 5816 5817 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 5818 5819 /* 5820 * Fetch pointer to the L2 page table associated with the address. 5821 */ 5822 if (l2b->l2b_kva == NULL) { 5823 pt_entry_t *ptep; 5824 5825 /* 5826 * No L2 page table has been allocated. Chances are, this 5827 * is because we just allocated the l2_dtable, above. 5828 */ 5829 nva = pmap_kernel_l2ptp_kva; 5830 ptep = (pt_entry_t *)nva; 5831 if ((nva & PGOFSET) == 0) { 5832 /* 5833 * Need to allocate a backing page 5834 */ 5835 if (pmap_grow_map(nva, &pmap_kernel_l2ptp_phys)) 5836 return (NULL); 5837 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 5838 } 5839 5840 l2->l2_occupancy++; 5841 l2b->l2b_kva = ptep; 5842 l2b->l2b_l1slot = l1slot; 5843 l2b->l2b_pa = pmap_kernel_l2ptp_phys; 5844 5845 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 5846 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 5847 } 5848 5849 return (l2b); 5850 } 5851 5852 vaddr_t 5853 pmap_growkernel(vaddr_t maxkvaddr) 5854 { 5855 pmap_t kpm = pmap_kernel(); 5856 #ifndef ARM_MMU_EXTENDED 5857 struct l1_ttable *l1; 5858 #endif 5859 int s; 5860 5861 if (maxkvaddr <= pmap_curmaxkvaddr) 5862 goto out; /* we are OK */ 5863 5864 NPDEBUG(PDB_GROWKERN, 5865 printf("pmap_growkernel: growing kernel from 0x%lx to 0x%lx\n", 5866 pmap_curmaxkvaddr, maxkvaddr)); 5867 5868 KDASSERT(maxkvaddr <= virtual_end); 5869 5870 /* 5871 * whoops! we need to add kernel PTPs 5872 */ 5873 5874 s = splhigh(); /* to be safe */ 5875 mutex_enter(kpm->pm_lock); 5876 5877 /* Map 1MB at a time */ 5878 size_t l1slot = l1pte_index(pmap_curmaxkvaddr); 5879 #ifdef ARM_MMU_EXTENDED 5880 pd_entry_t * const spdep = &kpm->pm_l1[l1slot]; 5881 pd_entry_t *pdep = spdep; 5882 #endif 5883 for (;pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE, 5884 #ifdef ARM_MMU_EXTENDED 5885 pdep++, 5886 #endif 5887 l1slot++) { 5888 struct l2_bucket *l2b = 5889 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 5890 KASSERT(l2b != NULL); 5891 5892 const pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 5893 | L1_C_DOM(PMAP_DOMAIN_KERNEL); 5894 #ifdef ARM_MMU_EXTENDED 5895 l1pte_setone(pdep, npde); 5896 #else 5897 /* Distribute new L1 entry to all other L1s */ 5898 SLIST_FOREACH(l1, &l1_list, l1_link) { 5899 pd_entry_t * const pdep = &l1->l1_kva[l1slot]; 5900 l1pte_setone(pdep, npde); 5901 PDE_SYNC(pdep); 5902 } 5903 #endif 5904 } 5905 #ifdef ARM_MMU_EXTENDED 5906 PDE_SYNC_RANGE(spdep, pdep - spdep); 5907 #endif 5908 5909 #ifdef PMAP_CACHE_VIVT 5910 /* 5911 * flush out the cache, expensive but growkernel will happen so 5912 * rarely 5913 */ 5914 cpu_dcache_wbinv_all(); 5915 cpu_tlb_flushD(); 5916 cpu_cpwait(); 5917 #endif 5918 5919 mutex_exit(kpm->pm_lock); 5920 splx(s); 5921 5922 out: 5923 return (pmap_curmaxkvaddr); 5924 } 5925 5926 /************************ Utility routines ****************************/ 5927 5928 #ifndef ARM_HAS_VBAR 5929 /* 5930 * vector_page_setprot: 5931 * 5932 * Manipulate the protection of the vector page. 5933 */ 5934 void 5935 vector_page_setprot(int prot) 5936 { 5937 struct l2_bucket *l2b; 5938 pt_entry_t *ptep; 5939 5940 #if defined(CPU_ARMV7) || defined(CPU_ARM11) 5941 /* 5942 * If we are using VBAR to use the vectors in the kernel, then it's 5943 * already mapped in the kernel text so no need to anything here. 5944 */ 5945 if (vector_page != ARM_VECTORS_LOW && vector_page != ARM_VECTORS_HIGH) { 5946 KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0); 5947 return; 5948 } 5949 #endif 5950 5951 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 5952 KASSERT(l2b != NULL); 5953 5954 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 5955 5956 const pt_entry_t opte = *ptep; 5957 #ifdef ARM_MMU_EXTENDED 5958 const pt_entry_t npte = (opte & ~(L2_S_PROT_MASK|L2_XS_XN)) 5959 | L2_S_PROT(PTE_KERNEL, prot); 5960 #else 5961 const pt_entry_t npte = (opte & ~L2_S_PROT_MASK) 5962 | L2_S_PROT(PTE_KERNEL, prot); 5963 #endif 5964 l2pte_set(ptep, npte, opte); 5965 PTE_SYNC(ptep); 5966 cpu_tlb_flushD_SE(vector_page); 5967 cpu_cpwait(); 5968 } 5969 #endif 5970 5971 /* 5972 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 5973 * Returns true if the mapping exists, else false. 5974 * 5975 * NOTE: This function is only used by a couple of arm-specific modules. 5976 * It is not safe to take any pmap locks here, since we could be right 5977 * in the middle of debugging the pmap anyway... 5978 * 5979 * It is possible for this routine to return false even though a valid 5980 * mapping does exist. This is because we don't lock, so the metadata 5981 * state may be inconsistent. 5982 * 5983 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 5984 * a "section" mapping. 5985 */ 5986 bool 5987 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 5988 { 5989 struct l2_dtable *l2; 5990 pd_entry_t *pdep, pde; 5991 pt_entry_t *ptep; 5992 u_short l1slot; 5993 5994 if (pm->pm_l1 == NULL) 5995 return false; 5996 5997 l1slot = l1pte_index(va); 5998 *pdp = pdep = pmap_l1_kva(pm) + l1slot; 5999 pde = *pdep; 6000 6001 if (l1pte_section_p(pde)) { 6002 *ptp = NULL; 6003 return true; 6004 } 6005 6006 l2 = pm->pm_l2[L2_IDX(l1slot)]; 6007 if (l2 == NULL || 6008 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 6009 return false; 6010 } 6011 6012 *ptp = &ptep[l2pte_index(va)]; 6013 return true; 6014 } 6015 6016 bool 6017 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 6018 { 6019 6020 if (pm->pm_l1 == NULL) 6021 return false; 6022 6023 *pdp = pmap_l1_kva(pm) + l1pte_index(va); 6024 6025 return true; 6026 } 6027 6028 /************************ Bootstrapping routines ****************************/ 6029 6030 #ifndef ARM_MMU_EXTENDED 6031 static void 6032 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 6033 { 6034 int i; 6035 6036 l1->l1_kva = l1pt; 6037 l1->l1_domain_use_count = 0; 6038 l1->l1_domain_first = 0; 6039 6040 for (i = 0; i < PMAP_DOMAINS; i++) 6041 l1->l1_domain_free[i] = i + 1; 6042 6043 /* 6044 * Copy the kernel's L1 entries to each new L1. 6045 */ 6046 if (pmap_initialized) 6047 memcpy(l1pt, pmap_l1_kva(pmap_kernel()), L1_TABLE_SIZE); 6048 6049 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 6050 &l1->l1_physaddr) == false) 6051 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 6052 6053 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 6054 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 6055 } 6056 #endif /* !ARM_MMU_EXTENDED */ 6057 6058 /* 6059 * pmap_bootstrap() is called from the board-specific initarm() routine 6060 * once the kernel L1/L2 descriptors tables have been set up. 6061 * 6062 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 6063 * spread over a number of disparate files/functions. 6064 * 6065 * We are passed the following parameters 6066 * - kernel_l1pt 6067 * This is a pointer to the base of the kernel's L1 translation table. 6068 * - vstart 6069 * 1MB-aligned start of managed kernel virtual memory. 6070 * - vend 6071 * 1MB-aligned end of managed kernel virtual memory. 6072 * 6073 * We use the first parameter to build the metadata (struct l1_ttable and 6074 * struct l2_dtable) necessary to track kernel mappings. 6075 */ 6076 #define PMAP_STATIC_L2_SIZE 16 6077 void 6078 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 6079 { 6080 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 6081 #ifndef ARM_MMU_EXTENDED 6082 static struct l1_ttable static_l1; 6083 struct l1_ttable *l1 = &static_l1; 6084 #endif 6085 struct l2_dtable *l2; 6086 struct l2_bucket *l2b; 6087 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 6088 pmap_t pm = pmap_kernel(); 6089 pt_entry_t *ptep; 6090 paddr_t pa; 6091 vsize_t size; 6092 int nptes, l2idx, l2next = 0; 6093 6094 #ifdef ARM_MMU_EXTENDED 6095 KASSERT(pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt); 6096 KASSERT(pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt); 6097 #endif 6098 6099 #ifdef VERBOSE_INIT_ARM 6100 printf("kpm "); 6101 #endif 6102 /* 6103 * Initialise the kernel pmap object 6104 */ 6105 curcpu()->ci_pmap_cur = pm; 6106 #ifdef ARM_MMU_EXTENDED 6107 pm->pm_l1 = l1pt; 6108 pm->pm_l1_pa = kernel_l1pt.pv_pa; 6109 #ifdef VERBOSE_INIT_ARM 6110 printf("tlb0 "); 6111 #endif 6112 pmap_tlb_info_init(&pmap_tlb0_info); 6113 #ifdef MULTIPROCESSOR 6114 #ifdef VERBOSE_INIT_ARM 6115 printf("kcpusets "); 6116 #endif 6117 pm->pm_onproc = kcpuset_running; 6118 pm->pm_active = kcpuset_running; 6119 #endif 6120 #else 6121 pm->pm_l1 = l1; 6122 #endif 6123 6124 #ifdef VERBOSE_INIT_ARM 6125 printf("locks "); 6126 #endif 6127 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 6128 if (arm_cache_prefer_mask != 0) { 6129 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_VM); 6130 } else { 6131 #endif 6132 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_NONE); 6133 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 6134 } 6135 #endif 6136 mutex_init(&pm->pm_obj_lock, MUTEX_DEFAULT, IPL_NONE); 6137 uvm_obj_init(&pm->pm_obj, NULL, false, 1); 6138 uvm_obj_setlock(&pm->pm_obj, &pm->pm_obj_lock); 6139 6140 #ifdef VERBOSE_INIT_ARM 6141 printf("l1pt "); 6142 #endif 6143 /* 6144 * Scan the L1 translation table created by initarm() and create 6145 * the required metadata for all valid mappings found in it. 6146 */ 6147 for (size_t l1slot = 0; 6148 l1slot < L1_TABLE_SIZE / sizeof(pd_entry_t); 6149 l1slot++) { 6150 pd_entry_t pde = l1pt[l1slot]; 6151 6152 /* 6153 * We're only interested in Coarse mappings. 6154 * pmap_extract() can deal with section mappings without 6155 * recourse to checking L2 metadata. 6156 */ 6157 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 6158 continue; 6159 6160 /* 6161 * Lookup the KVA of this L2 descriptor table 6162 */ 6163 pa = l1pte_pa(pde); 6164 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6165 if (ptep == NULL) { 6166 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 6167 (u_int)l1slot << L1_S_SHIFT, pa); 6168 } 6169 6170 /* 6171 * Fetch the associated L2 metadata structure. 6172 * Allocate a new one if necessary. 6173 */ 6174 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 6175 if (l2next == PMAP_STATIC_L2_SIZE) 6176 panic("pmap_bootstrap: out of static L2s"); 6177 pm->pm_l2[L2_IDX(l1slot)] = l2 = &static_l2[l2next++]; 6178 } 6179 6180 /* 6181 * One more L1 slot tracked... 6182 */ 6183 l2->l2_occupancy++; 6184 6185 /* 6186 * Fill in the details of the L2 descriptor in the 6187 * appropriate bucket. 6188 */ 6189 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 6190 l2b->l2b_kva = ptep; 6191 l2b->l2b_pa = pa; 6192 l2b->l2b_l1slot = l1slot; 6193 6194 /* 6195 * Establish an initial occupancy count for this descriptor 6196 */ 6197 for (l2idx = 0; 6198 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 6199 l2idx++) { 6200 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 6201 l2b->l2b_occupancy++; 6202 } 6203 } 6204 6205 /* 6206 * Make sure the descriptor itself has the correct cache mode. 6207 * If not, fix it, but whine about the problem. Port-meisters 6208 * should consider this a clue to fix up their initarm() 6209 * function. :) 6210 */ 6211 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep, 1)) { 6212 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6213 "L2 pte @ %p\n", ptep); 6214 } 6215 } 6216 6217 #ifdef VERBOSE_INIT_ARM 6218 printf("cache(l1pt) "); 6219 #endif 6220 /* 6221 * Ensure the primary (kernel) L1 has the correct cache mode for 6222 * a page table. Bitch if it is not correctly set. 6223 */ 6224 if (pmap_set_pt_cache_mode(l1pt, kernel_l1pt.pv_va, 6225 L1_TABLE_SIZE / L2_S_SIZE)) { 6226 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6227 "primary L1 @ 0x%lx\n", kernel_l1pt.pv_va); 6228 } 6229 6230 #ifdef PMAP_CACHE_VIVT 6231 cpu_dcache_wbinv_all(); 6232 cpu_tlb_flushID(); 6233 cpu_cpwait(); 6234 #endif 6235 6236 /* 6237 * now we allocate the "special" VAs which are used for tmp mappings 6238 * by the pmap (and other modules). we allocate the VAs by advancing 6239 * virtual_avail (note that there are no pages mapped at these VAs). 6240 * 6241 * Managed KVM space start from wherever initarm() tells us. 6242 */ 6243 virtual_avail = vstart; 6244 virtual_end = vend; 6245 6246 #ifdef VERBOSE_INIT_ARM 6247 printf("specials "); 6248 #endif 6249 #ifdef PMAP_CACHE_VIPT 6250 /* 6251 * If we have a VIPT cache, we need one page/pte per possible alias 6252 * page so we won't violate cache aliasing rules. 6253 */ 6254 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 6255 nptes = (arm_cache_prefer_mask >> L2_S_SHIFT) + 1; 6256 nptes = roundup(nptes, PAGE_SIZE / L2_S_SIZE); 6257 if (arm_pcache.icache_type != CACHE_TYPE_PIPT 6258 && arm_pcache.icache_way_size > nptes * L2_S_SIZE) { 6259 nptes = arm_pcache.icache_way_size >> L2_S_SHIFT; 6260 nptes = roundup(nptes, PAGE_SIZE / L2_S_SIZE); 6261 } 6262 #else 6263 nptes = PAGE_SIZE / L2_S_SIZE; 6264 #endif 6265 #ifdef MULTIPROCESSOR 6266 cnptes = nptes; 6267 nptes *= arm_cpu_max; 6268 #endif 6269 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 6270 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte, nptes); 6271 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 6272 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte, nptes); 6273 pmap_alloc_specials(&virtual_avail, nptes, &memhook, NULL); 6274 if (msgbufaddr == NULL) { 6275 pmap_alloc_specials(&virtual_avail, 6276 round_page(MSGBUFSIZE) / PAGE_SIZE, 6277 (void *)&msgbufaddr, NULL); 6278 } 6279 6280 /* 6281 * Allocate a range of kernel virtual address space to be used 6282 * for L2 descriptor tables and metadata allocation in 6283 * pmap_growkernel(). 6284 */ 6285 size = ((virtual_end - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 6286 pmap_alloc_specials(&virtual_avail, 6287 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 6288 &pmap_kernel_l2ptp_kva, NULL); 6289 6290 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 6291 pmap_alloc_specials(&virtual_avail, 6292 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 6293 &pmap_kernel_l2dtable_kva, NULL); 6294 6295 #ifndef ARM_MMU_EXTENDED 6296 /* 6297 * init the static-global locks and global pmap list. 6298 */ 6299 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 6300 6301 /* 6302 * We can now initialise the first L1's metadata. 6303 */ 6304 SLIST_INIT(&l1_list); 6305 TAILQ_INIT(&l1_lru_list); 6306 pmap_init_l1(l1, l1pt); 6307 #endif /* ARM_MMU_EXTENDED */ 6308 6309 #ifndef ARM_HAS_VBAR 6310 /* Set up vector page L1 details, if necessary */ 6311 if (vector_page < KERNEL_BASE) { 6312 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 6313 l2b = pmap_get_l2_bucket(pm, vector_page); 6314 KDASSERT(l2b != NULL); 6315 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 6316 L1_C_DOM(pmap_domain(pm)); 6317 } else 6318 pm->pm_pl1vec = NULL; 6319 #endif 6320 6321 #ifdef VERBOSE_INIT_ARM 6322 printf("pools "); 6323 #endif 6324 /* 6325 * Initialize the pmap cache 6326 */ 6327 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 6328 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 6329 6330 /* 6331 * Initialize the pv pool. 6332 */ 6333 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 6334 &pmap_bootstrap_pv_allocator, IPL_NONE); 6335 6336 /* 6337 * Initialize the L2 dtable pool and cache. 6338 */ 6339 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 6340 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 6341 6342 /* 6343 * Initialise the L2 descriptor table pool and cache 6344 */ 6345 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 0, 6346 L2_TABLE_SIZE_REAL, 0, "l2ptppl", NULL, IPL_NONE, 6347 pmap_l2ptp_ctor, NULL, NULL); 6348 6349 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 6350 6351 cpu_dcache_wbinv_all(); 6352 } 6353 6354 static bool 6355 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va, size_t nptes) 6356 { 6357 #ifdef ARM_MMU_EXTENDED 6358 return false; 6359 #else 6360 if (pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt 6361 && pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt) 6362 return false; 6363 6364 const vaddr_t eva = va + nptes * PAGE_SIZE; 6365 int rv = 0; 6366 6367 while (va < eva) { 6368 /* 6369 * Make sure the descriptor itself has the correct cache mode 6370 */ 6371 pd_entry_t * const pdep = &kl1[l1pte_index(va)]; 6372 pd_entry_t pde = *pdep; 6373 6374 if (l1pte_section_p(pde)) { 6375 __CTASSERT((L1_S_CACHE_MASK & L1_S_V6_SUPER) == 0); 6376 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 6377 *pdep = (pde & ~L1_S_CACHE_MASK) | 6378 pte_l1_s_cache_mode_pt; 6379 PDE_SYNC(pdep); 6380 cpu_dcache_wbinv_range((vaddr_t)pdep, 6381 sizeof(*pdep)); 6382 rv = 1; 6383 } 6384 return rv; 6385 } 6386 vaddr_t pa = l1pte_pa(pde); 6387 pt_entry_t *ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6388 if (ptep == NULL) 6389 panic("pmap_bootstrap: No PTP for va %#lx\n", va); 6390 6391 ptep += l2pte_index(va); 6392 const pt_entry_t opte = *ptep; 6393 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 6394 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 6395 | pte_l2_s_cache_mode_pt; 6396 l2pte_set(ptep, npte, opte); 6397 PTE_SYNC(ptep); 6398 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 6399 rv = 1; 6400 } 6401 va += PAGE_SIZE; 6402 } 6403 6404 return (rv); 6405 #endif 6406 } 6407 6408 static void 6409 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 6410 { 6411 vaddr_t va = *availp; 6412 struct l2_bucket *l2b; 6413 6414 if (ptep) { 6415 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6416 if (l2b == NULL) 6417 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 6418 6419 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 6420 } 6421 6422 *vap = va; 6423 *availp = va + (PAGE_SIZE * pages); 6424 } 6425 6426 void 6427 pmap_init(void) 6428 { 6429 6430 /* 6431 * Set the available memory vars - These do not map to real memory 6432 * addresses and cannot as the physical memory is fragmented. 6433 * They are used by ps for %mem calculations. 6434 * One could argue whether this should be the entire memory or just 6435 * the memory that is useable in a user process. 6436 */ 6437 avail_start = ptoa(uvm_physseg_get_avail_start(uvm_physseg_get_first())); 6438 avail_end = ptoa(uvm_physseg_get_avail_end(uvm_physseg_get_last())); 6439 6440 /* 6441 * Now we need to free enough pv_entry structures to allow us to get 6442 * the kmem_map/kmem_object allocated and inited (done after this 6443 * function is finished). to do this we allocate one bootstrap page out 6444 * of kernel_map and use it to provide an initial pool of pv_entry 6445 * structures. we never free this page. 6446 */ 6447 pool_setlowat(&pmap_pv_pool, (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 6448 6449 #ifdef ARM_MMU_EXTENDED 6450 pmap_tlb_info_evcnt_attach(&pmap_tlb0_info); 6451 #endif 6452 6453 pmap_initialized = true; 6454 } 6455 6456 static vaddr_t last_bootstrap_page = 0; 6457 static void *free_bootstrap_pages = NULL; 6458 6459 static void * 6460 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 6461 { 6462 extern void *pool_page_alloc(struct pool *, int); 6463 vaddr_t new_page; 6464 void *rv; 6465 6466 if (pmap_initialized) 6467 return (pool_page_alloc(pp, flags)); 6468 6469 if (free_bootstrap_pages) { 6470 rv = free_bootstrap_pages; 6471 free_bootstrap_pages = *((void **)rv); 6472 return (rv); 6473 } 6474 6475 KASSERT(kernel_map != NULL); 6476 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 6477 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 6478 6479 KASSERT(new_page > last_bootstrap_page); 6480 last_bootstrap_page = new_page; 6481 return ((void *)new_page); 6482 } 6483 6484 static void 6485 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 6486 { 6487 extern void pool_page_free(struct pool *, void *); 6488 6489 if ((vaddr_t)v <= last_bootstrap_page) { 6490 *((void **)v) = free_bootstrap_pages; 6491 free_bootstrap_pages = v; 6492 return; 6493 } 6494 6495 if (pmap_initialized) { 6496 pool_page_free(pp, v); 6497 return; 6498 } 6499 } 6500 6501 /* 6502 * pmap_postinit() 6503 * 6504 * This routine is called after the vm and kmem subsystems have been 6505 * initialised. This allows the pmap code to perform any initialisation 6506 * that can only be done once the memory allocation is in place. 6507 */ 6508 void 6509 pmap_postinit(void) 6510 { 6511 #ifndef ARM_MMU_EXTENDED 6512 extern paddr_t physical_start, physical_end; 6513 struct l1_ttable *l1; 6514 struct pglist plist; 6515 struct vm_page *m; 6516 pd_entry_t *pdep; 6517 vaddr_t va, eva; 6518 u_int loop, needed; 6519 int error; 6520 #endif 6521 6522 pool_cache_setlowat(&pmap_l2ptp_cache, (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 6523 pool_cache_setlowat(&pmap_l2dtable_cache, 6524 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 6525 6526 #ifndef ARM_MMU_EXTENDED 6527 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 6528 needed -= 1; 6529 6530 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 6531 6532 for (loop = 0; loop < needed; loop++, l1++) { 6533 /* Allocate a L1 page table */ 6534 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 6535 if (va == 0) 6536 panic("Cannot allocate L1 KVM"); 6537 6538 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 6539 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 6540 if (error) 6541 panic("Cannot allocate L1 physical pages"); 6542 6543 m = TAILQ_FIRST(&plist); 6544 eva = va + L1_TABLE_SIZE; 6545 pdep = (pd_entry_t *)va; 6546 6547 while (m && va < eva) { 6548 paddr_t pa = VM_PAGE_TO_PHYS(m); 6549 6550 pmap_kenter_pa(va, pa, 6551 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 6552 6553 va += PAGE_SIZE; 6554 m = TAILQ_NEXT(m, pageq.queue); 6555 } 6556 6557 #ifdef DIAGNOSTIC 6558 if (m) 6559 panic("pmap_alloc_l1pt: pglist not empty"); 6560 #endif /* DIAGNOSTIC */ 6561 6562 pmap_init_l1(l1, pdep); 6563 } 6564 6565 #ifdef DEBUG 6566 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 6567 needed); 6568 #endif 6569 #endif /* !ARM_MMU_EXTENDED */ 6570 } 6571 6572 /* 6573 * Note that the following routines are used by board-specific initialisation 6574 * code to configure the initial kernel page tables. 6575 * 6576 * If ARM32_NEW_VM_LAYOUT is *not* defined, they operate on the assumption that 6577 * L2 page-table pages are 4KB in size and use 4 L1 slots. This mimics the 6578 * behaviour of the old pmap, and provides an easy migration path for 6579 * initial bring-up of the new pmap on existing ports. Fortunately, 6580 * pmap_bootstrap() compensates for this hackery. This is only a stop-gap and 6581 * will be deprecated. 6582 * 6583 * If ARM32_NEW_VM_LAYOUT *is* defined, these functions deal with 1KB L2 page 6584 * tables. 6585 */ 6586 6587 /* 6588 * This list exists for the benefit of pmap_map_chunk(). It keeps track 6589 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 6590 * find them as necessary. 6591 * 6592 * Note that the data on this list MUST remain valid after initarm() returns, 6593 * as pmap_bootstrap() uses it to contruct L2 table metadata. 6594 */ 6595 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 6596 6597 static vaddr_t 6598 kernel_pt_lookup(paddr_t pa) 6599 { 6600 pv_addr_t *pv; 6601 6602 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 6603 if (pv->pv_pa == (pa & ~PGOFSET)) 6604 return (pv->pv_va | (pa & PGOFSET)); 6605 } 6606 return (0); 6607 } 6608 6609 /* 6610 * pmap_map_section: 6611 * 6612 * Create a single section mapping. 6613 */ 6614 void 6615 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6616 { 6617 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6618 const size_t l1slot = l1pte_index(va); 6619 pd_entry_t fl; 6620 6621 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 6622 6623 switch (cache) { 6624 case PTE_NOCACHE: 6625 default: 6626 fl = 0; 6627 break; 6628 6629 case PTE_CACHE: 6630 fl = pte_l1_s_cache_mode; 6631 break; 6632 6633 case PTE_PAGETABLE: 6634 fl = pte_l1_s_cache_mode_pt; 6635 break; 6636 } 6637 6638 const pd_entry_t npde = L1_S_PROTO | pa | 6639 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6640 l1pte_setone(pdep + l1slot, npde); 6641 PDE_SYNC(pdep + l1slot); 6642 } 6643 6644 /* 6645 * pmap_map_entry: 6646 * 6647 * Create a single page mapping. 6648 */ 6649 void 6650 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6651 { 6652 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6653 const size_t l1slot = l1pte_index(va); 6654 pt_entry_t npte; 6655 pt_entry_t *ptep; 6656 6657 KASSERT(((va | pa) & PGOFSET) == 0); 6658 6659 switch (cache) { 6660 case PTE_NOCACHE: 6661 default: 6662 npte = 0; 6663 break; 6664 6665 case PTE_CACHE: 6666 npte = pte_l2_s_cache_mode; 6667 break; 6668 6669 case PTE_PAGETABLE: 6670 npte = pte_l2_s_cache_mode_pt; 6671 break; 6672 } 6673 6674 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6675 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 6676 6677 ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6678 if (ptep == NULL) 6679 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 6680 6681 npte |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 6682 #ifdef ARM_MMU_EXTENDED 6683 if (prot & VM_PROT_EXECUTE) { 6684 npte &= ~L2_XS_XN; 6685 } 6686 #endif 6687 ptep += l2pte_index(va); 6688 l2pte_set(ptep, npte, 0); 6689 PTE_SYNC(ptep); 6690 } 6691 6692 /* 6693 * pmap_link_l2pt: 6694 * 6695 * Link the L2 page table specified by "l2pv" into the L1 6696 * page table at the slot for "va". 6697 */ 6698 void 6699 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 6700 { 6701 pd_entry_t * const pdep = (pd_entry_t *) l1pt + l1pte_index(va); 6702 6703 KASSERT((va & ((L1_S_SIZE * (PAGE_SIZE / L2_T_SIZE)) - 1)) == 0); 6704 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 6705 6706 const pd_entry_t npde = L1_C_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO 6707 | l2pv->pv_pa; 6708 6709 l1pte_set(pdep, npde); 6710 PDE_SYNC_RANGE(pdep, PAGE_SIZE / L2_T_SIZE); 6711 6712 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 6713 } 6714 6715 /* 6716 * pmap_map_chunk: 6717 * 6718 * Map a chunk of memory using the most efficient mappings 6719 * possible (section, large page, small page) into the 6720 * provided L1 and L2 tables at the specified virtual address. 6721 */ 6722 vsize_t 6723 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 6724 int prot, int cache) 6725 { 6726 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6727 pt_entry_t f1, f2s, f2l; 6728 vsize_t resid; 6729 6730 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 6731 6732 if (l1pt == 0) 6733 panic("pmap_map_chunk: no L1 table provided"); 6734 6735 #ifdef VERBOSE_INIT_ARM 6736 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 6737 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 6738 #endif 6739 6740 switch (cache) { 6741 case PTE_NOCACHE: 6742 default: 6743 f1 = 0; 6744 f2l = 0; 6745 f2s = 0; 6746 break; 6747 6748 case PTE_CACHE: 6749 f1 = pte_l1_s_cache_mode; 6750 f2l = pte_l2_l_cache_mode; 6751 f2s = pte_l2_s_cache_mode; 6752 break; 6753 6754 case PTE_PAGETABLE: 6755 f1 = pte_l1_s_cache_mode_pt; 6756 f2l = pte_l2_l_cache_mode_pt; 6757 f2s = pte_l2_s_cache_mode_pt; 6758 break; 6759 } 6760 6761 size = resid; 6762 6763 while (resid > 0) { 6764 const size_t l1slot = l1pte_index(va); 6765 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 6766 /* See if we can use a supersection mapping. */ 6767 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 6768 /* Supersection are always domain 0 */ 6769 const pd_entry_t npde = L1_SS_PROTO | pa 6770 #ifdef ARM_MMU_EXTENDED 6771 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6772 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6773 #endif 6774 | L1_S_PROT(PTE_KERNEL, prot) | f1; 6775 #ifdef VERBOSE_INIT_ARM 6776 printf("sS"); 6777 #endif 6778 l1pte_set(&pdep[l1slot], npde); 6779 PDE_SYNC_RANGE(&pdep[l1slot], L1_SS_SIZE / L1_S_SIZE); 6780 va += L1_SS_SIZE; 6781 pa += L1_SS_SIZE; 6782 resid -= L1_SS_SIZE; 6783 continue; 6784 } 6785 #endif 6786 /* See if we can use a section mapping. */ 6787 if (L1_S_MAPPABLE_P(va, pa, resid)) { 6788 const pd_entry_t npde = L1_S_PROTO | pa 6789 #ifdef ARM_MMU_EXTENDED 6790 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 6791 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 6792 #endif 6793 | L1_S_PROT(PTE_KERNEL, prot) | f1 6794 | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6795 #ifdef VERBOSE_INIT_ARM 6796 printf("S"); 6797 #endif 6798 l1pte_set(&pdep[l1slot], npde); 6799 PDE_SYNC(&pdep[l1slot]); 6800 va += L1_S_SIZE; 6801 pa += L1_S_SIZE; 6802 resid -= L1_S_SIZE; 6803 continue; 6804 } 6805 6806 /* 6807 * Ok, we're going to use an L2 table. Make sure 6808 * one is actually in the corresponding L1 slot 6809 * for the current VA. 6810 */ 6811 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 6812 panic("%s: no L2 table for VA %#lx", __func__, va); 6813 6814 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 6815 if (ptep == NULL) 6816 panic("%s: can't find L2 table for VA %#lx", __func__, 6817 va); 6818 6819 ptep += l2pte_index(va); 6820 6821 /* See if we can use a L2 large page mapping. */ 6822 if (L2_L_MAPPABLE_P(va, pa, resid)) { 6823 const pt_entry_t npte = L2_L_PROTO | pa 6824 #ifdef ARM_MMU_EXTENDED 6825 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_L_XN) 6826 | (va & 0x80000000 ? 0 : L2_XS_nG) 6827 #endif 6828 | L2_L_PROT(PTE_KERNEL, prot) | f2l; 6829 #ifdef VERBOSE_INIT_ARM 6830 printf("L"); 6831 #endif 6832 l2pte_set(ptep, npte, 0); 6833 PTE_SYNC_RANGE(ptep, L2_L_SIZE / L2_S_SIZE); 6834 va += L2_L_SIZE; 6835 pa += L2_L_SIZE; 6836 resid -= L2_L_SIZE; 6837 continue; 6838 } 6839 6840 #ifdef VERBOSE_INIT_ARM 6841 printf("P"); 6842 #endif 6843 /* Use a small page mapping. */ 6844 pt_entry_t npte = L2_S_PROTO | pa 6845 #ifdef ARM_MMU_EXTENDED 6846 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_XN) 6847 | (va & 0x80000000 ? 0 : L2_XS_nG) 6848 #endif 6849 | L2_S_PROT(PTE_KERNEL, prot) | f2s; 6850 #ifdef ARM_MMU_EXTENDED 6851 npte &= ((prot & VM_PROT_EXECUTE) ? ~L2_XS_XN : ~0); 6852 #endif 6853 l2pte_set(ptep, npte, 0); 6854 PTE_SYNC(ptep); 6855 va += PAGE_SIZE; 6856 pa += PAGE_SIZE; 6857 resid -= PAGE_SIZE; 6858 } 6859 #ifdef VERBOSE_INIT_ARM 6860 printf("\n"); 6861 #endif 6862 return (size); 6863 } 6864 6865 /********************** Static device map routines ***************************/ 6866 6867 static const struct pmap_devmap *pmap_devmap_table; 6868 6869 /* 6870 * Register the devmap table. This is provided in case early console 6871 * initialization needs to register mappings created by bootstrap code 6872 * before pmap_devmap_bootstrap() is called. 6873 */ 6874 void 6875 pmap_devmap_register(const struct pmap_devmap *table) 6876 { 6877 6878 pmap_devmap_table = table; 6879 } 6880 6881 /* 6882 * Map all of the static regions in the devmap table, and remember 6883 * the devmap table so other parts of the kernel can look up entries 6884 * later. 6885 */ 6886 void 6887 pmap_devmap_bootstrap(vaddr_t l1pt, const struct pmap_devmap *table) 6888 { 6889 int i; 6890 6891 pmap_devmap_table = table; 6892 6893 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6894 #ifdef VERBOSE_INIT_ARM 6895 printf("devmap: %08lx -> %08lx @ %08lx\n", 6896 pmap_devmap_table[i].pd_pa, 6897 pmap_devmap_table[i].pd_pa + 6898 pmap_devmap_table[i].pd_size - 1, 6899 pmap_devmap_table[i].pd_va); 6900 #endif 6901 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 6902 pmap_devmap_table[i].pd_pa, 6903 pmap_devmap_table[i].pd_size, 6904 pmap_devmap_table[i].pd_prot, 6905 pmap_devmap_table[i].pd_cache); 6906 } 6907 } 6908 6909 const struct pmap_devmap * 6910 pmap_devmap_find_pa(paddr_t pa, psize_t size) 6911 { 6912 uint64_t endpa; 6913 int i; 6914 6915 if (pmap_devmap_table == NULL) 6916 return (NULL); 6917 6918 endpa = (uint64_t)pa + (uint64_t)(size - 1); 6919 6920 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6921 if (pa >= pmap_devmap_table[i].pd_pa && 6922 endpa <= (uint64_t)pmap_devmap_table[i].pd_pa + 6923 (uint64_t)(pmap_devmap_table[i].pd_size - 1)) 6924 return (&pmap_devmap_table[i]); 6925 } 6926 6927 return (NULL); 6928 } 6929 6930 const struct pmap_devmap * 6931 pmap_devmap_find_va(vaddr_t va, vsize_t size) 6932 { 6933 int i; 6934 6935 if (pmap_devmap_table == NULL) 6936 return (NULL); 6937 6938 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 6939 if (va >= pmap_devmap_table[i].pd_va && 6940 va + size - 1 <= pmap_devmap_table[i].pd_va + 6941 pmap_devmap_table[i].pd_size - 1) 6942 return (&pmap_devmap_table[i]); 6943 } 6944 6945 return (NULL); 6946 } 6947 6948 /********************** PTE initialization routines **************************/ 6949 6950 /* 6951 * These routines are called when the CPU type is identified to set up 6952 * the PTE prototypes, cache modes, etc. 6953 * 6954 * The variables are always here, just in case modules need to reference 6955 * them (though, they shouldn't). 6956 */ 6957 6958 pt_entry_t pte_l1_s_cache_mode; 6959 pt_entry_t pte_l1_s_wc_mode; 6960 pt_entry_t pte_l1_s_cache_mode_pt; 6961 pt_entry_t pte_l1_s_cache_mask; 6962 6963 pt_entry_t pte_l2_l_cache_mode; 6964 pt_entry_t pte_l2_l_wc_mode; 6965 pt_entry_t pte_l2_l_cache_mode_pt; 6966 pt_entry_t pte_l2_l_cache_mask; 6967 6968 pt_entry_t pte_l2_s_cache_mode; 6969 pt_entry_t pte_l2_s_wc_mode; 6970 pt_entry_t pte_l2_s_cache_mode_pt; 6971 pt_entry_t pte_l2_s_cache_mask; 6972 6973 pt_entry_t pte_l1_s_prot_u; 6974 pt_entry_t pte_l1_s_prot_w; 6975 pt_entry_t pte_l1_s_prot_ro; 6976 pt_entry_t pte_l1_s_prot_mask; 6977 6978 pt_entry_t pte_l2_s_prot_u; 6979 pt_entry_t pte_l2_s_prot_w; 6980 pt_entry_t pte_l2_s_prot_ro; 6981 pt_entry_t pte_l2_s_prot_mask; 6982 6983 pt_entry_t pte_l2_l_prot_u; 6984 pt_entry_t pte_l2_l_prot_w; 6985 pt_entry_t pte_l2_l_prot_ro; 6986 pt_entry_t pte_l2_l_prot_mask; 6987 6988 pt_entry_t pte_l1_ss_proto; 6989 pt_entry_t pte_l1_s_proto; 6990 pt_entry_t pte_l1_c_proto; 6991 pt_entry_t pte_l2_s_proto; 6992 6993 void (*pmap_copy_page_func)(paddr_t, paddr_t); 6994 void (*pmap_zero_page_func)(paddr_t); 6995 6996 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 6997 void 6998 pmap_pte_init_generic(void) 6999 { 7000 7001 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7002 pte_l1_s_wc_mode = L1_S_B; 7003 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 7004 7005 pte_l2_l_cache_mode = L2_B|L2_C; 7006 pte_l2_l_wc_mode = L2_B; 7007 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 7008 7009 pte_l2_s_cache_mode = L2_B|L2_C; 7010 pte_l2_s_wc_mode = L2_B; 7011 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 7012 7013 /* 7014 * If we have a write-through cache, set B and C. If 7015 * we have a write-back cache, then we assume setting 7016 * only C will make those pages write-through (except for those 7017 * Cortex CPUs which can read the L1 caches). 7018 */ 7019 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 7020 #if ARM_MMU_V7 > 0 7021 || CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 7022 #endif 7023 #if ARM_MMU_V6 > 0 7024 || CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid) /* arm116 errata 399234 */ 7025 #endif 7026 || false) { 7027 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7028 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7029 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7030 } else { 7031 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 7032 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 7033 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 7034 } 7035 7036 pte_l1_s_prot_u = L1_S_PROT_U_generic; 7037 pte_l1_s_prot_w = L1_S_PROT_W_generic; 7038 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 7039 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 7040 7041 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7042 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7043 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7044 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7045 7046 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7047 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7048 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7049 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7050 7051 pte_l1_ss_proto = L1_SS_PROTO_generic; 7052 pte_l1_s_proto = L1_S_PROTO_generic; 7053 pte_l1_c_proto = L1_C_PROTO_generic; 7054 pte_l2_s_proto = L2_S_PROTO_generic; 7055 7056 pmap_copy_page_func = pmap_copy_page_generic; 7057 pmap_zero_page_func = pmap_zero_page_generic; 7058 } 7059 7060 #if defined(CPU_ARM8) 7061 void 7062 pmap_pte_init_arm8(void) 7063 { 7064 7065 /* 7066 * ARM8 is compatible with generic, but we need to use 7067 * the page tables uncached. 7068 */ 7069 pmap_pte_init_generic(); 7070 7071 pte_l1_s_cache_mode_pt = 0; 7072 pte_l2_l_cache_mode_pt = 0; 7073 pte_l2_s_cache_mode_pt = 0; 7074 } 7075 #endif /* CPU_ARM8 */ 7076 7077 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 7078 void 7079 pmap_pte_init_arm9(void) 7080 { 7081 7082 /* 7083 * ARM9 is compatible with generic, but we want to use 7084 * write-through caching for now. 7085 */ 7086 pmap_pte_init_generic(); 7087 7088 pte_l1_s_cache_mode = L1_S_C; 7089 pte_l2_l_cache_mode = L2_C; 7090 pte_l2_s_cache_mode = L2_C; 7091 7092 pte_l1_s_wc_mode = L1_S_B; 7093 pte_l2_l_wc_mode = L2_B; 7094 pte_l2_s_wc_mode = L2_B; 7095 7096 pte_l1_s_cache_mode_pt = L1_S_C; 7097 pte_l2_l_cache_mode_pt = L2_C; 7098 pte_l2_s_cache_mode_pt = L2_C; 7099 } 7100 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 7101 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 7102 7103 #if defined(CPU_ARM10) 7104 void 7105 pmap_pte_init_arm10(void) 7106 { 7107 7108 /* 7109 * ARM10 is compatible with generic, but we want to use 7110 * write-through caching for now. 7111 */ 7112 pmap_pte_init_generic(); 7113 7114 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 7115 pte_l2_l_cache_mode = L2_B | L2_C; 7116 pte_l2_s_cache_mode = L2_B | L2_C; 7117 7118 pte_l1_s_cache_mode = L1_S_B; 7119 pte_l2_l_cache_mode = L2_B; 7120 pte_l2_s_cache_mode = L2_B; 7121 7122 pte_l1_s_cache_mode_pt = L1_S_C; 7123 pte_l2_l_cache_mode_pt = L2_C; 7124 pte_l2_s_cache_mode_pt = L2_C; 7125 7126 } 7127 #endif /* CPU_ARM10 */ 7128 7129 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 7130 void 7131 pmap_pte_init_arm11(void) 7132 { 7133 7134 /* 7135 * ARM11 is compatible with generic, but we want to use 7136 * write-through caching for now. 7137 */ 7138 pmap_pte_init_generic(); 7139 7140 pte_l1_s_cache_mode = L1_S_C; 7141 pte_l2_l_cache_mode = L2_C; 7142 pte_l2_s_cache_mode = L2_C; 7143 7144 pte_l1_s_wc_mode = L1_S_B; 7145 pte_l2_l_wc_mode = L2_B; 7146 pte_l2_s_wc_mode = L2_B; 7147 7148 pte_l1_s_cache_mode_pt = L1_S_C; 7149 pte_l2_l_cache_mode_pt = L2_C; 7150 pte_l2_s_cache_mode_pt = L2_C; 7151 } 7152 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 7153 7154 #if ARM_MMU_SA1 == 1 7155 void 7156 pmap_pte_init_sa1(void) 7157 { 7158 7159 /* 7160 * The StrongARM SA-1 cache does not have a write-through 7161 * mode. So, do the generic initialization, then reset 7162 * the page table cache mode to B=1,C=1, and note that 7163 * the PTEs need to be sync'd. 7164 */ 7165 pmap_pte_init_generic(); 7166 7167 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7168 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7169 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7170 7171 pmap_needs_pte_sync = 1; 7172 } 7173 #endif /* ARM_MMU_SA1 == 1*/ 7174 7175 #if ARM_MMU_XSCALE == 1 7176 #if (ARM_NMMUS > 1) 7177 static u_int xscale_use_minidata; 7178 #endif 7179 7180 void 7181 pmap_pte_init_xscale(void) 7182 { 7183 uint32_t auxctl; 7184 int write_through = 0; 7185 7186 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7187 pte_l1_s_wc_mode = L1_S_B; 7188 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 7189 7190 pte_l2_l_cache_mode = L2_B|L2_C; 7191 pte_l2_l_wc_mode = L2_B; 7192 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 7193 7194 pte_l2_s_cache_mode = L2_B|L2_C; 7195 pte_l2_s_wc_mode = L2_B; 7196 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 7197 7198 pte_l1_s_cache_mode_pt = L1_S_C; 7199 pte_l2_l_cache_mode_pt = L2_C; 7200 pte_l2_s_cache_mode_pt = L2_C; 7201 7202 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 7203 /* 7204 * The XScale core has an enhanced mode where writes that 7205 * miss the cache cause a cache line to be allocated. This 7206 * is significantly faster than the traditional, write-through 7207 * behavior of this case. 7208 */ 7209 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 7210 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 7211 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 7212 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 7213 7214 #ifdef XSCALE_CACHE_WRITE_THROUGH 7215 /* 7216 * Some versions of the XScale core have various bugs in 7217 * their cache units, the work-around for which is to run 7218 * the cache in write-through mode. Unfortunately, this 7219 * has a major (negative) impact on performance. So, we 7220 * go ahead and run fast-and-loose, in the hopes that we 7221 * don't line up the planets in a way that will trip the 7222 * bugs. 7223 * 7224 * However, we give you the option to be slow-but-correct. 7225 */ 7226 write_through = 1; 7227 #elif defined(XSCALE_CACHE_WRITE_BACK) 7228 /* force write back cache mode */ 7229 write_through = 0; 7230 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 7231 /* 7232 * Intel PXA2[15]0 processors are known to have a bug in 7233 * write-back cache on revision 4 and earlier (stepping 7234 * A[01] and B[012]). Fixed for C0 and later. 7235 */ 7236 { 7237 uint32_t id, type; 7238 7239 id = cpufunc_id(); 7240 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 7241 7242 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 7243 if ((id & CPU_ID_REVISION_MASK) < 5) { 7244 /* write through for stepping A0-1 and B0-2 */ 7245 write_through = 1; 7246 } 7247 } 7248 } 7249 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 7250 7251 if (write_through) { 7252 pte_l1_s_cache_mode = L1_S_C; 7253 pte_l2_l_cache_mode = L2_C; 7254 pte_l2_s_cache_mode = L2_C; 7255 } 7256 7257 #if (ARM_NMMUS > 1) 7258 xscale_use_minidata = 1; 7259 #endif 7260 7261 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 7262 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 7263 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 7264 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 7265 7266 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 7267 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 7268 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 7269 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 7270 7271 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 7272 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 7273 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 7274 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 7275 7276 pte_l1_ss_proto = L1_SS_PROTO_xscale; 7277 pte_l1_s_proto = L1_S_PROTO_xscale; 7278 pte_l1_c_proto = L1_C_PROTO_xscale; 7279 pte_l2_s_proto = L2_S_PROTO_xscale; 7280 7281 pmap_copy_page_func = pmap_copy_page_xscale; 7282 pmap_zero_page_func = pmap_zero_page_xscale; 7283 7284 /* 7285 * Disable ECC protection of page table access, for now. 7286 */ 7287 auxctl = armreg_auxctl_read(); 7288 auxctl &= ~XSCALE_AUXCTL_P; 7289 armreg_auxctl_write(auxctl); 7290 } 7291 7292 /* 7293 * xscale_setup_minidata: 7294 * 7295 * Set up the mini-data cache clean area. We require the 7296 * caller to allocate the right amount of physically and 7297 * virtually contiguous space. 7298 */ 7299 void 7300 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 7301 { 7302 extern vaddr_t xscale_minidata_clean_addr; 7303 extern vsize_t xscale_minidata_clean_size; /* already initialized */ 7304 pd_entry_t *pde = (pd_entry_t *) l1pt; 7305 vsize_t size; 7306 uint32_t auxctl; 7307 7308 xscale_minidata_clean_addr = va; 7309 7310 /* Round it to page size. */ 7311 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 7312 7313 for (; size != 0; 7314 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 7315 const size_t l1slot = l1pte_index(va); 7316 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pde[l1slot])); 7317 if (ptep == NULL) 7318 panic("xscale_setup_minidata: can't find L2 table for " 7319 "VA 0x%08lx", va); 7320 7321 ptep += l2pte_index(va); 7322 pt_entry_t opte = *ptep; 7323 l2pte_set(ptep, 7324 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 7325 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X), opte); 7326 } 7327 7328 /* 7329 * Configure the mini-data cache for write-back with 7330 * read/write-allocate. 7331 * 7332 * NOTE: In order to reconfigure the mini-data cache, we must 7333 * make sure it contains no valid data! In order to do that, 7334 * we must issue a global data cache invalidate command! 7335 * 7336 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 7337 * THIS IS VERY IMPORTANT! 7338 */ 7339 7340 /* Invalidate data and mini-data. */ 7341 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 7342 auxctl = armreg_auxctl_read(); 7343 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 7344 armreg_auxctl_write(auxctl); 7345 } 7346 7347 /* 7348 * Change the PTEs for the specified kernel mappings such that they 7349 * will use the mini data cache instead of the main data cache. 7350 */ 7351 void 7352 pmap_uarea(vaddr_t va) 7353 { 7354 vaddr_t next_bucket, eva; 7355 7356 #if (ARM_NMMUS > 1) 7357 if (xscale_use_minidata == 0) 7358 return; 7359 #endif 7360 7361 eva = va + USPACE; 7362 7363 while (va < eva) { 7364 next_bucket = L2_NEXT_BUCKET_VA(va); 7365 if (next_bucket > eva) 7366 next_bucket = eva; 7367 7368 struct l2_bucket *l2b = pmap_get_l2_bucket(pmap_kernel(), va); 7369 KDASSERT(l2b != NULL); 7370 7371 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 7372 pt_entry_t *ptep = sptep; 7373 7374 while (va < next_bucket) { 7375 const pt_entry_t opte = *ptep; 7376 if (!l2pte_minidata_p(opte)) { 7377 cpu_dcache_wbinv_range(va, PAGE_SIZE); 7378 cpu_tlb_flushD_SE(va); 7379 l2pte_set(ptep, opte & ~L2_B, opte); 7380 } 7381 ptep += PAGE_SIZE / L2_S_SIZE; 7382 va += PAGE_SIZE; 7383 } 7384 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 7385 } 7386 cpu_cpwait(); 7387 } 7388 #endif /* ARM_MMU_XSCALE == 1 */ 7389 7390 7391 #if defined(CPU_ARM11MPCORE) 7392 7393 void 7394 pmap_pte_init_arm11mpcore(void) 7395 { 7396 7397 /* cache mode is controlled by 5 bits (B, C, TEX) */ 7398 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 7399 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 7400 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7401 /* use extended small page (without APn, with TEX) */ 7402 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 7403 #else 7404 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 7405 #endif 7406 7407 /* write-back, write-allocate */ 7408 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7409 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 7410 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7411 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7412 #else 7413 /* no TEX. read-allocate */ 7414 pte_l2_s_cache_mode = L2_C | L2_B; 7415 #endif 7416 /* 7417 * write-back, write-allocate for page tables. 7418 */ 7419 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7420 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 7421 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7422 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7423 #else 7424 pte_l2_s_cache_mode_pt = L2_C | L2_B; 7425 #endif 7426 7427 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 7428 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 7429 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 7430 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 7431 7432 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7433 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 7434 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 7435 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 7436 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 7437 7438 #else 7439 /* with AP[0..3] */ 7440 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7441 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7442 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7443 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7444 #endif 7445 7446 #ifdef ARM11MPCORE_COMPAT_MMU 7447 /* with AP[0..3] */ 7448 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7449 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7450 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7451 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7452 7453 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7454 pte_l1_s_proto = L1_S_PROTO_armv6; 7455 pte_l1_c_proto = L1_C_PROTO_armv6; 7456 pte_l2_s_proto = L2_S_PROTO_armv6c; 7457 #else 7458 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 7459 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 7460 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 7461 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 7462 7463 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7464 pte_l1_s_proto = L1_S_PROTO_armv6; 7465 pte_l1_c_proto = L1_C_PROTO_armv6; 7466 pte_l2_s_proto = L2_S_PROTO_armv6n; 7467 #endif 7468 7469 pmap_copy_page_func = pmap_copy_page_generic; 7470 pmap_zero_page_func = pmap_zero_page_generic; 7471 pmap_needs_pte_sync = 1; 7472 } 7473 #endif /* CPU_ARM11MPCORE */ 7474 7475 7476 #if ARM_MMU_V7 == 1 7477 void 7478 pmap_pte_init_armv7(void) 7479 { 7480 /* 7481 * The ARMv7-A MMU is mostly compatible with generic. If the 7482 * AP field is zero, that now means "no access" rather than 7483 * read-only. The prototypes are a little different because of 7484 * the XN bit. 7485 */ 7486 pmap_pte_init_generic(); 7487 7488 pmap_needs_pte_sync = 1; 7489 7490 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 7491 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 7492 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 7493 7494 /* 7495 * If the core support coherent walk then updates to translation tables 7496 * do not require a clean to the point of unification to ensure 7497 * visibility by subsequent translation table walks. That means we can 7498 * map everything shareable and cached and the right thing will happen. 7499 */ 7500 if (__SHIFTOUT(armreg_mmfr3_read(), __BITS(23,20))) { 7501 pmap_needs_pte_sync = 0; 7502 7503 /* 7504 * write-back, no write-allocate, shareable for normal pages. 7505 */ 7506 pte_l1_s_cache_mode |= L1_S_V6_S; 7507 pte_l2_l_cache_mode |= L2_XS_S; 7508 pte_l2_s_cache_mode |= L2_XS_S; 7509 } 7510 7511 /* 7512 * Page tables are just all other memory. We can use write-back since 7513 * pmap_needs_pte_sync is 1 (or the MMU can read out of cache). 7514 */ 7515 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode; 7516 pte_l2_l_cache_mode_pt = pte_l2_l_cache_mode; 7517 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode; 7518 7519 /* 7520 * Check the Memory Model Features to see if this CPU supports 7521 * the TLBIASID coproc op. 7522 */ 7523 if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(16,19)) >= 2) { 7524 arm_has_tlbiasid_p = true; 7525 } else if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(12,15)) >= 2) { 7526 arm_has_tlbiasid_p = true; 7527 } 7528 7529 /* 7530 * Check the MPIDR to see if this CPU supports MP extensions. 7531 */ 7532 #ifdef MULTIPROCESSOR 7533 arm_has_mpext_p = (armreg_mpidr_read() & (MPIDR_MP|MPIDR_U)) == MPIDR_MP; 7534 #else 7535 arm_has_mpext_p = false; 7536 #endif 7537 7538 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 7539 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 7540 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 7541 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 7542 7543 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 7544 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 7545 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 7546 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 7547 7548 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 7549 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 7550 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 7551 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 7552 7553 pte_l1_ss_proto = L1_SS_PROTO_armv7; 7554 pte_l1_s_proto = L1_S_PROTO_armv7; 7555 pte_l1_c_proto = L1_C_PROTO_armv7; 7556 pte_l2_s_proto = L2_S_PROTO_armv7; 7557 7558 } 7559 #endif /* ARM_MMU_V7 */ 7560 7561 /* 7562 * return the PA of the current L1 table, for use when handling a crash dump 7563 */ 7564 uint32_t 7565 pmap_kernel_L1_addr(void) 7566 { 7567 #ifdef ARM_MMU_EXTENDED 7568 return pmap_kernel()->pm_l1_pa; 7569 #else 7570 return pmap_kernel()->pm_l1->l1_physaddr; 7571 #endif 7572 } 7573 7574 #if defined(DDB) 7575 /* 7576 * A couple of ddb-callable functions for dumping pmaps 7577 */ 7578 void pmap_dump(pmap_t); 7579 7580 static pt_entry_t ncptes[64]; 7581 static void pmap_dump_ncpg(pmap_t); 7582 7583 void 7584 pmap_dump(pmap_t pm) 7585 { 7586 struct l2_dtable *l2; 7587 struct l2_bucket *l2b; 7588 pt_entry_t *ptep, pte; 7589 vaddr_t l2_va, l2b_va, va; 7590 int i, j, k, occ, rows = 0; 7591 7592 if (pm == pmap_kernel()) 7593 printf("pmap_kernel (%p): ", pm); 7594 else 7595 printf("user pmap (%p): ", pm); 7596 7597 #ifdef ARM_MMU_EXTENDED 7598 printf("l1 at %p\n", pmap_l1_kva(pm)); 7599 #else 7600 printf("domain %d, l1 at %p\n", pmap_domain(pm), pmap_l1_kva(pm)); 7601 #endif 7602 7603 l2_va = 0; 7604 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 7605 l2 = pm->pm_l2[i]; 7606 7607 if (l2 == NULL || l2->l2_occupancy == 0) 7608 continue; 7609 7610 l2b_va = l2_va; 7611 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 7612 l2b = &l2->l2_bucket[j]; 7613 7614 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 7615 continue; 7616 7617 ptep = l2b->l2b_kva; 7618 7619 for (k = 0; k < 256 && ptep[k] == 0; k++) 7620 ; 7621 7622 k &= ~63; 7623 occ = l2b->l2b_occupancy; 7624 va = l2b_va + (k * 4096); 7625 for (; k < 256; k++, va += 0x1000) { 7626 char ch = ' '; 7627 if ((k % 64) == 0) { 7628 if ((rows % 8) == 0) { 7629 printf( 7630 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 7631 } 7632 printf("%08lx: ", va); 7633 } 7634 7635 ncptes[k & 63] = 0; 7636 pte = ptep[k]; 7637 if (pte == 0) { 7638 ch = '.'; 7639 } else { 7640 occ--; 7641 switch (pte & 0x0c) { 7642 case 0x00: 7643 ch = 'D'; /* No cache No buff */ 7644 break; 7645 case 0x04: 7646 ch = 'B'; /* No cache buff */ 7647 break; 7648 case 0x08: 7649 if (pte & 0x40) 7650 ch = 'm'; 7651 else 7652 ch = 'C'; /* Cache No buff */ 7653 break; 7654 case 0x0c: 7655 ch = 'F'; /* Cache Buff */ 7656 break; 7657 } 7658 7659 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 7660 ch += 0x20; 7661 7662 if ((pte & 0xc) == 0) 7663 ncptes[k & 63] = pte; 7664 } 7665 7666 if ((k % 64) == 63) { 7667 rows++; 7668 printf("%c\n", ch); 7669 pmap_dump_ncpg(pm); 7670 if (occ == 0) 7671 break; 7672 } else 7673 printf("%c", ch); 7674 } 7675 } 7676 } 7677 } 7678 7679 static void 7680 pmap_dump_ncpg(pmap_t pm) 7681 { 7682 struct vm_page *pg; 7683 struct vm_page_md *md; 7684 struct pv_entry *pv; 7685 int i; 7686 7687 for (i = 0; i < 63; i++) { 7688 if (ncptes[i] == 0) 7689 continue; 7690 7691 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 7692 if (pg == NULL) 7693 continue; 7694 md = VM_PAGE_TO_MD(pg); 7695 7696 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 7697 VM_PAGE_TO_PHYS(pg), 7698 md->krw_mappings, md->kro_mappings, 7699 md->urw_mappings, md->uro_mappings); 7700 7701 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 7702 printf(" %c va 0x%08lx, flags 0x%x\n", 7703 (pm == pv->pv_pmap) ? '*' : ' ', 7704 pv->pv_va, pv->pv_flags); 7705 } 7706 } 7707 } 7708 #endif 7709 7710 #ifdef PMAP_STEAL_MEMORY 7711 void 7712 pmap_boot_pageadd(pv_addr_t *newpv) 7713 { 7714 pv_addr_t *pv, *npv; 7715 7716 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 7717 if (newpv->pv_pa < pv->pv_va) { 7718 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 7719 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 7720 newpv->pv_size += pv->pv_size; 7721 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 7722 } 7723 pv = NULL; 7724 } else { 7725 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 7726 pv = npv) { 7727 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 7728 KASSERT(pv->pv_pa < newpv->pv_pa); 7729 if (newpv->pv_pa > npv->pv_pa) 7730 continue; 7731 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 7732 pv->pv_size += newpv->pv_size; 7733 return; 7734 } 7735 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 7736 break; 7737 newpv->pv_size += npv->pv_size; 7738 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7739 SLIST_REMOVE_AFTER(newpv, pv_list); 7740 return; 7741 } 7742 } 7743 } 7744 7745 if (pv) { 7746 SLIST_INSERT_AFTER(pv, newpv, pv_list); 7747 } else { 7748 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 7749 } 7750 } 7751 7752 void 7753 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 7754 pv_addr_t *rpv) 7755 { 7756 pv_addr_t *pv, **pvp; 7757 struct vm_physseg *ps; 7758 size_t i; 7759 7760 KASSERT(amount & PGOFSET); 7761 KASSERT((mask & PGOFSET) == 0); 7762 KASSERT((match & PGOFSET) == 0); 7763 KASSERT(amount != 0); 7764 7765 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7766 (pv = *pvp) != NULL; 7767 pvp = &SLIST_NEXT(pv, pv_list)) { 7768 pv_addr_t *newpv; 7769 psize_t off; 7770 /* 7771 * If this entry is too small to satify the request... 7772 */ 7773 KASSERT(pv->pv_size > 0); 7774 if (pv->pv_size < amount) 7775 continue; 7776 7777 for (off = 0; off <= mask; off += PAGE_SIZE) { 7778 if (((pv->pv_pa + off) & mask) == match 7779 && off + amount <= pv->pv_size) 7780 break; 7781 } 7782 if (off > mask) 7783 continue; 7784 7785 rpv->pv_va = pv->pv_va + off; 7786 rpv->pv_pa = pv->pv_pa + off; 7787 rpv->pv_size = amount; 7788 pv->pv_size -= amount; 7789 if (pv->pv_size == 0) { 7790 KASSERT(off == 0); 7791 KASSERT((vaddr_t) pv == rpv->pv_va); 7792 *pvp = SLIST_NEXT(pv, pv_list); 7793 } else if (off == 0) { 7794 KASSERT((vaddr_t) pv == rpv->pv_va); 7795 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7796 *newpv = *pv; 7797 newpv->pv_pa += amount; 7798 newpv->pv_va += amount; 7799 *pvp = newpv; 7800 } else if (off < pv->pv_size) { 7801 newpv = (pv_addr_t *) (rpv->pv_va + amount); 7802 *newpv = *pv; 7803 newpv->pv_size -= off; 7804 newpv->pv_pa += off + amount; 7805 newpv->pv_va += off + amount; 7806 7807 SLIST_NEXT(pv, pv_list) = newpv; 7808 pv->pv_size = off; 7809 } else { 7810 KASSERT((vaddr_t) pv != rpv->pv_va); 7811 } 7812 memset((void *)rpv->pv_va, 0, amount); 7813 return; 7814 } 7815 7816 if (vm_nphysseg == 0) 7817 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7818 7819 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 7820 (pv = *pvp) != NULL; 7821 pvp = &SLIST_NEXT(pv, pv_list)) { 7822 if (SLIST_NEXT(pv, pv_list) == NULL) 7823 break; 7824 } 7825 KASSERT(mask == 0); 7826 for (i = 0; i < vm_nphysseg; i++) { 7827 ps = VM_PHYSMEM_PTR(i); 7828 if (ps->avail_start == atop(pv->pv_pa + pv->pv_size) 7829 && pv->pv_va + pv->pv_size <= ptoa(ps->avail_end)) { 7830 rpv->pv_va = pv->pv_va; 7831 rpv->pv_pa = pv->pv_pa; 7832 rpv->pv_size = amount; 7833 *pvp = NULL; 7834 pmap_map_chunk(kernel_l1pt.pv_va, 7835 ptoa(ps->avail_start) + (pv->pv_va - pv->pv_pa), 7836 ptoa(ps->avail_start), 7837 amount - pv->pv_size, 7838 VM_PROT_READ|VM_PROT_WRITE, 7839 PTE_CACHE); 7840 ps->avail_start += atop(amount - pv->pv_size); 7841 /* 7842 * If we consumed the entire physseg, remove it. 7843 */ 7844 if (ps->avail_start == ps->avail_end) { 7845 for (--vm_nphysseg; i < vm_nphysseg; i++) 7846 VM_PHYSMEM_PTR_SWAP(i, i + 1); 7847 } 7848 memset((void *)rpv->pv_va, 0, rpv->pv_size); 7849 return; 7850 } 7851 } 7852 7853 panic("pmap_boot_pagealloc: couldn't allocate memory"); 7854 } 7855 7856 vaddr_t 7857 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 7858 { 7859 pv_addr_t pv; 7860 7861 pmap_boot_pagealloc(size, 0, 0, &pv); 7862 7863 return pv.pv_va; 7864 } 7865 #endif /* PMAP_STEAL_MEMORY */ 7866 7867 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 7868 { 7869 sysctl_createv(clog, 0, NULL, NULL, 7870 CTLFLAG_PERMANENT, 7871 CTLTYPE_NODE, "machdep", NULL, 7872 NULL, 0, NULL, 0, 7873 CTL_MACHDEP, CTL_EOL); 7874 7875 sysctl_createv(clog, 0, NULL, NULL, 7876 CTLFLAG_PERMANENT, 7877 CTLTYPE_INT, "kmpages", 7878 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 7879 NULL, 0, &pmap_kmpages, 0, 7880 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 7881 } 7882 7883 #ifdef PMAP_NEED_ALLOC_POOLPAGE 7884 struct vm_page * 7885 arm_pmap_alloc_poolpage(int flags) 7886 { 7887 /* 7888 * On some systems, only some pages may be "coherent" for dma and we 7889 * want to prefer those for pool pages (think mbufs) but fallback to 7890 * any page if none is available. 7891 */ 7892 if (arm_poolpage_vmfreelist != VM_FREELIST_DEFAULT) { 7893 return uvm_pagealloc_strat(NULL, 0, NULL, flags, 7894 UVM_PGA_STRAT_FALLBACK, arm_poolpage_vmfreelist); 7895 } 7896 7897 return uvm_pagealloc(NULL, 0, NULL, flags); 7898 } 7899 #endif 7900 7901 #if defined(ARM_MMU_EXTENDED) && defined(MULTIPROCESSOR) 7902 void 7903 pmap_md_tlb_info_attach(struct pmap_tlb_info *ti, struct cpu_info *ci) 7904 { 7905 /* nothing */ 7906 } 7907 7908 int 7909 pic_ipi_shootdown(void *arg) 7910 { 7911 #if PMAP_TLB_NEED_SHOOTDOWN 7912 pmap_tlb_shootdown_process(); 7913 #endif 7914 return 1; 7915 } 7916 #endif /* ARM_MMU_EXTENDED && MULTIPROCESSOR */ 7917 7918 7919 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 7920 vaddr_t 7921 pmap_direct_mapped_phys(paddr_t pa, bool *ok_p, vaddr_t va) 7922 { 7923 bool ok = false; 7924 if (physical_start <= pa && pa < physical_end) { 7925 #ifdef KERNEL_BASE_VOFFSET 7926 const vaddr_t newva = pa + KERNEL_BASE_VOFFSET; 7927 #else 7928 const vaddr_t newva = KERNEL_BASE + pa - physical_start; 7929 #endif 7930 #ifdef ARM_MMU_EXTENDED 7931 if (newva >= KERNEL_BASE && newva < pmap_directlimit) { 7932 #endif 7933 va = newva; 7934 ok = true; 7935 #ifdef ARM_MMU_EXTENDED 7936 } 7937 #endif 7938 } 7939 KASSERT(ok_p); 7940 *ok_p = ok; 7941 return va; 7942 } 7943 7944 vaddr_t 7945 pmap_map_poolpage(paddr_t pa) 7946 { 7947 bool ok __diagused; 7948 vaddr_t va = pmap_direct_mapped_phys(pa, &ok, 0); 7949 KASSERTMSG(ok, "pa %#lx not direct mappable", pa); 7950 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 7951 if (arm_cache_prefer_mask != 0) { 7952 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 7953 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 7954 pmap_acquire_page_lock(md); 7955 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 7956 pmap_release_page_lock(md); 7957 } 7958 #endif 7959 return va; 7960 } 7961 7962 paddr_t 7963 pmap_unmap_poolpage(vaddr_t va) 7964 { 7965 KASSERT(va >= KERNEL_BASE); 7966 #ifdef PMAP_CACHE_VIVT 7967 cpu_idcache_wbinv_range(va, PAGE_SIZE); 7968 #endif 7969 #if defined(KERNEL_BASE_VOFFSET) 7970 return va - KERNEL_BASE_VOFFSET; 7971 #else 7972 return va - KERNEL_BASE + physical_start; 7973 #endif 7974 } 7975 #endif /* __HAVE_MM_MD_DIRECT_MAPPED_PHYS */ 7976