1 /* $NetBSD: db_interface.c,v 1.59 2019/07/21 16:12:59 rin Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Scott K. Stevens 5 * 6 * Mach Operating System 7 * Copyright (c) 1991,1990 Carnegie Mellon University 8 * All Rights Reserved. 9 * 10 * Permission to use, copy, modify and distribute this software and its 11 * documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 18 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 * 30 * From: db_interface.c,v 2.4 1991/02/05 17:11:13 mrt (CMU) 31 */ 32 33 /* 34 * Interface to new debugger. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.59 2019/07/21 16:12:59 rin Exp $"); 39 40 #include "opt_ddb.h" 41 #include "opt_kgdb.h" 42 #include "opt_multiprocessor.h" 43 44 #include <sys/param.h> 45 #include <sys/proc.h> 46 #include <sys/reboot.h> 47 #include <sys/systm.h> /* just for boothowto */ 48 #include <sys/exec.h> 49 #include <sys/atomic.h> 50 #include <sys/intr.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <arm/arm32/db_machdep.h> 55 #include <arm/undefined.h> 56 #include <ddb/db_access.h> 57 #include <ddb/db_command.h> 58 #include <ddb/db_output.h> 59 #include <ddb/db_variables.h> 60 #include <ddb/db_sym.h> 61 #include <ddb/db_extern.h> 62 #include <ddb/db_interface.h> 63 #include <dev/cons.h> 64 65 #if defined(KGDB) || !defined(DDB) 66 #define db_printf printf 67 #endif 68 69 u_int db_fetch_reg(int, db_regs_t *); 70 71 int db_trapper(u_int, u_int, trapframe_t *, int); 72 73 int db_active = 0; 74 db_regs_t ddb_regs; /* register state */ 75 db_regs_t *ddb_regp; 76 77 #ifdef MULTIPROCESSOR 78 volatile struct cpu_info *db_onproc; 79 volatile struct cpu_info *db_newcpu; 80 #endif 81 82 83 84 85 #ifdef DDB 86 /* 87 * kdb_trap - field a TRACE or BPT trap 88 */ 89 int 90 kdb_trap(int type, db_regs_t *regs) 91 { 92 struct cpu_info * const ci = curcpu(); 93 db_regs_t dbreg; 94 int s; 95 96 switch (type) { 97 case T_BREAKPOINT: /* breakpoint */ 98 case -1: /* keyboard interrupt */ 99 break; 100 #ifdef MULTIPROCESSOR 101 case -2: 102 /* 103 * We called to enter ddb from another process but by the time 104 * we got here, no one was in ddb. So ignore the request. 105 */ 106 if (db_onproc == NULL) 107 return 1; 108 break; 109 #endif 110 default: 111 if (db_recover != 0) { 112 /* This will longjmp back into db_command_loop() */ 113 db_error("Faulted in DDB; continuing...\n"); 114 /*NOTREACHED*/ 115 } 116 } 117 118 /* Should switch to kdb`s own stack here. */ 119 120 #ifdef MULTIPROCESSOR 121 const bool is_mp_p = ncpu > 1; 122 if (is_mp_p) { 123 /* 124 * Try to take ownership of DDB. If we do, tell all other 125 * CPUs to enter DDB too. 126 */ 127 if (atomic_cas_ptr(&db_onproc, NULL, ci) == NULL) { 128 intr_ipi_send(NULL, IPI_DDB); 129 } 130 } 131 for (;;) { 132 if (is_mp_p) { 133 /* 134 * While we aren't the master, wait until the master 135 * gives control to us or exits. If it exited, we 136 * just exit too. Otherwise this cpu will enter DDB. 137 */ 138 membar_consumer(); 139 while (db_onproc != ci) { 140 if (db_onproc == NULL) 141 return 1; 142 #ifdef _ARM_ARCH_6 143 __asm __volatile("wfe"); 144 membar_consumer(); 145 #endif 146 if (db_onproc == ci) { 147 printf("%s: switching to %s\n", 148 __func__, ci->ci_cpuname); 149 } 150 } 151 } 152 #endif 153 154 s = splhigh(); 155 ci->ci_ddb_regs = &dbreg; 156 ddb_regp = &dbreg; 157 ddb_regs = *regs; 158 159 atomic_inc_32(&db_active); 160 cnpollc(true); 161 db_trap(type, 0/*code*/); 162 cnpollc(false); 163 atomic_dec_32(&db_active); 164 165 ci->ci_ddb_regs = NULL; 166 ddb_regp = &dbreg; 167 *regs = ddb_regs; 168 splx(s); 169 170 #ifdef MULTIPROCESSOR 171 if (is_mp_p && db_newcpu != NULL) { 172 db_onproc = db_newcpu; 173 db_newcpu = NULL; 174 #ifdef _ARM_ARCH_6 175 membar_producer(); 176 __asm __volatile("sev; sev"); 177 #endif 178 continue; 179 } 180 break; 181 } 182 183 if (is_mp_p) { 184 /* 185 * We are exiting DDB so there is noone onproc. Tell 186 * the other CPUs to exit. 187 */ 188 db_onproc = NULL; 189 #ifdef _ARM_ARCH_6 190 __asm __volatile("sev; sev"); 191 #endif 192 } 193 #endif 194 195 return 1; 196 } 197 #endif 198 199 int 200 db_validate_address(vaddr_t addr) 201 { 202 struct proc *p = curproc; 203 struct pmap *pmap; 204 205 if (!p || !p->p_vmspace || !p->p_vmspace->vm_map.pmap || 206 addr >= VM_MIN_KERNEL_ADDRESS 207 ) 208 pmap = pmap_kernel(); 209 else 210 pmap = p->p_vmspace->vm_map.pmap; 211 212 return (pmap_extract(pmap, addr, NULL) == false); 213 } 214 215 /* 216 * Read bytes from kernel address space for debugger. 217 */ 218 void 219 db_read_bytes(vaddr_t addr, size_t size, char *data) 220 { 221 char *src = (char *)addr; 222 223 if (db_validate_address((u_int)src)) { 224 db_printf("address %p is invalid\n", src); 225 return; 226 } 227 228 if (size == 4 && (addr & 3) == 0 && ((uintptr_t)data & 3) == 0) { 229 *((int*)data) = *((int*)src); 230 return; 231 } 232 233 if (size == 2 && (addr & 1) == 0 && ((uintptr_t)data & 1) == 0) { 234 *((short*)data) = *((short*)src); 235 return; 236 } 237 238 while (size-- > 0) { 239 if (db_validate_address((u_int)src)) { 240 db_printf("address %p is invalid\n", src); 241 return; 242 } 243 *data++ = *src++; 244 } 245 } 246 247 static void 248 db_write_text(vaddr_t addr, size_t size, const char *data) 249 { 250 251 ktext_write((void *)addr, data, size); 252 } 253 254 /* 255 * Write bytes to kernel address space for debugger. 256 */ 257 void 258 db_write_bytes(vaddr_t addr, size_t size, const char *data) 259 { 260 extern char kernel_text[]; 261 extern char etext[]; 262 char *dst; 263 size_t loop; 264 265 /* If any part is in kernel text, use db_write_text() */ 266 if (addr >= (vaddr_t) kernel_text && addr < (vaddr_t) etext) { 267 db_write_text(addr, size, data); 268 return; 269 } 270 271 dst = (char *)addr; 272 if (db_validate_address((u_int)dst)) { 273 db_printf("address %p is invalid\n", dst); 274 return; 275 } 276 277 if (size == 4 && (addr & 3) == 0 && ((uintptr_t)data & 3) == 0) 278 *((int*)dst) = *((const int *)data); 279 else 280 if (size == 2 && (addr & 1) == 0 && ((uintptr_t)data & 1) == 0) 281 *((short*)dst) = *((const short *)data); 282 else { 283 loop = size; 284 while (loop-- > 0) { 285 if (db_validate_address((u_int)dst)) { 286 db_printf("address %p is invalid\n", dst); 287 return; 288 } 289 *dst++ = *data++; 290 } 291 } 292 293 /* make sure the caches and memory are in sync */ 294 cpu_icache_sync_range(addr, size); 295 296 /* In case the current page tables have been modified ... */ 297 cpu_tlb_flushID(); 298 cpu_cpwait(); 299 } 300 301 #ifdef DDB 302 void 303 cpu_Debugger(void) 304 { 305 #if _BYTE_ORDER == _LITTLE_ENDIAN 306 __asm(".word 0xe7ffffff"); 307 #else 308 __asm(".word 0xffffffe7"); 309 #endif 310 } 311 312 int 313 db_trapper(u_int addr, u_int inst, trapframe_t *frame, int fault_code) 314 { 315 316 if (fault_code == 0) { 317 if ((inst & ~INSN_COND_MASK) == (BKPT_INST & ~INSN_COND_MASK)) 318 kdb_trap(T_BREAKPOINT, frame); 319 else 320 kdb_trap(-1, frame); 321 } else 322 return 1; 323 return 0; 324 } 325 326 extern u_int esym; 327 extern u_int end; 328 329 static struct undefined_handler db_uh; 330 331 void 332 db_machine_init(void) 333 { 334 335 /* 336 * We get called before malloc() is available, so supply a static 337 * struct undefined_handler. 338 */ 339 db_uh.uh_handler = db_trapper; 340 install_coproc_handler_static(CORE_UNKNOWN_HANDLER, &db_uh); 341 } 342 #endif 343 344 u_int 345 db_fetch_reg(int reg, db_regs_t *regs) 346 { 347 348 switch (reg) { 349 case 0: 350 return regs->tf_r0; 351 case 1: 352 return regs->tf_r1; 353 case 2: 354 return regs->tf_r2; 355 case 3: 356 return regs->tf_r3; 357 case 4: 358 return regs->tf_r4; 359 case 5: 360 return regs->tf_r5; 361 case 6: 362 return regs->tf_r6; 363 case 7: 364 return regs->tf_r7; 365 case 8: 366 return regs->tf_r8; 367 case 9: 368 return regs->tf_r9; 369 case 10: 370 return regs->tf_r10; 371 case 11: 372 return regs->tf_r11; 373 case 12: 374 return regs->tf_r12; 375 case 13: 376 return regs->tf_svc_sp; 377 case 14: 378 return regs->tf_svc_lr; 379 case 15: 380 return regs->tf_pc; 381 default: 382 panic("db_fetch_reg: botch"); 383 } 384 } 385 386 u_int 387 branch_taken(u_int insn, u_int pc, db_regs_t *regs) 388 { 389 u_int addr, nregs; 390 391 switch ((insn >> 24) & 0xf) { 392 case 0xa: /* b ... */ 393 case 0xb: /* bl ... */ 394 addr = ((insn << 2) & 0x03ffffff); 395 if (addr & 0x02000000) 396 addr |= 0xfc000000; 397 return pc + 8 + addr; 398 case 0x7: /* ldr pc, [pc, reg, lsl #2] */ 399 addr = db_fetch_reg(insn & 0xf, regs); 400 addr = pc + 8 + (addr << 2); 401 db_read_bytes(addr, 4, (char *)&addr); 402 return addr; 403 case 0x5: /* ldr pc, [reg] */ 404 addr = db_fetch_reg((insn >> 16) & 0xf, regs); 405 db_read_bytes(addr, 4, (char *)&addr); 406 return addr; 407 case 0x1: /* mov pc, reg */ 408 addr = db_fetch_reg(insn & 0xf, regs); 409 return addr; 410 case 0x8: /* ldmxx reg, {..., pc} */ 411 case 0x9: 412 addr = db_fetch_reg((insn >> 16) & 0xf, regs); 413 nregs = (insn & 0x5555) + ((insn >> 1) & 0x5555); 414 nregs = (nregs & 0x3333) + ((nregs >> 2) & 0x3333); 415 nregs = (nregs + (nregs >> 4)) & 0x0f0f; 416 nregs = (nregs + (nregs >> 8)) & 0x001f; 417 switch ((insn >> 23) & 0x3) { 418 case 0x0: /* ldmda */ 419 addr = addr - 0; 420 break; 421 case 0x1: /* ldmia */ 422 addr = addr + 0 + ((nregs - 1) << 2); 423 break; 424 case 0x2: /* ldmdb */ 425 addr = addr - 4; 426 break; 427 case 0x3: /* ldmib */ 428 addr = addr + 4 + ((nregs - 1) << 2); 429 break; 430 } 431 db_read_bytes(addr, 4, (char *)&addr); 432 return addr; 433 default: 434 panic("branch_taken: botch"); 435 } 436 } 437