1 /* $NetBSD: cpu.c,v 1.153 2022/03/03 06:26:05 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Mark Brinicombe. 5 * Copyright (c) 1995 Brini. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpu.c 38 * 39 * Probing and configuration for the master CPU 40 * 41 * Created : 10/10/95 42 */ 43 44 #include "opt_armfpe.h" 45 #include "opt_cputypes.h" 46 #include "opt_multiprocessor.h" 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.153 2022/03/03 06:26:05 riastradh Exp $"); 50 51 #include <sys/param.h> 52 53 #include <sys/conf.h> 54 #include <sys/cpu.h> 55 #include <sys/device.h> 56 #include <sys/kmem.h> 57 #include <sys/proc.h> 58 #include <sys/reboot.h> 59 #include <sys/systm.h> 60 61 #include <uvm/uvm_extern.h> 62 63 #include <arm/locore.h> 64 #include <arm/undefined.h> 65 #include <arm/cpu_topology.h> 66 67 extern const char *cpu_arch; 68 69 #ifdef MULTIPROCESSOR 70 #ifdef MPDEBUG 71 uint32_t arm_cpu_marker[2] __cacheline_aligned = { 0, 0 }; 72 #endif 73 74 #endif 75 76 /* Prototypes */ 77 void identify_arm_cpu(device_t, struct cpu_info *); 78 void identify_features(device_t, struct cpu_info *); 79 void identify_cortex_caches(device_t); 80 81 /* 82 * Identify the master (boot) CPU 83 */ 84 85 void 86 cpu_attach(device_t dv, cpuid_t id) 87 { 88 const char * const xname = device_xname(dv); 89 const int unit = device_unit(dv); 90 struct cpu_info *ci; 91 92 if (unit == 0) { 93 ci = curcpu(); 94 95 /* Read SCTLR from cpu */ 96 ci->ci_ctrl = cpu_control(0, 0); 97 98 /* Get the CPU ID from coprocessor 15 */ 99 ci->ci_cpuid = id; 100 ci->ci_arm_cpuid = cpu_idnum(); 101 ci->ci_arm_cputype = ci->ci_arm_cpuid & CPU_ID_CPU_MASK; 102 ci->ci_arm_cpurev = ci->ci_arm_cpuid & CPU_ID_REVISION_MASK; 103 104 /* 105 * Get other sysregs for BP. APs information is grabbed in 106 * cpu_init_secondary_processor. 107 */ 108 ci->ci_actlr = armreg_auxctl_read(); 109 ci->ci_revidr = armreg_revidr_read(); 110 } else { 111 #ifdef MULTIPROCESSOR 112 if ((boothowto & RB_MD1) != 0) { 113 aprint_naive("\n"); 114 aprint_normal(": multiprocessor boot disabled\n"); 115 return; 116 } 117 118 KASSERT(unit < MAXCPUS); 119 ci = &cpu_info_store[unit]; 120 121 KASSERT(cpu_info[unit] == NULL); 122 ci->ci_cpl = IPL_HIGH; 123 ci->ci_cpuid = id; 124 ci->ci_data.cpu_cc_freq = cpu_info_store[0].ci_data.cpu_cc_freq; 125 126 ci->ci_undefsave[2] = cpu_info_store[0].ci_undefsave[2]; 127 128 cpu_info[unit] = ci; 129 if (cpu_hatched_p(unit) == false) { 130 ci->ci_dev = dv; 131 device_set_private(dv, ci); 132 aprint_naive(": disabled\n"); 133 aprint_normal(": disabled (unresponsive)\n"); 134 return; 135 } 136 #else 137 aprint_naive(": disabled\n"); 138 aprint_normal(": disabled (uniprocessor kernel)\n"); 139 return; 140 #endif 141 } 142 143 ci->ci_dev = dv; 144 device_set_private(dv, ci); 145 146 arm_cpu_do_topology(ci); 147 148 evcnt_attach_dynamic(&ci->ci_arm700bugcount, EVCNT_TYPE_MISC, 149 NULL, xname, "arm700swibug"); 150 151 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_WRTBUF_0], EVCNT_TYPE_TRAP, 152 NULL, xname, "vector abort"); 153 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_WRTBUF_1], EVCNT_TYPE_TRAP, 154 NULL, xname, "terminal abort"); 155 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSERR_0], EVCNT_TYPE_TRAP, 156 NULL, xname, "external linefetch abort (S)"); 157 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSERR_1], EVCNT_TYPE_TRAP, 158 NULL, xname, "external linefetch abort (P)"); 159 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSERR_2], EVCNT_TYPE_TRAP, 160 NULL, xname, "external non-linefetch abort (S)"); 161 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSERR_3], EVCNT_TYPE_TRAP, 162 NULL, xname, "external non-linefetch abort (P)"); 163 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSTRNL1], EVCNT_TYPE_TRAP, 164 NULL, xname, "external translation abort (L1)"); 165 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSTRNL2], EVCNT_TYPE_TRAP, 166 NULL, xname, "external translation abort (L2)"); 167 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_ALIGN_0], EVCNT_TYPE_TRAP, 168 NULL, xname, "alignment abort (0)"); 169 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_ALIGN_1], EVCNT_TYPE_TRAP, 170 NULL, xname, "alignment abort (1)"); 171 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_TRANS_S], EVCNT_TYPE_TRAP, 172 NULL, xname, "translation abort (S)"); 173 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_TRANS_P], EVCNT_TYPE_TRAP, 174 NULL, xname, "translation abort (P)"); 175 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_DOMAIN_S], EVCNT_TYPE_TRAP, 176 NULL, xname, "domain abort (S)"); 177 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_DOMAIN_P], EVCNT_TYPE_TRAP, 178 NULL, xname, "domain abort (P)"); 179 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_PERM_S], EVCNT_TYPE_TRAP, 180 NULL, xname, "permission abort (S)"); 181 evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_PERM_P], EVCNT_TYPE_TRAP, 182 NULL, xname, "permission abort (P)"); 183 evcnt_attach_dynamic_nozero(&ci->ci_und_ev, EVCNT_TYPE_TRAP, 184 NULL, xname, "undefined insn traps"); 185 evcnt_attach_dynamic_nozero(&ci->ci_und_cp15_ev, EVCNT_TYPE_TRAP, 186 NULL, xname, "undefined cp15 insn traps"); 187 188 ci->ci_kfpu_spl = -1; 189 190 #ifdef MULTIPROCESSOR 191 if (unit != 0) { 192 mi_cpu_attach(ci); 193 #ifdef ARM_MMU_EXTENDED 194 pmap_tlb_info_attach(&pmap_tlb0_info, ci); 195 #endif 196 } 197 #endif 198 199 identify_arm_cpu(dv, ci); 200 201 #ifdef CPU_STRONGARM 202 if (ci->ci_arm_cputype == CPU_ID_SA110 && 203 ci->ci_arm_cpurev < 3) { 204 aprint_normal_dev(dv, "SA-110 with bugged STM^ instruction\n"); 205 } 206 #endif 207 208 #ifdef CPU_ARM8 209 if ((ci->ci_arm_cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM810) { 210 int clock = arm8_clock_config(0, 0); 211 char *fclk; 212 aprint_normal_dev(dv, "ARM810 cp15=%02x", clock); 213 aprint_normal(" clock:%s", (clock & 1) ? " dynamic" : ""); 214 aprint_normal("%s", (clock & 2) ? " sync" : ""); 215 switch ((clock >> 2) & 3) { 216 case 0: 217 fclk = "bus clock"; 218 break; 219 case 1: 220 fclk = "ref clock"; 221 break; 222 case 3: 223 fclk = "pll"; 224 break; 225 default: 226 fclk = "illegal"; 227 break; 228 } 229 aprint_normal(" fclk source=%s\n", fclk); 230 } 231 #endif 232 233 vfp_attach(ci); 234 } 235 236 enum cpu_class { 237 CPU_CLASS_NONE, 238 CPU_CLASS_ARM2, 239 CPU_CLASS_ARM2AS, 240 CPU_CLASS_ARM3, 241 CPU_CLASS_ARM6, 242 CPU_CLASS_ARM7, 243 CPU_CLASS_ARM7TDMI, 244 CPU_CLASS_ARM8, 245 CPU_CLASS_ARM9TDMI, 246 CPU_CLASS_ARM9ES, 247 CPU_CLASS_ARM9EJS, 248 CPU_CLASS_ARM10E, 249 CPU_CLASS_ARM10EJ, 250 CPU_CLASS_SA1, 251 CPU_CLASS_XSCALE, 252 CPU_CLASS_ARM11J, 253 CPU_CLASS_ARMV4, 254 CPU_CLASS_CORTEX, 255 CPU_CLASS_PJ4B, 256 }; 257 258 static const char * const generic_steppings[16] = { 259 "rev 0", "rev 1", "rev 2", "rev 3", 260 "rev 4", "rev 5", "rev 6", "rev 7", 261 "rev 8", "rev 9", "rev 10", "rev 11", 262 "rev 12", "rev 13", "rev 14", "rev 15", 263 }; 264 265 static const char * const pN_steppings[16] = { 266 "*p0", "*p1", "*p2", "*p3", "*p4", "*p5", "*p6", "*p7", 267 "*p8", "*p9", "*p10", "*p11", "*p12", "*p13", "*p14", "*p15", 268 }; 269 270 static const char * const sa110_steppings[16] = { 271 "rev 0", "step J", "step K", "step S", 272 "step T", "rev 5", "rev 6", "rev 7", 273 "rev 8", "rev 9", "rev 10", "rev 11", 274 "rev 12", "rev 13", "rev 14", "rev 15", 275 }; 276 277 static const char * const sa1100_steppings[16] = { 278 "rev 0", "step B", "step C", "rev 3", 279 "rev 4", "rev 5", "rev 6", "rev 7", 280 "step D", "step E", "rev 10" "step G", 281 "rev 12", "rev 13", "rev 14", "rev 15", 282 }; 283 284 static const char * const sa1110_steppings[16] = { 285 "step A-0", "rev 1", "rev 2", "rev 3", 286 "step B-0", "step B-1", "step B-2", "step B-3", 287 "step B-4", "step B-5", "rev 10", "rev 11", 288 "rev 12", "rev 13", "rev 14", "rev 15", 289 }; 290 291 static const char * const ixp12x0_steppings[16] = { 292 "(IXP1200 step A)", "(IXP1200 step B)", 293 "rev 2", "(IXP1200 step C)", 294 "(IXP1200 step D)", "(IXP1240/1250 step A)", 295 "(IXP1240 step B)", "(IXP1250 step B)", 296 "rev 8", "rev 9", "rev 10", "rev 11", 297 "rev 12", "rev 13", "rev 14", "rev 15", 298 }; 299 300 static const char * const xscale_steppings[16] = { 301 "step A-0", "step A-1", "step B-0", "step C-0", 302 "step D-0", "rev 5", "rev 6", "rev 7", 303 "rev 8", "rev 9", "rev 10", "rev 11", 304 "rev 12", "rev 13", "rev 14", "rev 15", 305 }; 306 307 static const char * const i80321_steppings[16] = { 308 "step A-0", "step B-0", "rev 2", "rev 3", 309 "rev 4", "rev 5", "rev 6", "rev 7", 310 "rev 8", "rev 9", "rev 10", "rev 11", 311 "rev 12", "rev 13", "rev 14", "rev 15", 312 }; 313 314 static const char * const i80219_steppings[16] = { 315 "step A-0", "rev 1", "rev 2", "rev 3", 316 "rev 4", "rev 5", "rev 6", "rev 7", 317 "rev 8", "rev 9", "rev 10", "rev 11", 318 "rev 12", "rev 13", "rev 14", "rev 15", 319 }; 320 321 /* Steppings for PXA2[15]0 */ 322 static const char * const pxa2x0_steppings[16] = { 323 "step A-0", "step A-1", "step B-0", "step B-1", 324 "step B-2", "step C-0", "rev 6", "rev 7", 325 "rev 8", "rev 9", "rev 10", "rev 11", 326 "rev 12", "rev 13", "rev 14", "rev 15", 327 }; 328 329 /* Steppings for PXA255/26x. 330 * rev 5: PXA26x B0, rev 6: PXA255 A0 331 */ 332 static const char * const pxa255_steppings[16] = { 333 "rev 0", "rev 1", "rev 2", "step A-0", 334 "rev 4", "step B-0", "step A-0", "rev 7", 335 "rev 8", "rev 9", "rev 10", "rev 11", 336 "rev 12", "rev 13", "rev 14", "rev 15", 337 }; 338 339 /* Stepping for PXA27x */ 340 static const char * const pxa27x_steppings[16] = { 341 "step A-0", "step A-1", "step B-0", "step B-1", 342 "step C-0", "rev 5", "rev 6", "rev 7", 343 "rev 8", "rev 9", "rev 10", "rev 11", 344 "rev 12", "rev 13", "rev 14", "rev 15", 345 }; 346 347 static const char * const ixp425_steppings[16] = { 348 "step 0", "rev 1", "rev 2", "rev 3", 349 "rev 4", "rev 5", "rev 6", "rev 7", 350 "rev 8", "rev 9", "rev 10", "rev 11", 351 "rev 12", "rev 13", "rev 14", "rev 15", 352 }; 353 354 struct cpuidtab { 355 uint32_t cpuid; 356 enum cpu_class cpu_class; 357 const char *cpu_classname; 358 const char * const *cpu_steppings; 359 char cpu_arch[8]; 360 }; 361 362 const struct cpuidtab cpuids[] = { 363 { CPU_ID_ARM2, CPU_CLASS_ARM2, "ARM2", 364 generic_steppings, "2" }, 365 { CPU_ID_ARM250, CPU_CLASS_ARM2AS, "ARM250", 366 generic_steppings, "2" }, 367 368 { CPU_ID_ARM3, CPU_CLASS_ARM3, "ARM3", 369 generic_steppings, "2A" }, 370 371 { CPU_ID_ARM600, CPU_CLASS_ARM6, "ARM600", 372 generic_steppings, "3" }, 373 { CPU_ID_ARM610, CPU_CLASS_ARM6, "ARM610", 374 generic_steppings, "3" }, 375 { CPU_ID_ARM620, CPU_CLASS_ARM6, "ARM620", 376 generic_steppings, "3" }, 377 378 { CPU_ID_ARM700, CPU_CLASS_ARM7, "ARM700", 379 generic_steppings, "3" }, 380 { CPU_ID_ARM710, CPU_CLASS_ARM7, "ARM710", 381 generic_steppings, "3" }, 382 { CPU_ID_ARM7500, CPU_CLASS_ARM7, "ARM7500", 383 generic_steppings, "3" }, 384 { CPU_ID_ARM710A, CPU_CLASS_ARM7, "ARM710a", 385 generic_steppings, "3" }, 386 { CPU_ID_ARM7500FE, CPU_CLASS_ARM7, "ARM7500FE", 387 generic_steppings, "3" }, 388 389 { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810", 390 generic_steppings, "4" }, 391 392 { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", 393 sa110_steppings, "4" }, 394 { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100", 395 sa1100_steppings, "4" }, 396 { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110", 397 sa1110_steppings, "4" }, 398 399 { CPU_ID_FA526, CPU_CLASS_ARMV4, "FA526", 400 generic_steppings, "4" }, 401 402 { CPU_ID_IXP1200, CPU_CLASS_SA1, "IXP1200", 403 ixp12x0_steppings, "4" }, 404 405 { CPU_ID_ARM710T, CPU_CLASS_ARM7TDMI, "ARM710T", 406 generic_steppings, "4T" }, 407 { CPU_ID_ARM720T, CPU_CLASS_ARM7TDMI, "ARM720T", 408 generic_steppings, "4T" }, 409 { CPU_ID_ARM740T8K, CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)", 410 generic_steppings, "4T" }, 411 { CPU_ID_ARM740T4K, CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)", 412 generic_steppings, "4T" }, 413 { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T", 414 generic_steppings, "4T" }, 415 { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T", 416 generic_steppings, "4T" }, 417 { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T", 418 generic_steppings, "4T" }, 419 { CPU_ID_TI925T, CPU_CLASS_ARM9TDMI, "TI ARM925T", 420 generic_steppings, "4T" }, 421 422 { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S", 423 generic_steppings, "5TE" }, 424 { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S", 425 generic_steppings, "5TE" }, 426 { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", 427 generic_steppings, "5TE" }, 428 { CPU_ID_MV88SV131, CPU_CLASS_ARM9ES, "Sheeva 88SV131", 429 generic_steppings, "5TE" }, 430 { CPU_ID_MV88FR571_VD, CPU_CLASS_ARM9ES, "Sheeva 88FR571-vd", 431 generic_steppings, "5TE" }, 432 433 { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200", 434 xscale_steppings, "5TE" }, 435 436 { CPU_ID_80321_400, CPU_CLASS_XSCALE, "i80321 400MHz", 437 i80321_steppings, "5TE" }, 438 { CPU_ID_80321_600, CPU_CLASS_XSCALE, "i80321 600MHz", 439 i80321_steppings, "5TE" }, 440 { CPU_ID_80321_400_B0, CPU_CLASS_XSCALE, "i80321 400MHz", 441 i80321_steppings, "5TE" }, 442 { CPU_ID_80321_600_B0, CPU_CLASS_XSCALE, "i80321 600MHz", 443 i80321_steppings, "5TE" }, 444 445 { CPU_ID_80219_400, CPU_CLASS_XSCALE, "i80219 400MHz", 446 i80219_steppings, "5TE" }, 447 { CPU_ID_80219_600, CPU_CLASS_XSCALE, "i80219 600MHz", 448 i80219_steppings, "5TE" }, 449 450 { CPU_ID_PXA27X, CPU_CLASS_XSCALE, "PXA27x", 451 pxa27x_steppings, "5TE" }, 452 { CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250", 453 pxa2x0_steppings, "5TE" }, 454 { CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210", 455 pxa2x0_steppings, "5TE" }, 456 { CPU_ID_PXA250B, CPU_CLASS_XSCALE, "PXA250", 457 pxa2x0_steppings, "5TE" }, 458 { CPU_ID_PXA210B, CPU_CLASS_XSCALE, "PXA210", 459 pxa2x0_steppings, "5TE" }, 460 { CPU_ID_PXA250C, CPU_CLASS_XSCALE, "PXA255/26x", 461 pxa255_steppings, "5TE" }, 462 { CPU_ID_PXA210C, CPU_CLASS_XSCALE, "PXA210", 463 pxa2x0_steppings, "5TE" }, 464 465 { CPU_ID_IXP425_533, CPU_CLASS_XSCALE, "IXP425 533MHz", 466 ixp425_steppings, "5TE" }, 467 { CPU_ID_IXP425_400, CPU_CLASS_XSCALE, "IXP425 400MHz", 468 ixp425_steppings, "5TE" }, 469 { CPU_ID_IXP425_266, CPU_CLASS_XSCALE, "IXP425 266MHz", 470 ixp425_steppings, "5TE" }, 471 472 { CPU_ID_ARM1020E, CPU_CLASS_ARM10E, "ARM1020E", 473 generic_steppings, "5TE" }, 474 { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022E-S", 475 generic_steppings, "5TE" }, 476 477 { CPU_ID_ARM1026EJS, CPU_CLASS_ARM10EJ, "ARM1026EJ-S", 478 generic_steppings, "5TEJ" }, 479 { CPU_ID_ARM926EJS, CPU_CLASS_ARM9EJS, "ARM926EJ-S r0", 480 pN_steppings, "5TEJ" }, 481 482 { CPU_ID_ARM1136JS, CPU_CLASS_ARM11J, "ARM1136J-S r0", 483 pN_steppings, "6J" }, 484 { CPU_ID_ARM1136JSR1, CPU_CLASS_ARM11J, "ARM1136J-S r1", 485 pN_steppings, "6J" }, 486 #if 0 487 /* The ARM1156T2-S only has a memory protection unit */ 488 { CPU_ID_ARM1156T2S, CPU_CLASS_ARM11J, "ARM1156T2-S r0", 489 pN_steppings, "6T2" }, 490 #endif 491 { CPU_ID_ARM1176JZS, CPU_CLASS_ARM11J, "ARM1176JZ-S r0", 492 pN_steppings, "6ZK" }, 493 494 { CPU_ID_ARM11MPCORE, CPU_CLASS_ARM11J, "ARM11 MPCore", 495 generic_steppings, "6K" }, 496 497 { CPU_ID_CORTEXA5R0, CPU_CLASS_CORTEX, "Cortex-A5 r0", 498 pN_steppings, "7A" }, 499 { CPU_ID_CORTEXA7R0, CPU_CLASS_CORTEX, "Cortex-A7 r0", 500 pN_steppings, "7A" }, 501 { CPU_ID_CORTEXA8R1, CPU_CLASS_CORTEX, "Cortex-A8 r1", 502 pN_steppings, "7A" }, 503 { CPU_ID_CORTEXA8R2, CPU_CLASS_CORTEX, "Cortex-A8 r2", 504 pN_steppings, "7A" }, 505 { CPU_ID_CORTEXA8R3, CPU_CLASS_CORTEX, "Cortex-A8 r3", 506 pN_steppings, "7A" }, 507 { CPU_ID_CORTEXA9R1, CPU_CLASS_CORTEX, "Cortex-A9 r1", 508 pN_steppings, "7A" }, 509 { CPU_ID_CORTEXA9R2, CPU_CLASS_CORTEX, "Cortex-A9 r2", 510 pN_steppings, "7A" }, 511 { CPU_ID_CORTEXA9R3, CPU_CLASS_CORTEX, "Cortex-A9 r3", 512 pN_steppings, "7A" }, 513 { CPU_ID_CORTEXA9R4, CPU_CLASS_CORTEX, "Cortex-A9 r4", 514 pN_steppings, "7A" }, 515 { CPU_ID_CORTEXA12R0, CPU_CLASS_CORTEX, "Cortex-A17(A12) r0", /* A12 was rebranded A17 */ 516 pN_steppings, "7A" }, 517 { CPU_ID_CORTEXA15R2, CPU_CLASS_CORTEX, "Cortex-A15 r2", 518 pN_steppings, "7A" }, 519 { CPU_ID_CORTEXA15R3, CPU_CLASS_CORTEX, "Cortex-A15 r3", 520 pN_steppings, "7A" }, 521 { CPU_ID_CORTEXA15R4, CPU_CLASS_CORTEX, "Cortex-A15 r4", 522 pN_steppings, "7A" }, 523 { CPU_ID_CORTEXA17R1, CPU_CLASS_CORTEX, "Cortex-A17 r1", 524 pN_steppings, "7A" }, 525 { CPU_ID_CORTEXA35R0, CPU_CLASS_CORTEX, "Cortex-A35 r0", 526 pN_steppings, "8A" }, 527 { CPU_ID_CORTEXA53R0, CPU_CLASS_CORTEX, "Cortex-A53 r0", 528 pN_steppings, "8A" }, 529 { CPU_ID_CORTEXA57R0, CPU_CLASS_CORTEX, "Cortex-A57 r0", 530 pN_steppings, "8A" }, 531 { CPU_ID_CORTEXA57R1, CPU_CLASS_CORTEX, "Cortex-A57 r1", 532 pN_steppings, "8A" }, 533 { CPU_ID_CORTEXA72R0, CPU_CLASS_CORTEX, "Cortex-A72 r0", 534 pN_steppings, "8A" }, 535 536 { CPU_ID_MV88SV581X_V6, CPU_CLASS_PJ4B, "Sheeva 88SV581x", 537 generic_steppings }, 538 { CPU_ID_ARM_88SV581X_V6, CPU_CLASS_PJ4B, "Sheeva 88SV581x", 539 generic_steppings }, 540 { CPU_ID_MV88SV581X_V7, CPU_CLASS_PJ4B, "Sheeva 88SV581x", 541 generic_steppings }, 542 { CPU_ID_ARM_88SV581X_V7, CPU_CLASS_PJ4B, "Sheeva 88SV581x", 543 generic_steppings }, 544 { CPU_ID_MV88SV584X_V6, CPU_CLASS_PJ4B, "Sheeva 88SV584x", 545 generic_steppings }, 546 { CPU_ID_ARM_88SV584X_V6, CPU_CLASS_PJ4B, "Sheeva 88SV584x", 547 generic_steppings }, 548 { CPU_ID_MV88SV584X_V7, CPU_CLASS_PJ4B, "Sheeva 88SV584x", 549 generic_steppings }, 550 551 552 { 0, CPU_CLASS_NONE, NULL, NULL, "" } 553 }; 554 555 struct cpu_classtab { 556 const char *class_name; 557 const char *class_option; 558 }; 559 560 const struct cpu_classtab cpu_classes[] = { 561 [CPU_CLASS_NONE] = { "unknown", NULL }, 562 [CPU_CLASS_ARM2] = { "ARM2", "CPU_ARM2" }, 563 [CPU_CLASS_ARM2AS] = { "ARM2as", "CPU_ARM250" }, 564 [CPU_CLASS_ARM3] = { "ARM3", "CPU_ARM3" }, 565 [CPU_CLASS_ARM6] = { "ARM6", "CPU_ARM6" }, 566 [CPU_CLASS_ARM7] = { "ARM7", "CPU_ARM7" }, 567 [CPU_CLASS_ARM7TDMI] = { "ARM7TDMI", "CPU_ARM7TDMI" }, 568 [CPU_CLASS_ARM8] = { "ARM8", "CPU_ARM8" }, 569 [CPU_CLASS_ARM9TDMI] = { "ARM9TDMI", NULL }, 570 [CPU_CLASS_ARM9ES] = { "ARM9E-S", "CPU_ARM9E" }, 571 [CPU_CLASS_ARM9EJS] = { "ARM9EJ-S", "CPU_ARM9E" }, 572 [CPU_CLASS_ARM10E] = { "ARM10E", "CPU_ARM10" }, 573 [CPU_CLASS_ARM10EJ] = { "ARM10EJ", "CPU_ARM10" }, 574 [CPU_CLASS_SA1] = { "SA-1", "CPU_SA110" }, 575 [CPU_CLASS_XSCALE] = { "XScale", "CPU_XSCALE_..." }, 576 [CPU_CLASS_ARM11J] = { "ARM11J", "CPU_ARM11" }, 577 [CPU_CLASS_ARMV4] = { "ARMv4", "CPU_ARMV4" }, 578 [CPU_CLASS_CORTEX] = { "Cortex", "CPU_CORTEX" }, 579 [CPU_CLASS_PJ4B] = { "Marvell", "CPU_PJ4B" }, 580 }; 581 582 /* 583 * Report the type of the specified arm processor. This uses the generic and 584 * arm specific information in the CPU structure to identify the processor. 585 * The remaining fields in the CPU structure are filled in appropriately. 586 */ 587 588 static const char * const wtnames[] = { 589 "write-through", 590 "write-back", 591 "write-back", 592 "**unknown 3**", 593 "**unknown 4**", 594 "write-back-locking", /* XXX XScale-specific? */ 595 "write-back-locking-A", 596 "write-back-locking-B", 597 "**unknown 8**", 598 "**unknown 9**", 599 "**unknown 10**", 600 "**unknown 11**", 601 "write-back", 602 "write-back-locking-line", 603 "write-back-locking-C", 604 "write-back-locking-D", 605 }; 606 607 static void 608 print_cache_info(device_t dv, struct arm_cache_info *info, u_int level) 609 { 610 if (info->cache_unified) { 611 aprint_normal_dev(dv, "L%u %dKB/%dB %d-way (%u set) %s %cI%cT Unified cache\n", 612 level + 1, 613 info->dcache_size / 1024, 614 info->dcache_line_size, info->dcache_ways, 615 info->dcache_sets ? info->dcache_sets : 616 info->dcache_size / 617 (info->dcache_line_size * info->dcache_ways), 618 wtnames[info->cache_type], 619 info->dcache_type & CACHE_TYPE_PIxx ? 'P' : 'V', 620 info->dcache_type & CACHE_TYPE_xxPT ? 'P' : 'V'); 621 } else { 622 aprint_normal_dev(dv, "L%u %dKB/%dB %d-way (%u set) %cI%cT Instruction cache\n", 623 level + 1, 624 info->icache_size / 1024, 625 info->icache_line_size, info->icache_ways, 626 info->icache_sets ? info->icache_sets : 627 info->icache_size / 628 (info->icache_line_size * info->icache_ways), 629 info->icache_type & CACHE_TYPE_PIxx ? 'P' : 'V', 630 info->icache_type & CACHE_TYPE_xxPT ? 'P' : 'V'); 631 aprint_normal_dev(dv, "L%u %dKB/%dB %d-way (%u set) %s %cI%cT Data cache\n", 632 level + 1, 633 info->dcache_size / 1024, 634 info->dcache_line_size, info->dcache_ways, 635 info->dcache_sets ? info->dcache_sets : 636 info->dcache_size / 637 (info->dcache_line_size * info->dcache_ways), 638 wtnames[info->cache_type], 639 info->dcache_type & CACHE_TYPE_PIxx ? 'P' : 'V', 640 info->dcache_type & CACHE_TYPE_xxPT ? 'P' : 'V'); 641 } 642 } 643 644 static enum cpu_class 645 identify_arm_model(uint32_t cpuid, char *buf, size_t len) 646 { 647 enum cpu_class cpu_class = CPU_CLASS_NONE; 648 for (const struct cpuidtab *id = cpuids; id->cpuid != 0; id++) { 649 if (id->cpuid == (cpuid & CPU_ID_CPU_MASK)) { 650 const char *steppingstr = 651 id->cpu_steppings[cpuid & CPU_ID_REVISION_MASK]; 652 cpu_arch = id->cpu_arch; 653 cpu_class = id->cpu_class; 654 snprintf(buf, len, "%s%s%s (%s V%s core)", 655 id->cpu_classname, 656 steppingstr[0] == '*' ? "" : " ", 657 &steppingstr[steppingstr[0] == '*'], 658 cpu_classes[cpu_class].class_name, 659 cpu_arch); 660 return cpu_class; 661 } 662 } 663 664 snprintf(buf, len, "unknown CPU (ID = 0x%x)", cpuid); 665 return cpu_class; 666 } 667 668 void 669 identify_arm_cpu(device_t dv, struct cpu_info *ci) 670 { 671 const uint32_t arm_cpuid = ci->ci_arm_cpuid; 672 const char * const xname = device_xname(dv); 673 char model[128]; 674 const char *m; 675 676 if (arm_cpuid == 0) { 677 aprint_error("Processor failed probe - no CPU ID\n"); 678 return; 679 } 680 681 const enum cpu_class cpu_class = identify_arm_model(arm_cpuid, 682 model, sizeof(model)); 683 if (ci->ci_cpuid == 0) { 684 m = cpu_getmodel(); 685 if (m == NULL || *m == 0) 686 cpu_setmodel("%s", model); 687 } 688 689 if (ci->ci_data.cpu_cc_freq != 0) { 690 char freqbuf[10]; 691 humanize_number(freqbuf, sizeof(freqbuf), ci->ci_data.cpu_cc_freq, 692 "Hz", 1000); 693 694 aprint_naive(": %s %s\n", freqbuf, model); 695 aprint_normal(": %s %s\n", freqbuf, model); 696 } else { 697 aprint_naive(": %s\n", model); 698 aprint_normal(": %s\n", model); 699 } 700 701 aprint_debug_dev(dv, "midr: %#x\n", arm_cpuid); 702 703 aprint_normal("%s:", xname); 704 705 switch (cpu_class) { 706 case CPU_CLASS_ARM6: 707 case CPU_CLASS_ARM7: 708 case CPU_CLASS_ARM7TDMI: 709 case CPU_CLASS_ARM8: 710 if ((ci->ci_ctrl & CPU_CONTROL_IDC_ENABLE) == 0) 711 aprint_normal(" IDC disabled"); 712 else 713 aprint_normal(" IDC enabled"); 714 break; 715 case CPU_CLASS_ARM9TDMI: 716 case CPU_CLASS_ARM9ES: 717 case CPU_CLASS_ARM9EJS: 718 case CPU_CLASS_ARM10E: 719 case CPU_CLASS_ARM10EJ: 720 case CPU_CLASS_SA1: 721 case CPU_CLASS_XSCALE: 722 case CPU_CLASS_ARM11J: 723 case CPU_CLASS_ARMV4: 724 case CPU_CLASS_CORTEX: 725 case CPU_CLASS_PJ4B: 726 if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0) 727 aprint_normal(" DC disabled"); 728 else 729 aprint_normal(" DC enabled"); 730 if ((ci->ci_ctrl & CPU_CONTROL_IC_ENABLE) == 0) 731 aprint_normal(" IC disabled"); 732 else 733 aprint_normal(" IC enabled"); 734 break; 735 default: 736 break; 737 } 738 if ((ci->ci_ctrl & CPU_CONTROL_WBUF_ENABLE) == 0) 739 aprint_normal(" WB disabled"); 740 else 741 aprint_normal(" WB enabled"); 742 743 if (ci->ci_ctrl & CPU_CONTROL_LABT_ENABLE) 744 aprint_normal(" LABT"); 745 else 746 aprint_normal(" EABT"); 747 748 if (ci->ci_ctrl & CPU_CONTROL_BPRD_ENABLE) 749 aprint_normal(" branch prediction enabled"); 750 751 aprint_normal("\n"); 752 753 if (CPU_ID_CORTEX_P(arm_cpuid) || 754 CPU_ID_ARM11_P(arm_cpuid) || 755 CPU_ID_MV88SV58XX_P(arm_cpuid)) { 756 if ((arm_cpuid & CPU_ID_CPU_MASK) != CPU_ID_ARM1136JS && 757 (arm_cpuid & CPU_ID_CPU_MASK) != CPU_ID_ARM1176JZS) { 758 identify_features(dv, ci); 759 } 760 } 761 762 /* Print cache info. */ 763 if (arm_pcache.icache_line_size != 0 || arm_pcache.dcache_line_size != 0) { 764 print_cache_info(dv, &arm_pcache, 0); 765 } 766 if (arm_scache.icache_line_size != 0 || arm_scache.dcache_line_size != 0) { 767 print_cache_info(dv, &arm_scache, 1); 768 } 769 770 771 switch (cpu_class) { 772 #ifdef CPU_ARM6 773 case CPU_CLASS_ARM6: 774 #endif 775 #ifdef CPU_ARM7 776 case CPU_CLASS_ARM7: 777 #endif 778 #ifdef CPU_ARM7TDMI 779 case CPU_CLASS_ARM7TDMI: 780 #endif 781 #ifdef CPU_ARM8 782 case CPU_CLASS_ARM8: 783 #endif 784 #ifdef CPU_ARM9 785 case CPU_CLASS_ARM9TDMI: 786 #endif 787 #if defined(CPU_ARM9E) || defined(CPU_SHEEVA) 788 case CPU_CLASS_ARM9ES: 789 case CPU_CLASS_ARM9EJS: 790 #endif 791 #ifdef CPU_ARM10 792 case CPU_CLASS_ARM10E: 793 case CPU_CLASS_ARM10EJ: 794 #endif 795 #if defined(CPU_SA110) || defined(CPU_SA1100) || \ 796 defined(CPU_SA1110) || defined(CPU_IXP12X0) 797 case CPU_CLASS_SA1: 798 #endif 799 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 800 defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) 801 case CPU_CLASS_XSCALE: 802 #endif 803 #if defined(CPU_ARM11) 804 case CPU_CLASS_ARM11J: 805 #endif 806 #if defined(CPU_CORTEX) 807 case CPU_CLASS_CORTEX: 808 #endif 809 #if defined(CPU_PJ4B) 810 case CPU_CLASS_PJ4B: 811 #endif 812 #if defined(CPU_FA526) 813 case CPU_CLASS_ARMV4: 814 #endif 815 break; 816 default: 817 if (cpu_classes[cpu_class].class_option == NULL) { 818 aprint_error_dev(dv, "%s does not fully support this CPU.\n", 819 ostype); 820 } else { 821 aprint_error_dev(dv, "This kernel does not fully support " 822 "this CPU.\n"); 823 aprint_normal_dev(dv, "Recompile with \"options %s\" to " 824 "correct this.\n", cpu_classes[cpu_class].class_option); 825 } 826 break; 827 } 828 } 829 830 extern int cpu_instruction_set_attributes[6]; 831 extern int cpu_memory_model_features[4]; 832 extern int cpu_processor_features[2]; 833 extern int cpu_simd_present; 834 extern int cpu_simdex_present; 835 836 void 837 identify_features(device_t dv, struct cpu_info *ci) 838 { 839 const int unit = device_unit(dv); 840 841 aprint_debug_dev(dv, "sctlr: %#x\n", ci->ci_ctrl); 842 aprint_debug_dev(dv, "actlr: %#x\n", ci->ci_actlr); 843 aprint_debug_dev(dv, "revidr: %#x\n", ci->ci_revidr); 844 #ifdef MULTIPROCESSOR 845 aprint_debug_dev(dv, "mpidr: %#x\n", ci->ci_mpidr); 846 #endif 847 848 if (unit != 0) 849 return; 850 851 cpu_instruction_set_attributes[0] = armreg_isar0_read(); 852 cpu_instruction_set_attributes[1] = armreg_isar1_read(); 853 cpu_instruction_set_attributes[2] = armreg_isar2_read(); 854 cpu_instruction_set_attributes[3] = armreg_isar3_read(); 855 cpu_instruction_set_attributes[4] = armreg_isar4_read(); 856 cpu_instruction_set_attributes[5] = armreg_isar5_read(); 857 858 cpu_hwdiv_present = 859 ((cpu_instruction_set_attributes[0] >> 24) & 0x0f) >= 2; 860 cpu_simd_present = 861 ((cpu_instruction_set_attributes[3] >> 4) & 0x0f) >= 3; 862 cpu_simdex_present = cpu_simd_present 863 && ((cpu_instruction_set_attributes[1] >> 12) & 0x0f) >= 2; 864 cpu_synchprim_present = 865 ((cpu_instruction_set_attributes[3] >> 8) & 0xf0) 866 | ((cpu_instruction_set_attributes[4] >> 20) & 0x0f); 867 868 cpu_memory_model_features[0] = armreg_mmfr0_read(); 869 cpu_memory_model_features[1] = armreg_mmfr1_read(); 870 cpu_memory_model_features[2] = armreg_mmfr2_read(); 871 cpu_memory_model_features[3] = armreg_mmfr3_read(); 872 873 #if 0 874 if (__SHIFTOUT(cpu_memory_model_features[3], __BITS(23,20))) { 875 /* 876 * Updates to the translation tables do not require a clean 877 * to the point of unification to ensure visibility by 878 * subsequent translation table walks. 879 */ 880 pmap_needs_pte_sync = 0; 881 } 882 #endif 883 884 cpu_processor_features[0] = armreg_pfr0_read(); 885 cpu_processor_features[1] = armreg_pfr1_read(); 886 887 aprint_debug_dev(dv, 888 "isar: [0]=%#x [1]=%#x [2]=%#x [3]=%#x, [4]=%#x, [5]=%#x\n", 889 cpu_instruction_set_attributes[0], 890 cpu_instruction_set_attributes[1], 891 cpu_instruction_set_attributes[2], 892 cpu_instruction_set_attributes[3], 893 cpu_instruction_set_attributes[4], 894 cpu_instruction_set_attributes[5]); 895 aprint_debug_dev(dv, 896 "mmfr: [0]=%#x [1]=%#x [2]=%#x [3]=%#x\n", 897 cpu_memory_model_features[0], cpu_memory_model_features[1], 898 cpu_memory_model_features[2], cpu_memory_model_features[3]); 899 aprint_debug_dev(dv, 900 "pfr: [0]=%#x [1]=%#x\n", 901 cpu_processor_features[0], cpu_processor_features[1]); 902 } 903 904 #ifdef _ARM_ARCH_6 905 int 906 cpu_maxproc_hook(int nmaxproc) 907 { 908 909 #ifdef ARM_MMU_EXTENDED 910 return pmap_maxproc_set(nmaxproc); 911 #else 912 return 0; 913 #endif 914 } 915 #endif 916