1 /* $NetBSD: cpu.c,v 1.78 2011/03/10 08:07:08 bsh Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Mark Brinicombe. 5 * Copyright (c) 1995 Brini. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpu.c 38 * 39 * Probing and configuration for the master CPU 40 * 41 * Created : 10/10/95 42 */ 43 44 #include "opt_armfpe.h" 45 #include "opt_multiprocessor.h" 46 47 #include <sys/param.h> 48 49 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.78 2011/03/10 08:07:08 bsh Exp $"); 50 51 #include <sys/systm.h> 52 #include <sys/malloc.h> 53 #include <sys/device.h> 54 #include <sys/proc.h> 55 #include <sys/conf.h> 56 #include <uvm/uvm_extern.h> 57 #include <machine/cpu.h> 58 59 #include <arm/cpuconf.h> 60 #include <arm/undefined.h> 61 62 #ifdef ARMFPE 63 #include <machine/bootconfig.h> /* For boot args */ 64 #include <arm/fpe-arm/armfpe.h> 65 #endif 66 67 #ifdef FPU_VFP 68 #include <arm/vfpvar.h> 69 #endif 70 71 char cpu_model[256]; 72 73 /* Prototypes */ 74 void identify_arm_cpu(struct device *dv, struct cpu_info *); 75 76 /* 77 * Identify the master (boot) CPU 78 */ 79 80 void 81 cpu_attach(struct device *dv) 82 { 83 int usearmfpe; 84 85 usearmfpe = 1; /* when compiled in, its enabled by default */ 86 87 curcpu()->ci_dev = dv; 88 89 evcnt_attach_dynamic(&curcpu()->ci_arm700bugcount, EVCNT_TYPE_MISC, 90 NULL, dv->dv_xname, "arm700swibug"); 91 92 /* Get the CPU ID from coprocessor 15 */ 93 94 curcpu()->ci_arm_cpuid = cpu_id(); 95 curcpu()->ci_arm_cputype = curcpu()->ci_arm_cpuid & CPU_ID_CPU_MASK; 96 curcpu()->ci_arm_cpurev = 97 curcpu()->ci_arm_cpuid & CPU_ID_REVISION_MASK; 98 99 identify_arm_cpu(dv, curcpu()); 100 101 if (curcpu()->ci_arm_cputype == CPU_ID_SA110 && 102 curcpu()->ci_arm_cpurev < 3) { 103 aprint_normal("%s: SA-110 with bugged STM^ instruction\n", 104 dv->dv_xname); 105 } 106 107 #ifdef CPU_ARM8 108 if ((curcpu()->ci_arm_cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM810) { 109 int clock = arm8_clock_config(0, 0); 110 char *fclk; 111 aprint_normal("%s: ARM810 cp15=%02x", dv->dv_xname, clock); 112 aprint_normal(" clock:%s", (clock & 1) ? " dynamic" : ""); 113 aprint_normal("%s", (clock & 2) ? " sync" : ""); 114 switch ((clock >> 2) & 3) { 115 case 0: 116 fclk = "bus clock"; 117 break; 118 case 1: 119 fclk = "ref clock"; 120 break; 121 case 3: 122 fclk = "pll"; 123 break; 124 default: 125 fclk = "illegal"; 126 break; 127 } 128 aprint_normal(" fclk source=%s\n", fclk); 129 } 130 #endif 131 132 #ifdef ARMFPE 133 /* 134 * Ok now we test for an FPA 135 * At this point no floating point emulator has been installed. 136 * This means any FP instruction will cause undefined exception. 137 * We install a temporay coproc 1 handler which will modify 138 * undefined_test if it is called. 139 * We then try to read the FP status register. If undefined_test 140 * has been decremented then the instruction was not handled by 141 * an FPA so we know the FPA is missing. If undefined_test is 142 * still 1 then we know the instruction was handled by an FPA. 143 * We then remove our test handler and look at the 144 * FP status register for identification. 145 */ 146 147 /* 148 * Ok if ARMFPE is defined and the boot options request the 149 * ARM FPE then it will be installed as the FPE. 150 * This is just while I work on integrating the new FPE. 151 * It means the new FPE gets installed if compiled int (ARMFPE 152 * defined) and also gives me a on/off option when I boot in 153 * case the new FPE is causing panics. 154 */ 155 156 157 if (boot_args) 158 get_bootconf_option(boot_args, "armfpe", 159 BOOTOPT_TYPE_BOOLEAN, &usearmfpe); 160 if (usearmfpe) 161 initialise_arm_fpe(); 162 #endif 163 164 #ifdef FPU_VFP 165 vfp_attach(); 166 #endif 167 } 168 169 enum cpu_class { 170 CPU_CLASS_NONE, 171 CPU_CLASS_ARM2, 172 CPU_CLASS_ARM2AS, 173 CPU_CLASS_ARM3, 174 CPU_CLASS_ARM6, 175 CPU_CLASS_ARM7, 176 CPU_CLASS_ARM7TDMI, 177 CPU_CLASS_ARM8, 178 CPU_CLASS_ARM9TDMI, 179 CPU_CLASS_ARM9ES, 180 CPU_CLASS_ARM9EJS, 181 CPU_CLASS_ARM10E, 182 CPU_CLASS_ARM10EJ, 183 CPU_CLASS_SA1, 184 CPU_CLASS_XSCALE, 185 CPU_CLASS_ARM11J, 186 CPU_CLASS_ARMV4, 187 CPU_CLASS_CORTEX, 188 }; 189 190 static const char * const generic_steppings[16] = { 191 "rev 0", "rev 1", "rev 2", "rev 3", 192 "rev 4", "rev 5", "rev 6", "rev 7", 193 "rev 8", "rev 9", "rev 10", "rev 11", 194 "rev 12", "rev 13", "rev 14", "rev 15", 195 }; 196 197 static const char * const pN_steppings[16] = { 198 "*p0", "*p1", "*p2", "*p3", "*p4", "*p5", "*p6", "*p7", 199 "*p8", "*p9", "*p10", "*p11", "*p12", "*p13", "*p14", "*p15", 200 }; 201 202 static const char * const sa110_steppings[16] = { 203 "rev 0", "step J", "step K", "step S", 204 "step T", "rev 5", "rev 6", "rev 7", 205 "rev 8", "rev 9", "rev 10", "rev 11", 206 "rev 12", "rev 13", "rev 14", "rev 15", 207 }; 208 209 static const char * const sa1100_steppings[16] = { 210 "rev 0", "step B", "step C", "rev 3", 211 "rev 4", "rev 5", "rev 6", "rev 7", 212 "step D", "step E", "rev 10" "step G", 213 "rev 12", "rev 13", "rev 14", "rev 15", 214 }; 215 216 static const char * const sa1110_steppings[16] = { 217 "step A-0", "rev 1", "rev 2", "rev 3", 218 "step B-0", "step B-1", "step B-2", "step B-3", 219 "step B-4", "step B-5", "rev 10", "rev 11", 220 "rev 12", "rev 13", "rev 14", "rev 15", 221 }; 222 223 static const char * const ixp12x0_steppings[16] = { 224 "(IXP1200 step A)", "(IXP1200 step B)", 225 "rev 2", "(IXP1200 step C)", 226 "(IXP1200 step D)", "(IXP1240/1250 step A)", 227 "(IXP1240 step B)", "(IXP1250 step B)", 228 "rev 8", "rev 9", "rev 10", "rev 11", 229 "rev 12", "rev 13", "rev 14", "rev 15", 230 }; 231 232 static const char * const xscale_steppings[16] = { 233 "step A-0", "step A-1", "step B-0", "step C-0", 234 "step D-0", "rev 5", "rev 6", "rev 7", 235 "rev 8", "rev 9", "rev 10", "rev 11", 236 "rev 12", "rev 13", "rev 14", "rev 15", 237 }; 238 239 static const char * const i80321_steppings[16] = { 240 "step A-0", "step B-0", "rev 2", "rev 3", 241 "rev 4", "rev 5", "rev 6", "rev 7", 242 "rev 8", "rev 9", "rev 10", "rev 11", 243 "rev 12", "rev 13", "rev 14", "rev 15", 244 }; 245 246 static const char * const i80219_steppings[16] = { 247 "step A-0", "rev 1", "rev 2", "rev 3", 248 "rev 4", "rev 5", "rev 6", "rev 7", 249 "rev 8", "rev 9", "rev 10", "rev 11", 250 "rev 12", "rev 13", "rev 14", "rev 15", 251 }; 252 253 /* Steppings for PXA2[15]0 */ 254 static const char * const pxa2x0_steppings[16] = { 255 "step A-0", "step A-1", "step B-0", "step B-1", 256 "step B-2", "step C-0", "rev 6", "rev 7", 257 "rev 8", "rev 9", "rev 10", "rev 11", 258 "rev 12", "rev 13", "rev 14", "rev 15", 259 }; 260 261 /* Steppings for PXA255/26x. 262 * rev 5: PXA26x B0, rev 6: PXA255 A0 263 */ 264 static const char * const pxa255_steppings[16] = { 265 "rev 0", "rev 1", "rev 2", "step A-0", 266 "rev 4", "step B-0", "step A-0", "rev 7", 267 "rev 8", "rev 9", "rev 10", "rev 11", 268 "rev 12", "rev 13", "rev 14", "rev 15", 269 }; 270 271 /* Stepping for PXA27x */ 272 static const char * const pxa27x_steppings[16] = { 273 "step A-0", "step A-1", "step B-0", "step B-1", 274 "step C-0", "rev 5", "rev 6", "rev 7", 275 "rev 8", "rev 9", "rev 10", "rev 11", 276 "rev 12", "rev 13", "rev 14", "rev 15", 277 }; 278 279 static const char * const ixp425_steppings[16] = { 280 "step 0", "rev 1", "rev 2", "rev 3", 281 "rev 4", "rev 5", "rev 6", "rev 7", 282 "rev 8", "rev 9", "rev 10", "rev 11", 283 "rev 12", "rev 13", "rev 14", "rev 15", 284 }; 285 286 struct cpuidtab { 287 u_int32_t cpuid; 288 enum cpu_class cpu_class; 289 const char *cpu_classname; 290 const char * const *cpu_steppings; 291 }; 292 293 const struct cpuidtab cpuids[] = { 294 { CPU_ID_ARM2, CPU_CLASS_ARM2, "ARM2", 295 generic_steppings }, 296 { CPU_ID_ARM250, CPU_CLASS_ARM2AS, "ARM250", 297 generic_steppings }, 298 299 { CPU_ID_ARM3, CPU_CLASS_ARM3, "ARM3", 300 generic_steppings }, 301 302 { CPU_ID_ARM600, CPU_CLASS_ARM6, "ARM600", 303 generic_steppings }, 304 { CPU_ID_ARM610, CPU_CLASS_ARM6, "ARM610", 305 generic_steppings }, 306 { CPU_ID_ARM620, CPU_CLASS_ARM6, "ARM620", 307 generic_steppings }, 308 309 { CPU_ID_ARM700, CPU_CLASS_ARM7, "ARM700", 310 generic_steppings }, 311 { CPU_ID_ARM710, CPU_CLASS_ARM7, "ARM710", 312 generic_steppings }, 313 { CPU_ID_ARM7500, CPU_CLASS_ARM7, "ARM7500", 314 generic_steppings }, 315 { CPU_ID_ARM710A, CPU_CLASS_ARM7, "ARM710a", 316 generic_steppings }, 317 { CPU_ID_ARM7500FE, CPU_CLASS_ARM7, "ARM7500FE", 318 generic_steppings }, 319 { CPU_ID_ARM710T, CPU_CLASS_ARM7TDMI, "ARM710T", 320 generic_steppings }, 321 { CPU_ID_ARM720T, CPU_CLASS_ARM7TDMI, "ARM720T", 322 generic_steppings }, 323 { CPU_ID_ARM740T8K, CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)", 324 generic_steppings }, 325 { CPU_ID_ARM740T4K, CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)", 326 generic_steppings }, 327 328 { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810", 329 generic_steppings }, 330 331 { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T", 332 generic_steppings }, 333 { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T", 334 generic_steppings }, 335 { CPU_ID_ARM926EJS, CPU_CLASS_ARM9EJS, "ARM926EJ-S", 336 generic_steppings }, 337 { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T", 338 generic_steppings }, 339 { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S", 340 generic_steppings }, 341 { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S", 342 generic_steppings }, 343 { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", 344 generic_steppings }, 345 { CPU_ID_TI925T, CPU_CLASS_ARM9TDMI, "TI ARM925T", 346 generic_steppings }, 347 { CPU_ID_MV88SV131, CPU_CLASS_ARM9ES, "Sheeva 88SV131", 348 generic_steppings }, 349 { CPU_ID_MV88FR571_VD, CPU_CLASS_ARM9ES, "Sheeva 88FR571-vd", 350 generic_steppings }, 351 352 { CPU_ID_ARM1020E, CPU_CLASS_ARM10E, "ARM1020E", 353 generic_steppings }, 354 { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022E-S", 355 generic_steppings }, 356 { CPU_ID_ARM1026EJS, CPU_CLASS_ARM10EJ, "ARM1026EJ-S", 357 generic_steppings }, 358 359 { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", 360 sa110_steppings }, 361 { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100", 362 sa1100_steppings }, 363 { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110", 364 sa1110_steppings }, 365 366 { CPU_ID_IXP1200, CPU_CLASS_SA1, "IXP1200", 367 ixp12x0_steppings }, 368 369 { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200", 370 xscale_steppings }, 371 372 { CPU_ID_80321_400, CPU_CLASS_XSCALE, "i80321 400MHz", 373 i80321_steppings }, 374 { CPU_ID_80321_600, CPU_CLASS_XSCALE, "i80321 600MHz", 375 i80321_steppings }, 376 { CPU_ID_80321_400_B0, CPU_CLASS_XSCALE, "i80321 400MHz", 377 i80321_steppings }, 378 { CPU_ID_80321_600_B0, CPU_CLASS_XSCALE, "i80321 600MHz", 379 i80321_steppings }, 380 381 { CPU_ID_80219_400, CPU_CLASS_XSCALE, "i80219 400MHz", 382 i80219_steppings }, 383 { CPU_ID_80219_600, CPU_CLASS_XSCALE, "i80219 600MHz", 384 i80219_steppings }, 385 386 { CPU_ID_PXA27X, CPU_CLASS_XSCALE, "PXA27x", 387 pxa27x_steppings }, 388 { CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250", 389 pxa2x0_steppings }, 390 { CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210", 391 pxa2x0_steppings }, 392 { CPU_ID_PXA250B, CPU_CLASS_XSCALE, "PXA250", 393 pxa2x0_steppings }, 394 { CPU_ID_PXA210B, CPU_CLASS_XSCALE, "PXA210", 395 pxa2x0_steppings }, 396 { CPU_ID_PXA250C, CPU_CLASS_XSCALE, "PXA255/26x", 397 pxa255_steppings }, 398 { CPU_ID_PXA210C, CPU_CLASS_XSCALE, "PXA210", 399 pxa2x0_steppings }, 400 401 { CPU_ID_IXP425_533, CPU_CLASS_XSCALE, "IXP425 533MHz", 402 ixp425_steppings }, 403 { CPU_ID_IXP425_400, CPU_CLASS_XSCALE, "IXP425 400MHz", 404 ixp425_steppings }, 405 { CPU_ID_IXP425_266, CPU_CLASS_XSCALE, "IXP425 266MHz", 406 ixp425_steppings }, 407 408 { CPU_ID_ARM1136JS, CPU_CLASS_ARM11J, "ARM1136J-S r0", 409 pN_steppings }, 410 { CPU_ID_ARM1136JSR1, CPU_CLASS_ARM11J, "ARM1136J-S r1", 411 pN_steppings }, 412 { CPU_ID_ARM1176JS, CPU_CLASS_ARM11J, "ARM1176J-S r0", 413 pN_steppings }, 414 415 { CPU_ID_ARM11MPCORE, CPU_CLASS_ARM11J, "ARM11 MPCore", 416 generic_steppings }, 417 418 { CPU_ID_CORTEXA8R1, CPU_CLASS_CORTEX, "Cortex-A8 r1", 419 pN_steppings }, 420 { CPU_ID_CORTEXA8R2, CPU_CLASS_CORTEX, "Cortex-A8 r2", 421 pN_steppings }, 422 { CPU_ID_CORTEXA8R3, CPU_CLASS_CORTEX, "Cortex-A8 r3", 423 pN_steppings }, 424 { CPU_ID_CORTEXA9R1, CPU_CLASS_CORTEX, "Cortex-A9 r1", 425 pN_steppings }, 426 { CPU_ID_CORTEXA8R3, CPU_CLASS_ARM11J, "Cortex-A8 r3", 427 pN_steppings }, 428 429 { CPU_ID_FA526, CPU_CLASS_ARMV4, "FA526", 430 generic_steppings }, 431 432 { 0, CPU_CLASS_NONE, NULL, NULL } 433 }; 434 435 struct cpu_classtab { 436 const char *class_name; 437 const char *class_option; 438 }; 439 440 const struct cpu_classtab cpu_classes[] = { 441 [CPU_CLASS_NONE] = { "unknown", NULL }, 442 [CPU_CLASS_ARM2] = { "ARM2", "CPU_ARM2" }, 443 [CPU_CLASS_ARM2AS] = { "ARM2as", "CPU_ARM250" }, 444 [CPU_CLASS_ARM3] = { "ARM3", "CPU_ARM3" }, 445 [CPU_CLASS_ARM6] = { "ARM6", "CPU_ARM6" }, 446 [CPU_CLASS_ARM7] = { "ARM7", "CPU_ARM7" }, 447 [CPU_CLASS_ARM7TDMI] = { "ARM7TDMI", "CPU_ARM7TDMI" }, 448 [CPU_CLASS_ARM8] = { "ARM8", "CPU_ARM8" }, 449 [CPU_CLASS_ARM9TDMI] = { "ARM9TDMI", NULL }, 450 [CPU_CLASS_ARM9ES] = { "ARM9E-S", "CPU_ARM9E" }, 451 [CPU_CLASS_ARM9EJS] = { "ARM9EJ-S", "CPU_ARM9E" }, 452 [CPU_CLASS_ARM10E] = { "ARM10E", "CPU_ARM10" }, 453 [CPU_CLASS_ARM10EJ] = { "ARM10EJ", "CPU_ARM10" }, 454 [CPU_CLASS_SA1] = { "SA-1", "CPU_SA110" }, 455 [CPU_CLASS_XSCALE] = { "XScale", "CPU_XSCALE_..." }, 456 [CPU_CLASS_ARM11J] = { "ARM11J", "CPU_ARM11" }, 457 [CPU_CLASS_ARMV4] = { "ARMv4", "CPU_ARMV4" }, 458 [CPU_CLASS_CORTEX] = { "Cortex", "CPU_CORTEX" }, 459 }; 460 461 /* 462 * Report the type of the specified arm processor. This uses the generic and 463 * arm specific information in the CPU structure to identify the processor. 464 * The remaining fields in the CPU structure are filled in appropriately. 465 */ 466 467 static const char * const wtnames[] = { 468 "write-through", 469 "write-back", 470 "write-back", 471 "**unknown 3**", 472 "**unknown 4**", 473 "write-back-locking", /* XXX XScale-specific? */ 474 "write-back-locking-A", 475 "write-back-locking-B", 476 "**unknown 8**", 477 "**unknown 9**", 478 "**unknown 10**", 479 "**unknown 11**", 480 "**unknown 12**", 481 "**unknown 13**", 482 "write-back-locking-C", 483 "**unknown 15**", 484 }; 485 486 void 487 identify_arm_cpu(struct device *dv, struct cpu_info *ci) 488 { 489 u_int cpuid; 490 enum cpu_class cpu_class = CPU_CLASS_NONE; 491 int i; 492 const char *steppingstr; 493 494 cpuid = ci->ci_arm_cpuid; 495 496 if (cpuid == 0) { 497 aprint_error("Processor failed probe - no CPU ID\n"); 498 return; 499 } 500 501 for (i = 0; cpuids[i].cpuid != 0; i++) 502 if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) { 503 cpu_class = cpuids[i].cpu_class; 504 steppingstr = cpuids[i].cpu_steppings[cpuid & 505 CPU_ID_REVISION_MASK], 506 sprintf(cpu_model, "%s%s%s (%s core)", 507 cpuids[i].cpu_classname, 508 steppingstr[0] == '*' ? "" : " ", 509 &steppingstr[steppingstr[0] == '*'], 510 cpu_classes[cpu_class].class_name); 511 break; 512 } 513 514 if (cpuids[i].cpuid == 0) 515 sprintf(cpu_model, "unknown CPU (ID = 0x%x)", cpuid); 516 517 aprint_naive(": %s\n", cpu_model); 518 aprint_normal(": %s\n", cpu_model); 519 520 aprint_normal("%s:", dv->dv_xname); 521 522 switch (cpu_class) { 523 case CPU_CLASS_ARM6: 524 case CPU_CLASS_ARM7: 525 case CPU_CLASS_ARM7TDMI: 526 case CPU_CLASS_ARM8: 527 if ((ci->ci_ctrl & CPU_CONTROL_IDC_ENABLE) == 0) 528 aprint_normal(" IDC disabled"); 529 else 530 aprint_normal(" IDC enabled"); 531 break; 532 case CPU_CLASS_ARM9TDMI: 533 case CPU_CLASS_ARM9ES: 534 case CPU_CLASS_ARM9EJS: 535 case CPU_CLASS_ARM10E: 536 case CPU_CLASS_ARM10EJ: 537 case CPU_CLASS_SA1: 538 case CPU_CLASS_XSCALE: 539 case CPU_CLASS_ARM11J: 540 case CPU_CLASS_ARMV4: 541 case CPU_CLASS_CORTEX: 542 if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0) 543 aprint_normal(" DC disabled"); 544 else 545 aprint_normal(" DC enabled"); 546 if ((ci->ci_ctrl & CPU_CONTROL_IC_ENABLE) == 0) 547 aprint_normal(" IC disabled"); 548 else 549 aprint_normal(" IC enabled"); 550 break; 551 default: 552 break; 553 } 554 if ((ci->ci_ctrl & CPU_CONTROL_WBUF_ENABLE) == 0) 555 aprint_normal(" WB disabled"); 556 else 557 aprint_normal(" WB enabled"); 558 559 if (ci->ci_ctrl & CPU_CONTROL_LABT_ENABLE) 560 aprint_normal(" LABT"); 561 else 562 aprint_normal(" EABT"); 563 564 if (ci->ci_ctrl & CPU_CONTROL_BPRD_ENABLE) 565 aprint_normal(" branch prediction enabled"); 566 567 aprint_normal("\n"); 568 569 /* Print cache info. */ 570 if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0) 571 goto skip_pcache; 572 573 if (arm_pcache_unified) { 574 aprint_normal("%s: %dKB/%dB %d-way %s unified cache\n", 575 dv->dv_xname, arm_pdcache_size / 1024, 576 arm_pdcache_line_size, arm_pdcache_ways, 577 wtnames[arm_pcache_type]); 578 } else { 579 aprint_normal("%s: %dKB/%dB %d-way Instruction cache\n", 580 dv->dv_xname, arm_picache_size / 1024, 581 arm_picache_line_size, arm_picache_ways); 582 aprint_normal("%s: %dKB/%dB %d-way %s Data cache\n", 583 dv->dv_xname, arm_pdcache_size / 1024, 584 arm_pdcache_line_size, arm_pdcache_ways, 585 wtnames[arm_pcache_type]); 586 } 587 588 skip_pcache: 589 590 switch (cpu_class) { 591 #ifdef CPU_ARM2 592 case CPU_CLASS_ARM2: 593 #endif 594 #ifdef CPU_ARM250 595 case CPU_CLASS_ARM2AS: 596 #endif 597 #ifdef CPU_ARM3 598 case CPU_CLASS_ARM3: 599 #endif 600 #ifdef CPU_ARM6 601 case CPU_CLASS_ARM6: 602 #endif 603 #ifdef CPU_ARM7 604 case CPU_CLASS_ARM7: 605 #endif 606 #ifdef CPU_ARM7TDMI 607 case CPU_CLASS_ARM7TDMI: 608 #endif 609 #ifdef CPU_ARM8 610 case CPU_CLASS_ARM8: 611 #endif 612 #ifdef CPU_ARM9 613 case CPU_CLASS_ARM9TDMI: 614 #endif 615 #if defined(CPU_ARM9E) || defined(CPU_SHEEVA) 616 case CPU_CLASS_ARM9ES: 617 case CPU_CLASS_ARM9EJS: 618 #endif 619 #ifdef CPU_ARM10 620 case CPU_CLASS_ARM10E: 621 case CPU_CLASS_ARM10EJ: 622 #endif 623 #if defined(CPU_SA110) || defined(CPU_SA1100) || \ 624 defined(CPU_SA1110) || defined(CPU_IXP12X0) 625 case CPU_CLASS_SA1: 626 #endif 627 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 628 defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) 629 case CPU_CLASS_XSCALE: 630 #endif 631 #if defined(CPU_ARM11) 632 case CPU_CLASS_ARM11J: 633 #endif 634 #if defined(CPU_CORTEX) 635 case CPU_CLASS_CORTEX: 636 #endif 637 #if defined(CPU_FA526) 638 case CPU_CLASS_ARMV4: 639 #endif 640 break; 641 default: 642 if (cpu_classes[cpu_class].class_option == NULL) 643 aprint_error("%s: %s does not fully support this CPU." 644 "\n", dv->dv_xname, ostype); 645 else { 646 aprint_error("%s: This kernel does not fully support " 647 "this CPU.\n", dv->dv_xname); 648 aprint_normal("%s: Recompile with \"options %s\" to " 649 "correct this.\n", dv->dv_xname, 650 cpu_classes[cpu_class].class_option); 651 } 652 break; 653 } 654 655 } 656 657 /* End of cpu.c */ 658