1 /* $NetBSD: cortex_pmc.c,v 1.8 2020/06/20 07:10:36 skrll Exp $ */ 2 3 /* Copyright (c) 2007 Microsoft 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Microsoft 17 * 18 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 32 /* 33 * support for ARM cortex Performance Monitor Counters 34 * based on arm11_pmc.c 35 */ 36 37 #include <sys/cdefs.h> 38 /* __KERNEL_RCSID(0, "$NetBSD: cortex_pmc.c,v 1.8 2020/06/20 07:10:36 skrll Exp $"); */ 39 40 #include <sys/param.h> 41 #include <sys/types.h> 42 43 #include <sys/kernel.h> 44 #include <sys/systm.h> 45 #include <sys/time.h> 46 #include <sys/timetc.h> 47 48 #include <dev/clock_subr.h> 49 50 #include <uvm/uvm_extern.h> 51 52 #include <arm/armreg.h> 53 #include <arm/cpufunc.h> 54 #include <arm/arm32/machdep.h> 55 56 #ifndef CORTEX_PMC_CCNT_HZ 57 # define CORTEX_PMC_CCNT_HZ 400000000 /* 400MHz */ 58 #endif 59 60 #define COUNTS_PER_USEC (curcpu()->ci_data.cpu_cc_freq / (1000*1000)) 61 62 static const uint32_t counts_per_wrap = ~0UL - 1; 63 64 /* 65 * enable the PMC CCNT for delay() 66 */ 67 void 68 cortex_pmc_ccnt_init(void) 69 { 70 if (curcpu()->ci_data.cpu_cc_freq == 0) { 71 curcpu()->ci_data.cpu_cc_freq = CORTEX_PMC_CCNT_HZ; 72 } 73 } 74 75 /* 76 * delay - for "at least" arg usec 77 * 78 * NOTE: at 400MHz we are restricted to (uint32_t)~0 "counts" 79 * if this is a problem, accumulate counts in LL vars 80 */ 81 void 82 delay(u_int arg) 83 { 84 uint32_t ctrl; 85 uint32_t cur; 86 uint32_t last; 87 uint32_t delta = 0; 88 uint32_t usecs = 0; 89 const uint32_t counts_per_usec = COUNTS_PER_USEC; 90 const uint32_t delay_arg_limit = ~0UL / counts_per_usec; /* about 10 sec */ 91 92 if (arg > delay_arg_limit) 93 panic("%s: arg %u overflow, limit is %u usec\n", 94 __func__, arg, delay_arg_limit); 95 96 last = armreg_pmccntr_read(); 97 delta = usecs = 0; 98 while (arg > usecs) { 99 cur = armreg_pmccntr_read(); 100 101 /* 102 * overflow flag is moved to a separate register 103 * and is not read from PMC Control Register 104 */ 105 ctrl = armreg_pmovsr_read(); 106 if (ctrl & CORTEX_CNTOFL_C) { 107 /* 108 * Reset overflow flag for cycle counter in overflow 109 * register 110 */ 111 armreg_pmovsr_write(CORTEX_CNTOFL_C); 112 delta += (cur + (counts_per_wrap - last)); 113 } else { 114 delta += (cur - last); 115 } 116 last = cur; 117 if (delta >= counts_per_usec) { 118 usecs += delta / counts_per_usec; 119 delta %= counts_per_usec; 120 } 121 } 122 } 123