1 /*- 2 * Copyright (c) 2013 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas of 3am Software Foundry. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include "opt_multiprocessor.h" 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(1, "$NetBSD: arm32_tlb.c,v 1.9 2015/03/26 08:45:05 hsuenaga Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/types.h> 37 38 #include <uvm/uvm.h> 39 40 #include <arm/locore.h> 41 42 bool arm_has_tlbiasid_p; // CPU supports TLBIASID system coprocessor op 43 44 tlb_asid_t 45 tlb_get_asid(void) 46 { 47 return armreg_contextidr_read() & 0xff; 48 } 49 50 void 51 tlb_set_asid(tlb_asid_t asid) 52 { 53 arm_dsb(); 54 if (asid == KERNEL_PID) { 55 armreg_ttbcr_write(armreg_ttbcr_read() | TTBCR_S_PD0); 56 arm_isb(); 57 } 58 armreg_contextidr_write(asid); 59 arm_isb(); 60 } 61 62 void 63 tlb_invalidate_all(void) 64 { 65 const bool vivt_icache_p = arm_pcache.icache_type == CACHE_TYPE_VIVT; 66 arm_dsb(); 67 #ifdef MULTIPROCESSOR 68 armreg_tlbiallis_write(0); 69 #else 70 armreg_tlbiall_write(0); 71 #endif 72 arm_isb(); 73 if (__predict_false(vivt_icache_p)) { 74 if (arm_has_tlbiasid_p) { 75 armreg_icialluis_write(0); 76 } else { 77 armreg_iciallu_write(0); 78 } 79 } 80 arm_isb(); 81 } 82 83 void 84 tlb_invalidate_globals(void) 85 { 86 tlb_invalidate_all(); 87 } 88 89 void 90 tlb_invalidate_asids(tlb_asid_t lo, tlb_asid_t hi) 91 { 92 const bool vivt_icache_p = arm_pcache.icache_type == CACHE_TYPE_VIVT; 93 arm_dsb(); 94 if (arm_has_tlbiasid_p) { 95 for (; lo <= hi; lo++) { 96 #ifdef MULTIPROCESSOR 97 armreg_tlbiasidis_write(lo); 98 #else 99 armreg_tlbiasid_write(lo); 100 #endif 101 } 102 arm_isb(); 103 if (__predict_false(vivt_icache_p)) { 104 #ifdef MULTIPROCESSOR 105 armreg_icialluis_write(0); 106 #else 107 armreg_iciallu_write(0); 108 #endif 109 } 110 } else { 111 armreg_tlbiall_write(0); 112 arm_isb(); 113 if (__predict_false(vivt_icache_p)) { 114 armreg_iciallu_write(0); 115 } 116 } 117 arm_isb(); 118 } 119 120 void 121 tlb_invalidate_addr(vaddr_t va, tlb_asid_t asid) 122 { 123 arm_dsb(); 124 va = trunc_page(va) | asid; 125 for (vaddr_t eva = va + PAGE_SIZE; va < eva; va += L2_S_SIZE) { 126 #ifdef MULTIPROCESSOR 127 armreg_tlbimvais_write(va); 128 #else 129 armreg_tlbimva_write(va); 130 #endif 131 //armreg_tlbiall_write(asid); 132 } 133 arm_dsb(); 134 arm_isb(); 135 } 136 137 bool 138 tlb_update_addr(vaddr_t va, tlb_asid_t asid, pt_entry_t pte, bool insert_p) 139 { 140 tlb_invalidate_addr(va, asid); 141 return true; 142 } 143 144 #if !defined(MULTIPROCESSOR) && defined(CPU_CORTEXA5) 145 static u_int 146 tlb_cortex_a5_record_asids(u_long *mapp) 147 { 148 u_int nasids = 0; 149 for (size_t va_index = 0; va_index < 63; va_index++) { 150 for (size_t way = 0; way < 2; way++) { 151 armreg_tlbdataop_write( 152 __SHIFTIN(way, ARM_TLBDATAOP_WAY) 153 | __SHIFTIN(va_index, ARM_A5_TLBDATAOP_INDEX)); 154 arm_isb(); 155 const uint64_t d = ((uint64_t) armreg_tlbdata1_read()) 156 | armreg_tlbdata0_read(); 157 if (!(d & ARM_TLBDATA_VALID) 158 || !(d & ARM_A5_TLBDATA_nG)) 159 continue; 160 161 const tlb_asid_t asid = __SHIFTOUT(d, 162 ARM_A5_TLBDATA_ASID); 163 const u_long mask = 1L << (asid & 31); 164 const size_t idx = asid >> 5; 165 if (mapp[idx] & mask) 166 continue; 167 168 mapp[idx] |= mask; 169 nasids++; 170 } 171 } 172 return nasids; 173 } 174 #endif 175 176 #if !defined(MULTIPROCESSOR) && defined(CPU_CORTEXA7) 177 static u_int 178 tlb_cortex_a7_record_asids(u_long *mapp) 179 { 180 u_int nasids = 0; 181 for (size_t va_index = 0; va_index < 128; va_index++) { 182 for (size_t way = 0; way < 2; way++) { 183 armreg_tlbdataop_write( 184 __SHIFTIN(way, ARM_TLBDATAOP_WAY) 185 | __SHIFTIN(va_index, ARM_A7_TLBDATAOP_INDEX)); 186 arm_isb(); 187 const uint32_t d0 = armreg_tlbdata0_read(); 188 const uint32_t d1 = armreg_tlbdata1_read(); 189 if (!(d0 & ARM_TLBDATA_VALID) 190 || !(d1 & ARM_A7_TLBDATA1_nG)) 191 continue; 192 193 const uint64_t d01 = ((uint64_t) d1)|d0; 194 const tlb_asid_t asid = __SHIFTOUT(d01, 195 ARM_A7_TLBDATA01_ASID); 196 const u_long mask = 1L << (asid & 31); 197 const size_t idx = asid >> 5; 198 if (mapp[idx] & mask) 199 continue; 200 201 mapp[idx] |= mask; 202 nasids++; 203 } 204 } 205 return nasids; 206 } 207 #endif 208 209 u_int 210 tlb_record_asids(u_long *mapp) 211 { 212 #ifndef MULTIPROCESSOR 213 #ifdef CPU_CORTEXA5 214 if (CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid)) 215 return tlb_cortex_a5_record_asids(mapp); 216 #endif 217 #ifdef CPU_CORTEXA7 218 if (CPU_ID_CORTEX_A7_P(curcpu()->ci_arm_cpuid)) 219 return tlb_cortex_a7_record_asids(mapp); 220 #endif 221 #endif /* MULTIPROCESSOR */ 222 #ifdef DIAGNOSTIC 223 mapp[0] = 0xfffffffe; 224 mapp[1] = 0xffffffff; 225 mapp[2] = 0xffffffff; 226 mapp[3] = 0xffffffff; 227 mapp[4] = 0xffffffff; 228 mapp[5] = 0xffffffff; 229 mapp[6] = 0xffffffff; 230 mapp[7] = 0xffffffff; 231 #endif 232 return 255; 233 } 234 235 void 236 tlb_walk(void *ctx, bool (*func)(void *, vaddr_t, tlb_asid_t, pt_entry_t)) 237 { 238 /* no way to view the TLB */ 239 } 240