xref: /netbsd-src/sys/arch/arm/arm/undefined.c (revision f89f6560d453f5e37386cc7938c072d2f528b9fa) 
1 /*	$NetBSD: undefined.c,v 1.56 2015/04/15 13:22:50 matt Exp $	*/
2 
3 /*
4  * Copyright (c) 2001 Ben Harris.
5  * Copyright (c) 1995 Mark Brinicombe.
6  * Copyright (c) 1995 Brini.
7  * All rights reserved.
8  *
9  * This code is derived from software written for Brini by Mark Brinicombe
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the distribution.
19  * 3. All advertising materials mentioning features or use of this software
20  *    must display the following acknowledgement:
21  *	This product includes software developed by Brini.
22  * 4. The name of the company nor the name of the author may be used to
23  *    endorse or promote products derived from this software without specific
24  *    prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
27  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
28  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
29  * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
30  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36  * SUCH DAMAGE.
37  *
38  * RiscBSD kernel project
39  *
40  * undefined.c
41  *
42  * Fault handler
43  *
44  * Created      : 06/01/95
45  */
46 
47 #define FAST_FPE
48 
49 #include "opt_ddb.h"
50 #include "opt_kgdb.h"
51 #include "opt_dtrace.h"
52 
53 #include <sys/param.h>
54 #ifdef KGDB
55 #include <sys/kgdb.h>
56 #endif
57 
58 __KERNEL_RCSID(0, "$NetBSD: undefined.c,v 1.56 2015/04/15 13:22:50 matt Exp $");
59 
60 #include <sys/kmem.h>
61 #include <sys/queue.h>
62 #include <sys/signal.h>
63 #include <sys/systm.h>
64 #include <sys/proc.h>
65 #include <sys/syslog.h>
66 #include <sys/vmmeter.h>
67 #include <sys/cpu.h>
68 #ifdef FAST_FPE
69 #include <sys/acct.h>
70 #endif
71 #include <sys/userret.h>
72 
73 #include <uvm/uvm_extern.h>
74 
75 #include <arm/locore.h>
76 #include <arm/undefined.h>
77 
78 #include <machine/pcb.h>
79 #include <machine/trap.h>
80 
81 #include <arch/arm/arm/disassem.h>
82 
83 #ifdef DDB
84 #include <ddb/db_output.h>
85 #include <machine/db_machdep.h>
86 #endif
87 
88 #ifdef acorn26
89 #include <machine/machdep.h>
90 #endif
91 
92 static int gdb_trapper(u_int, u_int, struct trapframe *, int);
93 
94 LIST_HEAD(, undefined_handler) undefined_handlers[NUM_UNKNOWN_HANDLERS];
95 
96 
97 void *
98 install_coproc_handler(int coproc, undef_handler_t handler)
99 {
100 	struct undefined_handler *uh;
101 
102 	KASSERT(coproc >= 0 && coproc < NUM_UNKNOWN_HANDLERS);
103 	KASSERT(handler != NULL); /* Used to be legal. */
104 
105 	uh = kmem_alloc(sizeof(*uh), KM_NOSLEEP);
106 	KASSERT(uh != NULL);
107 	uh->uh_handler = handler;
108 	install_coproc_handler_static(coproc, uh);
109 	return uh;
110 }
111 
112 void
113 install_coproc_handler_static(int coproc, struct undefined_handler *uh)
114 {
115 
116 	LIST_INSERT_HEAD(&undefined_handlers[coproc], uh, uh_link);
117 }
118 
119 void
120 remove_coproc_handler(void *cookie)
121 {
122 	struct undefined_handler *uh = cookie;
123 
124 	LIST_REMOVE(uh, uh_link);
125 	kmem_free(uh, sizeof(*uh));
126 }
127 
128 static int
129 cp15_trapper(u_int addr, u_int insn, struct trapframe *tf, int code)
130 {
131 	struct lwp * const l = curlwp;
132 
133 #if defined(THUMB_CODE) && !defined(CPU_ARMV7)
134 	if (tf->tf_spsr & PSR_T_bit)
135 		return 1;
136 #endif
137 	if (code != FAULT_USER)
138 		return 1;
139 
140 	/*
141 	 * Don't overwrite sp, pc, etc.
142 	 */
143 	const u_int regno = (insn >> 12) & 15;
144 	if (regno > 12)
145 		return 1;
146 
147 	/*
148 	 * Get a pointer to the register used in the instruction to be emulated.
149 	 */
150 	register_t * const regp = &tf->tf_r0 + regno;
151 
152 	/*
153 	 * Handle MRC p15, 0, <Rd>, c13, c0, 3 (Read User read-only thread id)
154 	 */
155 	if ((insn & 0xffff0fff) == 0xee1d0f70) {
156 		*regp = (uintptr_t)l->l_private;
157 		tf->tf_pc += INSN_SIZE;
158 		curcpu()->ci_und_cp15_ev.ev_count++;
159 		return 0;
160 	}
161 
162 	/*
163 	 * Handle {MRC,MCR} p15, 0, <Rd>, c13, c0, 2 (User read/write thread id)
164 	 */
165 	if ((insn & 0xffef0fff) == 0xee0d0f50) {
166 		struct pcb * const pcb = lwp_getpcb(l);
167 		if (insn & 0x00100000)
168 			*regp = pcb->pcb_user_pid_rw;
169 		else
170 			pcb->pcb_user_pid_rw = *regp;
171 		tf->tf_pc += INSN_SIZE;
172 		curcpu()->ci_und_cp15_ev.ev_count++;
173 		return 0;
174 	}
175 
176 	return 1;
177 }
178 
179 static int
180 gdb_trapper(u_int addr, u_int insn, struct trapframe *tf, int code)
181 {
182 	struct lwp * const l = curlwp;
183 
184 #ifdef THUMB_CODE
185 	if (tf->tf_spsr & PSR_T_bit) {
186 		if (insn == GDB_THUMB_BREAKPOINT)
187 			goto bkpt;
188 	}
189 	else
190 #endif
191 	{
192 		if (insn == GDB_BREAKPOINT || insn == GDB5_BREAKPOINT) {
193 #ifdef THUMB_CODE
194 		bkpt:
195 #endif
196 			if (code == FAULT_USER) {
197 				ksiginfo_t ksi;
198 
199 				KSI_INIT_TRAP(&ksi);
200 				ksi.ksi_signo = SIGTRAP;
201 				ksi.ksi_code = TRAP_BRKPT;
202 				ksi.ksi_addr = (uint32_t *)addr;
203 				ksi.ksi_trap = 0;
204 				trapsignal(l, &ksi);
205 				return 0;
206 			}
207 #ifdef KGDB
208 			return !kgdb_trap(T_BREAKPOINT, tf);
209 #endif
210 		}
211 	}
212 	return 1;
213 }
214 
215 static struct undefined_handler cp15_uh;
216 static struct undefined_handler gdb_uh;
217 #ifdef THUMB_CODE
218 static struct undefined_handler gdb_uh_thumb;
219 #endif
220 
221 #ifdef KDTRACE_HOOKS
222 #include <sys/dtrace_bsd.h>
223 
224 /* Not used for now, but needed for dtrace/fbt modules */
225 dtrace_doubletrap_func_t	dtrace_doubletrap_func = NULL;
226 dtrace_trap_func_t		dtrace_trap_func = NULL;
227 
228 int (* dtrace_invop_jump_addr)(uintptr_t, uintptr_t *, uintptr_t);
229 void (* dtrace_emulation_jump_addr)(int, struct trapframe *);
230 
231 static int
232 dtrace_trapper(u_int addr, struct trapframe *frame)
233 {
234 	int op;
235 	struct trapframe back;
236 	u_int insn = read_insn(addr, false);
237 
238 	if (dtrace_invop_jump_addr == NULL || dtrace_emulation_jump_addr == NULL)
239 		return 1;
240 
241 	if (!DTRACE_IS_BREAKPOINT(insn))
242 		return 1;
243 
244 	/* cond value is encoded in the first byte */
245 	if (!arm_cond_ok_p(__SHIFTIN(insn, INSN_COND_MASK), frame->tf_spsr)) {
246 		frame->tf_pc += INSN_SIZE;
247 		return 0;
248 	}
249 
250 	back = *frame;
251 	op = dtrace_invop_jump_addr(addr, (uintptr_t *) frame->tf_svc_sp, frame->tf_r0);
252 	*frame = back;
253 
254 	dtrace_emulation_jump_addr(op, frame);
255 
256 	return 0;
257 }
258 #endif
259 
260 void
261 undefined_init(void)
262 {
263 	int loop;
264 
265 	/* Not actually necessary -- the initialiser is just NULL */
266 	for (loop = 0; loop < NUM_UNKNOWN_HANDLERS; ++loop)
267 		LIST_INIT(&undefined_handlers[loop]);
268 
269 	/* Install handler for CP15 emulation */
270 	cp15_uh.uh_handler = cp15_trapper;
271 	install_coproc_handler_static(SYSTEM_COPROC, &cp15_uh);
272 
273 	/* Install handler for GDB breakpoints */
274 	gdb_uh.uh_handler = gdb_trapper;
275 	install_coproc_handler_static(CORE_UNKNOWN_HANDLER, &gdb_uh);
276 #ifdef THUMB_CODE
277 	gdb_uh_thumb.uh_handler = gdb_trapper;
278 	install_coproc_handler_static(THUMB_UNKNOWN_HANDLER, &gdb_uh_thumb);
279 #endif
280 }
281 
282 void
283 undefinedinstruction(trapframe_t *tf)
284 {
285 	struct lwp *l;
286 	vaddr_t fault_pc;
287 	int fault_instruction;
288 	int fault_code;
289 	int coprocessor;
290 	int user;
291 	struct undefined_handler *uh;
292 #ifdef VERBOSE_ARM32
293 	int s;
294 #endif
295 
296 	curcpu()->ci_und_ev.ev_count++;
297 
298 #ifdef KDTRACE_HOOKS
299 	if ((tf->tf_spsr & PSR_MODE) != PSR_USR32_MODE) {
300 		tf->tf_pc -= INSN_SIZE;
301 		if (dtrace_trapper(tf->tf_pc, tf) == 0)
302 			return;
303 		tf->tf_pc += INSN_SIZE; /* Reset for the rest code */
304 	}
305 #endif
306 
307 	/* Enable interrupts if they were enabled before the exception. */
308 #ifdef acorn26
309 	if ((tf->tf_r15 & R15_IRQ_DISABLE) == 0)
310 		int_on();
311 #else
312 	restore_interrupts(tf->tf_spsr & IF32_bits);
313 #endif
314 
315 #ifndef acorn26
316 #ifdef THUMB_CODE
317 	if (tf->tf_spsr & PSR_T_bit)
318 		tf->tf_pc -= THUMB_INSN_SIZE;
319 	else
320 #endif
321 	{
322 		tf->tf_pc -= INSN_SIZE;
323 	}
324 #endif
325 
326 #ifdef __PROG26
327 	fault_pc = tf->tf_r15 & R15_PC;
328 #else
329 	fault_pc = tf->tf_pc;
330 #endif
331 
332 	/* Get the current lwp/proc structure or lwp0/proc0 if there is none. */
333 	l = curlwp;
334 
335 #ifdef __PROG26
336 	if ((tf->tf_r15 & R15_MODE) == R15_MODE_USR) {
337 #else
338 	if ((tf->tf_spsr & PSR_MODE) == PSR_USR32_MODE) {
339 #endif
340 		user = 1;
341 		LWP_CACHE_CREDS(l, l->l_proc);
342 	} else
343 		user = 0;
344 
345 
346 #ifdef THUMB_CODE
347 	if (tf->tf_spsr & PSR_T_bit) {
348 		fault_instruction = read_thumb_insn(fault_pc, user);
349 		if (fault_instruction >= 0xe000) {
350 			fault_instruction = (fault_instruction << 16)
351 			    | read_thumb_insn(fault_pc + 2, user);
352 		}
353 	}
354 	else
355 #endif
356 	{
357 		/*
358 		 * Make sure the program counter is correctly aligned so we
359 		 * don't take an alignment fault trying to read the opcode.
360 		 */
361 		if (__predict_false((fault_pc & 3) != 0)) {
362 			ksiginfo_t ksi;
363 			/* Give the user an illegal instruction signal. */
364 			KSI_INIT_TRAP(&ksi);
365 			ksi.ksi_signo = SIGILL;
366 			ksi.ksi_code = ILL_ILLOPC;
367 			ksi.ksi_addr = (uint32_t *)(intptr_t) fault_pc;
368 			trapsignal(l, &ksi);
369 			userret(l);
370 			return;
371 		}
372 	 	/*
373 		 * Should use fuword() here .. but in the interests of
374 		 * squeezing every  bit of speed we will just use
375 		 * ReadWord(). We know the instruction can be read
376 		 * as was just executed so this will never fail unless
377 		 * the kernel is screwed up in which case it does
378 		 * not really matter does it ?
379 		 */
380 		fault_instruction = read_insn(fault_pc, user);
381 	}
382 
383 	/* Update vmmeter statistics */
384 	curcpu()->ci_data.cpu_ntrap++;
385 
386 #ifdef THUMB_CODE
387 	if ((tf->tf_spsr & PSR_T_bit) && !CPU_IS_ARMV7_P()) {
388 		coprocessor = THUMB_UNKNOWN_HANDLER;
389 	}
390 	else
391 #endif
392 	{
393 		/* Check for coprocessor instruction */
394 
395 		/*
396 		 * According to the datasheets you only need to look at
397 		 * bit 27 of the instruction to tell the difference
398 		 * between and undefined instruction and a coprocessor
399 		 * instruction following an undefined instruction trap.
400 		 *
401 		 * ARMv5 adds undefined instructions in the NV space,
402 		 * even when bit 27 is set.
403 		 */
404 
405 		if ((fault_instruction & (1 << 27)) != 0
406 		    && (fault_instruction & 0xf0000000) != 0xf0000000) {
407 			coprocessor = (fault_instruction >> 8) & 0x0f;
408 #ifdef THUMB_CODE
409 		} else if ((tf->tf_spsr & PSR_T_bit) && !CPU_IS_ARMV7_P()) {
410 			coprocessor = THUMB_UNKNOWN_HANDLER;
411 #endif
412 		} else {
413 			coprocessor = CORE_UNKNOWN_HANDLER;
414 		}
415 	}
416 
417 	if (user) {
418 		/*
419 		 * Modify the fault_code to reflect the USR/SVC state at
420 		 * time of fault.
421 		 */
422 		fault_code = FAULT_USER;
423 		lwp_settrapframe(l, tf);
424 	} else
425 		fault_code = 0;
426 
427 	/* OK this is were we do something about the instruction. */
428 	LIST_FOREACH(uh, &undefined_handlers[coprocessor], uh_link)
429 	    if (uh->uh_handler(fault_pc, fault_instruction, tf,
430 			       fault_code) == 0)
431 		    break;
432 
433 	if (uh == NULL) {
434 		/* Fault has not been handled */
435 		ksiginfo_t ksi;
436 
437 #ifdef VERBOSE_ARM32
438 		s = spltty();
439 
440 		if ((fault_instruction & 0x0f000010) == 0x0e000000) {
441 			printf("CDP\n");
442 			disassemble(fault_pc);
443 		} else if ((fault_instruction & 0x0e000000) == 0x0c000000) {
444 			printf("LDC/STC\n");
445 			disassemble(fault_pc);
446 		} else if ((fault_instruction & 0x0f000010) == 0x0e000010) {
447 			printf("MRC/MCR\n");
448 			disassemble(fault_pc);
449 		} else if ((fault_instruction & ~INSN_COND_MASK)
450 			 != (KERNEL_BREAKPOINT & ~INSN_COND_MASK)) {
451 			printf("Undefined instruction\n");
452 			disassemble(fault_pc);
453 		}
454 
455 		splx(s);
456 #endif
457 
458 		if ((fault_code & FAULT_USER) == 0) {
459 #ifdef DDB
460 			db_printf("Undefined instruction %#x in kernel at %#lx (LR %#x SP %#x)\n",
461 			    fault_instruction, fault_pc, tf->tf_svc_lr, tf->tf_svc_sp);
462 			kdb_trap(T_FAULT, tf);
463 #else
464 			panic("undefined instruction %#x in kernel at %#lx", fault_instruction, fault_pc);
465 #endif
466 		}
467 		KSI_INIT_TRAP(&ksi);
468 		ksi.ksi_signo = SIGILL;
469 		ksi.ksi_code = ILL_ILLOPC;
470 		ksi.ksi_addr = (uint32_t *)fault_pc;
471 		ksi.ksi_trap = fault_instruction;
472 		trapsignal(l, &ksi);
473 	}
474 
475 	if ((fault_code & FAULT_USER) == 0)
476 		return;
477 
478 	userret(l);
479 }
480