xref: /netbsd-src/sys/arch/arm/arm/undefined.c (revision 6cf6fe02a981b55727c49c3d37b0d8191a98c0ee) 
1 /*	$NetBSD: undefined.c,v 1.54 2014/03/28 21:44:35 matt Exp $	*/
2 
3 /*
4  * Copyright (c) 2001 Ben Harris.
5  * Copyright (c) 1995 Mark Brinicombe.
6  * Copyright (c) 1995 Brini.
7  * All rights reserved.
8  *
9  * This code is derived from software written for Brini by Mark Brinicombe
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the distribution.
19  * 3. All advertising materials mentioning features or use of this software
20  *    must display the following acknowledgement:
21  *	This product includes software developed by Brini.
22  * 4. The name of the company nor the name of the author may be used to
23  *    endorse or promote products derived from this software without specific
24  *    prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
27  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
28  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
29  * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
30  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36  * SUCH DAMAGE.
37  *
38  * RiscBSD kernel project
39  *
40  * undefined.c
41  *
42  * Fault handler
43  *
44  * Created      : 06/01/95
45  */
46 
47 #define FAST_FPE
48 
49 #include "opt_ddb.h"
50 #include "opt_kgdb.h"
51 #include "opt_dtrace.h"
52 
53 #include <sys/param.h>
54 #ifdef KGDB
55 #include <sys/kgdb.h>
56 #endif
57 
58 __KERNEL_RCSID(0, "$NetBSD: undefined.c,v 1.54 2014/03/28 21:44:35 matt Exp $");
59 
60 #include <sys/kmem.h>
61 #include <sys/queue.h>
62 #include <sys/signal.h>
63 #include <sys/systm.h>
64 #include <sys/proc.h>
65 #include <sys/syslog.h>
66 #include <sys/vmmeter.h>
67 #include <sys/cpu.h>
68 #ifdef FAST_FPE
69 #include <sys/acct.h>
70 #endif
71 #include <sys/userret.h>
72 
73 #include <uvm/uvm_extern.h>
74 
75 #include <arm/locore.h>
76 #include <arm/undefined.h>
77 
78 #include <machine/pcb.h>
79 #include <machine/trap.h>
80 
81 #include <arch/arm/arm/disassem.h>
82 
83 #ifdef DDB
84 #include <ddb/db_output.h>
85 #include <machine/db_machdep.h>
86 #endif
87 
88 #ifdef acorn26
89 #include <machine/machdep.h>
90 #endif
91 
92 static int gdb_trapper(u_int, u_int, struct trapframe *, int);
93 
94 LIST_HEAD(, undefined_handler) undefined_handlers[NUM_UNKNOWN_HANDLERS];
95 
96 
97 void *
98 install_coproc_handler(int coproc, undef_handler_t handler)
99 {
100 	struct undefined_handler *uh;
101 
102 	KASSERT(coproc >= 0 && coproc < NUM_UNKNOWN_HANDLERS);
103 	KASSERT(handler != NULL); /* Used to be legal. */
104 
105 	uh = kmem_alloc(sizeof(*uh), KM_SLEEP);
106 	uh->uh_handler = handler;
107 	install_coproc_handler_static(coproc, uh);
108 	return uh;
109 }
110 
111 void
112 install_coproc_handler_static(int coproc, struct undefined_handler *uh)
113 {
114 
115 	LIST_INSERT_HEAD(&undefined_handlers[coproc], uh, uh_link);
116 }
117 
118 void
119 remove_coproc_handler(void *cookie)
120 {
121 	struct undefined_handler *uh = cookie;
122 
123 	LIST_REMOVE(uh, uh_link);
124 	kmem_free(uh, sizeof(*uh));
125 }
126 
127 static int
128 cp15_trapper(u_int addr, u_int insn, struct trapframe *tf, int code)
129 {
130 	struct lwp * const l = curlwp;
131 
132 #if defined(THUMB_CODE) && !defined(CPU_ARMV7)
133 	if (tf->tf_spsr & PSR_T_bit)
134 		return 1;
135 #endif
136 	if (code != FAULT_USER)
137 		return 1;
138 
139 	/*
140 	 * Don't overwrite sp, pc, etc.
141 	 */
142 	const u_int regno = (insn >> 12) & 15;
143 	if (regno > 12)
144 		return 1;
145 
146 	/*
147 	 * Get a pointer to the register used in the instruction to be emulated.
148 	 */
149 	register_t * const regp = &tf->tf_r0 + regno;
150 
151 	/*
152 	 * Handle MRC p15, 0, <Rd>, c13, c0, 3 (Read User read-only thread id)
153 	 */
154 	if ((insn & 0xffff0fff) == 0xee1d0f70) {
155 		*regp = (uintptr_t)l->l_private;
156 		tf->tf_pc += INSN_SIZE;
157 		curcpu()->ci_und_cp15_ev.ev_count++;
158 		return 0;
159 	}
160 
161 	/*
162 	 * Handle {MRC,MCR} p15, 0, <Rd>, c13, c0, 2 (User read/write thread id)
163 	 */
164 	if ((insn & 0xffef0fff) == 0xee0d0f50) {
165 		struct pcb * const pcb = lwp_getpcb(l);
166 		if (insn & 0x00100000)
167 			*regp = pcb->pcb_user_pid_rw;
168 		else
169 			pcb->pcb_user_pid_rw = *regp;
170 		tf->tf_pc += INSN_SIZE;
171 		curcpu()->ci_und_cp15_ev.ev_count++;
172 		return 0;
173 	}
174 
175 	return 1;
176 }
177 
178 static int
179 gdb_trapper(u_int addr, u_int insn, struct trapframe *tf, int code)
180 {
181 	struct lwp * const l = curlwp;
182 
183 #ifdef THUMB_CODE
184 	if (tf->tf_spsr & PSR_T_bit) {
185 		if (insn == GDB_THUMB_BREAKPOINT)
186 			goto bkpt;
187 	}
188 	else
189 #endif
190 	{
191 		if (insn == GDB_BREAKPOINT || insn == GDB5_BREAKPOINT) {
192 #ifdef THUMB_CODE
193 		bkpt:
194 #endif
195 			if (code == FAULT_USER) {
196 				ksiginfo_t ksi;
197 
198 				KSI_INIT_TRAP(&ksi);
199 				ksi.ksi_signo = SIGTRAP;
200 				ksi.ksi_code = TRAP_BRKPT;
201 				ksi.ksi_addr = (uint32_t *)addr;
202 				ksi.ksi_trap = 0;
203 				trapsignal(l, &ksi);
204 				return 0;
205 			}
206 #ifdef KGDB
207 			return !kgdb_trap(T_BREAKPOINT, tf);
208 #endif
209 		}
210 	}
211 	return 1;
212 }
213 
214 static struct undefined_handler cp15_uh;
215 static struct undefined_handler gdb_uh;
216 #ifdef THUMB_CODE
217 static struct undefined_handler gdb_uh_thumb;
218 #endif
219 
220 #ifdef KDTRACE_HOOKS
221 #include <sys/dtrace_bsd.h>
222 
223 /* Not used for now, but needed for dtrace/fbt modules */
224 dtrace_doubletrap_func_t	dtrace_doubletrap_func = NULL;
225 dtrace_trap_func_t		dtrace_trap_func = NULL;
226 
227 int (* dtrace_invop_jump_addr)(uintptr_t, uintptr_t *, uintptr_t);
228 void (* dtrace_emulation_jump_addr)(int, struct trapframe *);
229 
230 static int
231 dtrace_trapper(u_int addr, struct trapframe *frame)
232 {
233 	int op;
234 	struct trapframe back;
235 	u_int insn = read_insn(addr, false);
236 
237 	if (dtrace_invop_jump_addr == NULL || dtrace_emulation_jump_addr == NULL)
238 		return 1;
239 
240 	if (!DTRACE_IS_BREAKPOINT(insn))
241 		return 1;
242 
243 	/* cond value is encoded in the first byte */
244 	if (!arm_cond_ok_p(__SHIFTIN(insn, INSN_COND_MASK), frame->tf_spsr)) {
245 		frame->tf_pc += INSN_SIZE;
246 		return 0;
247 	}
248 
249 	back = *frame;
250 	op = dtrace_invop_jump_addr(addr, (uintptr_t *) frame->tf_svc_sp, frame->tf_r0);
251 	*frame = back;
252 
253 	dtrace_emulation_jump_addr(op, frame);
254 
255 	return 0;
256 }
257 #endif
258 
259 void
260 undefined_init(void)
261 {
262 	int loop;
263 
264 	/* Not actually necessary -- the initialiser is just NULL */
265 	for (loop = 0; loop < NUM_UNKNOWN_HANDLERS; ++loop)
266 		LIST_INIT(&undefined_handlers[loop]);
267 
268 	/* Install handler for CP15 emulation */
269 	cp15_uh.uh_handler = cp15_trapper;
270 	install_coproc_handler_static(SYSTEM_COPROC, &cp15_uh);
271 
272 	/* Install handler for GDB breakpoints */
273 	gdb_uh.uh_handler = gdb_trapper;
274 	install_coproc_handler_static(CORE_UNKNOWN_HANDLER, &gdb_uh);
275 #ifdef THUMB_CODE
276 	gdb_uh_thumb.uh_handler = gdb_trapper;
277 	install_coproc_handler_static(THUMB_UNKNOWN_HANDLER, &gdb_uh_thumb);
278 #endif
279 }
280 
281 void
282 undefinedinstruction(trapframe_t *tf)
283 {
284 	struct lwp *l;
285 	vaddr_t fault_pc;
286 	int fault_instruction;
287 	int fault_code;
288 	int coprocessor;
289 	int user;
290 	struct undefined_handler *uh;
291 #ifdef VERBOSE_ARM32
292 	int s;
293 #endif
294 
295 	curcpu()->ci_und_ev.ev_count++;
296 
297 #ifdef KDTRACE_HOOKS
298 	if ((tf->tf_spsr & PSR_MODE) != PSR_USR32_MODE) {
299 		tf->tf_pc -= INSN_SIZE;
300 		if (dtrace_trapper(tf->tf_pc, tf) == 0)
301 			return;
302 		tf->tf_pc += INSN_SIZE; /* Reset for the rest code */
303 	}
304 #endif
305 
306 	/* Enable interrupts if they were enabled before the exception. */
307 #ifdef acorn26
308 	if ((tf->tf_r15 & R15_IRQ_DISABLE) == 0)
309 		int_on();
310 #else
311 	restore_interrupts(tf->tf_spsr & IF32_bits);
312 #endif
313 
314 #ifndef acorn26
315 #ifdef THUMB_CODE
316 	if (tf->tf_spsr & PSR_T_bit)
317 		tf->tf_pc -= THUMB_INSN_SIZE;
318 	else
319 #endif
320 	{
321 		tf->tf_pc -= INSN_SIZE;
322 	}
323 #endif
324 
325 #ifdef __PROG26
326 	fault_pc = tf->tf_r15 & R15_PC;
327 #else
328 	fault_pc = tf->tf_pc;
329 #endif
330 
331 	/* Get the current lwp/proc structure or lwp0/proc0 if there is none. */
332 	l = curlwp;
333 
334 #ifdef __PROG26
335 	if ((tf->tf_r15 & R15_MODE) == R15_MODE_USR) {
336 #else
337 	if ((tf->tf_spsr & PSR_MODE) == PSR_USR32_MODE) {
338 #endif
339 		user = 1;
340 		LWP_CACHE_CREDS(l, l->l_proc);
341 	} else
342 		user = 0;
343 
344 
345 #ifdef THUMB_CODE
346 	if (tf->tf_spsr & PSR_T_bit) {
347 		fault_instruction = read_thumb_insn(fault_pc, user);
348 		if (fault_instruction >= 0xe000) {
349 			fault_instruction = (fault_instruction << 16)
350 			    | read_thumb_insn(fault_pc + 2, user);
351 		}
352 	}
353 	else
354 #endif
355 	{
356 		/*
357 		 * Make sure the program counter is correctly aligned so we
358 		 * don't take an alignment fault trying to read the opcode.
359 		 */
360 		if (__predict_false((fault_pc & 3) != 0)) {
361 			ksiginfo_t ksi;
362 			/* Give the user an illegal instruction signal. */
363 			KSI_INIT_TRAP(&ksi);
364 			ksi.ksi_signo = SIGILL;
365 			ksi.ksi_code = ILL_ILLOPC;
366 			ksi.ksi_addr = (uint32_t *)(intptr_t) fault_pc;
367 			trapsignal(l, &ksi);
368 			userret(l);
369 			return;
370 		}
371 	 	/*
372 		 * Should use fuword() here .. but in the interests of
373 		 * squeezing every  bit of speed we will just use
374 		 * ReadWord(). We know the instruction can be read
375 		 * as was just executed so this will never fail unless
376 		 * the kernel is screwed up in which case it does
377 		 * not really matter does it ?
378 		 */
379 		fault_instruction = read_insn(fault_pc, user);
380 	}
381 
382 	/* Update vmmeter statistics */
383 	curcpu()->ci_data.cpu_ntrap++;
384 
385 #ifdef THUMB_CODE
386 	if ((tf->tf_spsr & PSR_T_bit) && !CPU_IS_ARMV7_P()) {
387 		coprocessor = THUMB_UNKNOWN_HANDLER;
388 	}
389 	else
390 #endif
391 	{
392 		/* Check for coprocessor instruction */
393 
394 		/*
395 		 * According to the datasheets you only need to look at
396 		 * bit 27 of the instruction to tell the difference
397 		 * between and undefined instruction and a coprocessor
398 		 * instruction following an undefined instruction trap.
399 		 *
400 		 * ARMv5 adds undefined instructions in the NV space,
401 		 * even when bit 27 is set.
402 		 */
403 
404 		if ((fault_instruction & (1 << 27)) != 0
405 		    && (fault_instruction & 0xf0000000) != 0xf0000000) {
406 			coprocessor = (fault_instruction >> 8) & 0x0f;
407 #ifdef THUMB_CODE
408 		} else if ((tf->tf_spsr & PSR_T_bit) && !CPU_IS_ARMV7_P()) {
409 			coprocessor = THUMB_UNKNOWN_HANDLER;
410 #endif
411 		} else {
412 			coprocessor = CORE_UNKNOWN_HANDLER;
413 		}
414 	}
415 
416 	if (user) {
417 		/*
418 		 * Modify the fault_code to reflect the USR/SVC state at
419 		 * time of fault.
420 		 */
421 		fault_code = FAULT_USER;
422 		lwp_settrapframe(l, tf);
423 	} else
424 		fault_code = 0;
425 
426 	/* OK this is were we do something about the instruction. */
427 	LIST_FOREACH(uh, &undefined_handlers[coprocessor], uh_link)
428 	    if (uh->uh_handler(fault_pc, fault_instruction, tf,
429 			       fault_code) == 0)
430 		    break;
431 
432 	if (uh == NULL) {
433 		/* Fault has not been handled */
434 		ksiginfo_t ksi;
435 
436 #ifdef VERBOSE_ARM32
437 		s = spltty();
438 
439 		if ((fault_instruction & 0x0f000010) == 0x0e000000) {
440 			printf("CDP\n");
441 			disassemble(fault_pc);
442 		} else if ((fault_instruction & 0x0e000000) == 0x0c000000) {
443 			printf("LDC/STC\n");
444 			disassemble(fault_pc);
445 		} else if ((fault_instruction & 0x0f000010) == 0x0e000010) {
446 			printf("MRC/MCR\n");
447 			disassemble(fault_pc);
448 		} else if ((fault_instruction & ~INSN_COND_MASK)
449 			 != (KERNEL_BREAKPOINT & ~INSN_COND_MASK)) {
450 			printf("Undefined instruction\n");
451 			disassemble(fault_pc);
452 		}
453 
454 		splx(s);
455 #endif
456 
457 		if ((fault_code & FAULT_USER) == 0) {
458 #ifdef DDB
459 			db_printf("Undefined instruction %#x in kernel at %#lx (LR %#x SP %#x)\n",
460 			    fault_instruction, fault_pc, tf->tf_svc_lr, tf->tf_svc_sp);
461 			kdb_trap(T_FAULT, tf);
462 #else
463 			panic("undefined instruction %#x in kernel at %#lx", fault_instruction, fault_pc);
464 #endif
465 		}
466 		KSI_INIT_TRAP(&ksi);
467 		ksi.ksi_signo = SIGILL;
468 		ksi.ksi_code = ILL_ILLOPC;
469 		ksi.ksi_addr = (uint32_t *)fault_pc;
470 		ksi.ksi_trap = fault_instruction;
471 		trapsignal(l, &ksi);
472 	}
473 
474 	if ((fault_code & FAULT_USER) == 0)
475 		return;
476 
477 #ifdef FAST_FPE
478 	/* Optimised exit code */
479 	{
480 		/*
481 		 * Check for reschedule request, at the moment there is only
482 		 * 1 ast so this code should always be run
483 		 */
484 		if (curcpu()->ci_want_resched) {
485 			/*
486 			 * We are being preempted.
487 			 */
488 			preempt();
489 		}
490 
491 		/* Invoke MI userret code */
492 		mi_userret(l);
493 	}
494 #else
495 	userret(l);
496 #endif
497 }
498