xref: /netbsd-src/sys/arch/arm/arm/undefined.c (revision 6a493d6bc668897c91594964a732d38505b70cbb) 
1 /*	$NetBSD: undefined.c,v 1.50 2013/08/18 08:08:15 matt Exp $	*/
2 
3 /*
4  * Copyright (c) 2001 Ben Harris.
5  * Copyright (c) 1995 Mark Brinicombe.
6  * Copyright (c) 1995 Brini.
7  * All rights reserved.
8  *
9  * This code is derived from software written for Brini by Mark Brinicombe
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the distribution.
19  * 3. All advertising materials mentioning features or use of this software
20  *    must display the following acknowledgement:
21  *	This product includes software developed by Brini.
22  * 4. The name of the company nor the name of the author may be used to
23  *    endorse or promote products derived from this software without specific
24  *    prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
27  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
28  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
29  * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
30  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36  * SUCH DAMAGE.
37  *
38  * RiscBSD kernel project
39  *
40  * undefined.c
41  *
42  * Fault handler
43  *
44  * Created      : 06/01/95
45  */
46 
47 #define FAST_FPE
48 
49 #include "opt_ddb.h"
50 #include "opt_kgdb.h"
51 
52 #include <sys/param.h>
53 #ifdef KGDB
54 #include <sys/kgdb.h>
55 #endif
56 
57 __KERNEL_RCSID(0, "$NetBSD: undefined.c,v 1.50 2013/08/18 08:08:15 matt Exp $");
58 
59 #include <sys/kmem.h>
60 #include <sys/queue.h>
61 #include <sys/signal.h>
62 #include <sys/systm.h>
63 #include <sys/proc.h>
64 #include <sys/syslog.h>
65 #include <sys/vmmeter.h>
66 #include <sys/cpu.h>
67 #ifdef FAST_FPE
68 #include <sys/acct.h>
69 #endif
70 #include <sys/userret.h>
71 
72 #include <uvm/uvm_extern.h>
73 
74 #include <arm/locore.h>
75 #include <arm/undefined.h>
76 
77 #include <machine/pcb.h>
78 #include <machine/trap.h>
79 
80 #include <arch/arm/arm/disassem.h>
81 
82 #ifdef DDB
83 #include <ddb/db_output.h>
84 #include <machine/db_machdep.h>
85 #endif
86 
87 #ifdef acorn26
88 #include <machine/machdep.h>
89 #endif
90 
91 static int gdb_trapper(u_int, u_int, struct trapframe *, int);
92 
93 LIST_HEAD(, undefined_handler) undefined_handlers[NUM_UNKNOWN_HANDLERS];
94 
95 
96 void *
97 install_coproc_handler(int coproc, undef_handler_t handler)
98 {
99 	struct undefined_handler *uh;
100 
101 	KASSERT(coproc >= 0 && coproc < NUM_UNKNOWN_HANDLERS);
102 	KASSERT(handler != NULL); /* Used to be legal. */
103 
104 	uh = kmem_alloc(sizeof(*uh), KM_SLEEP);
105 	uh->uh_handler = handler;
106 	install_coproc_handler_static(coproc, uh);
107 	return uh;
108 }
109 
110 void
111 install_coproc_handler_static(int coproc, struct undefined_handler *uh)
112 {
113 
114 	LIST_INSERT_HEAD(&undefined_handlers[coproc], uh, uh_link);
115 }
116 
117 void
118 remove_coproc_handler(void *cookie)
119 {
120 	struct undefined_handler *uh = cookie;
121 
122 	LIST_REMOVE(uh, uh_link);
123 	kmem_free(uh, sizeof(*uh));
124 }
125 
126 static struct evcnt cp15_ev =
127     EVCNT_INITIALIZER(EVCNT_TYPE_TRAP, NULL, "cpu0", "undefined cp15 insn traps");
128 EVCNT_ATTACH_STATIC(cp15_ev);
129 
130 static int
131 cp15_trapper(u_int addr, u_int insn, struct trapframe *frame, int code)
132 {
133 	struct lwp * const l = curlwp;
134 
135 #if defined(THUMB_CODE) && !defined(CPU_ARMV7)
136 	if (frame->tf_spsr & PSR_T_bit)
137 		return 1;
138 #endif
139 	if (code != FAULT_USER)
140 		return 1;
141 
142 	/*
143 	 * Don't overwrite sp, pc, etc.
144 	 */
145 	const u_int regno = (insn >> 12) & 15;
146 	if (regno > 12)
147 		return 1;
148 
149 	/*
150 	 * Get a pointer to the register used in the instruction to be emulated.
151 	 */
152 	register_t * const regp = &frame->tf_r0 + regno;
153 
154 	/*
155 	 * Handle MRC p15, 0, <Rd>, c13, c0, 3 (Read User read-only thread id)
156 	 */
157 	if ((insn & 0xffff0fff) == 0xee1d0f70) {
158 		*regp = (uintptr_t)l->l_private;
159 		frame->tf_pc += INSN_SIZE;
160 		cp15_ev.ev_count++;
161 		return 0;
162 	}
163 
164 	/*
165 	 * Handle {MRC,MCR} p15, 0, <Rd>, c13, c0, 2 (User read/write thread id)
166 	 */
167 	if ((insn & 0xffef0fff) == 0xee0d0f50) {
168 		struct pcb * const pcb = lwp_getpcb(l);
169 		if (insn & 0x00100000)
170 			*regp = pcb->pcb_user_pid_rw;
171 		else
172 			pcb->pcb_user_pid_rw = *regp;
173 		frame->tf_pc += INSN_SIZE;
174 		cp15_ev.ev_count++;
175 		return 0;
176 	}
177 
178 	return 1;
179 }
180 
181 static int
182 gdb_trapper(u_int addr, u_int insn, struct trapframe *frame, int code)
183 {
184 	struct lwp * const l = curlwp;
185 
186 #ifdef THUMB_CODE
187 	if (frame->tf_spsr & PSR_T_bit) {
188 		if (insn == GDB_THUMB_BREAKPOINT)
189 			goto bkpt;
190 	}
191 	else
192 #endif
193 	{
194 		if (insn == GDB_BREAKPOINT || insn == GDB5_BREAKPOINT) {
195 #ifdef THUMB_CODE
196 		bkpt:
197 #endif
198 			if (code == FAULT_USER) {
199 				ksiginfo_t ksi;
200 
201 				KSI_INIT_TRAP(&ksi);
202 				ksi.ksi_signo = SIGTRAP;
203 				ksi.ksi_code = TRAP_BRKPT;
204 				ksi.ksi_addr = (uint32_t *)addr;
205 				ksi.ksi_trap = 0;
206 				trapsignal(l, &ksi);
207 				return 0;
208 			}
209 #ifdef KGDB
210 			return !kgdb_trap(T_BREAKPOINT, frame);
211 #endif
212 		}
213 	}
214 	return 1;
215 }
216 
217 static struct undefined_handler cp15_uh;
218 static struct undefined_handler gdb_uh;
219 #ifdef THUMB_CODE
220 static struct undefined_handler gdb_uh_thumb;
221 #endif
222 
223 void
224 undefined_init(void)
225 {
226 	int loop;
227 
228 	/* Not actually necessary -- the initialiser is just NULL */
229 	for (loop = 0; loop < NUM_UNKNOWN_HANDLERS; ++loop)
230 		LIST_INIT(&undefined_handlers[loop]);
231 
232 	/* Install handler for CP15 emulation */
233 	cp15_uh.uh_handler = cp15_trapper;
234 	install_coproc_handler_static(SYSTEM_COPROC, &cp15_uh);
235 
236 	/* Install handler for GDB breakpoints */
237 	gdb_uh.uh_handler = gdb_trapper;
238 	install_coproc_handler_static(CORE_UNKNOWN_HANDLER, &gdb_uh);
239 #ifdef THUMB_CODE
240 	gdb_uh_thumb.uh_handler = gdb_trapper;
241 	install_coproc_handler_static(THUMB_UNKNOWN_HANDLER, &gdb_uh_thumb);
242 #endif
243 }
244 
245 static struct evcnt und_ev =
246     EVCNT_INITIALIZER(EVCNT_TYPE_TRAP, NULL, "cpu0", "undefined insn traps");
247 EVCNT_ATTACH_STATIC(und_ev);
248 
249 void
250 undefinedinstruction(trapframe_t *frame)
251 {
252 	struct lwp *l;
253 	u_int fault_pc;
254 	int fault_instruction;
255 	int fault_code;
256 	int coprocessor;
257 	int user;
258 	struct undefined_handler *uh;
259 #ifdef VERBOSE_ARM32
260 	int s;
261 #endif
262 
263 	und_ev.ev_count++;
264 
265 	/* Enable interrupts if they were enabled before the exception. */
266 #ifdef acorn26
267 	if ((frame->tf_r15 & R15_IRQ_DISABLE) == 0)
268 		int_on();
269 #else
270 	restore_interrupts(frame->tf_spsr & IF32_bits);
271 #endif
272 
273 #ifndef acorn26
274 #ifdef THUMB_CODE
275 	if (frame->tf_spsr & PSR_T_bit)
276 		frame->tf_pc -= THUMB_INSN_SIZE;
277 	else
278 #endif
279 	{
280 		frame->tf_pc -= INSN_SIZE;
281 	}
282 #endif
283 
284 #ifdef __PROG26
285 	fault_pc = frame->tf_r15 & R15_PC;
286 #else
287 	fault_pc = frame->tf_pc;
288 #endif
289 
290 	/* Get the current lwp/proc structure or lwp0/proc0 if there is none. */
291 	l = curlwp;
292 
293 #ifdef __PROG26
294 	if ((frame->tf_r15 & R15_MODE) == R15_MODE_USR) {
295 #else
296 	if ((frame->tf_spsr & PSR_MODE) == PSR_USR32_MODE) {
297 #endif
298 		user = 1;
299 		LWP_CACHE_CREDS(l, l->l_proc);
300 	} else
301 		user = 0;
302 
303 
304 #ifdef THUMB_CODE
305 	if (frame->tf_spsr & PSR_T_bit) {
306 		const uint16_t * const pc = (const uint16_t *)(fault_pc & ~1);
307 		fault_instruction = pc[0];
308 #if defined(__ARMEB__) && defined(_ARM_ARCH_7)
309 		fault_instruction = le16toh(fault_instruction);
310 #endif
311 		if (fault_instruction >= 0xe000) {
312 			uint16_t tmp = pc[1];
313 #if defined(__ARMEB__) && defined(_ARM_ARCH_7)
314 			tmp = le16toh(tmp);
315 #endif
316 			fault_instruction = (fault_instruction << 16) | tmp;
317 		}
318 	}
319 	else
320 #endif
321 	{
322 		/*
323 		 * Make sure the program counter is correctly aligned so we
324 		 * don't take an alignment fault trying to read the opcode.
325 		 */
326 		if (__predict_false((fault_pc & 3) != 0)) {
327 			ksiginfo_t ksi;
328 			/* Give the user an illegal instruction signal. */
329 			KSI_INIT_TRAP(&ksi);
330 			ksi.ksi_signo = SIGILL;
331 			ksi.ksi_code = ILL_ILLOPC;
332 			ksi.ksi_addr = (uint32_t *)(intptr_t) fault_pc;
333 			trapsignal(l, &ksi);
334 			userret(l);
335 			return;
336 		}
337 	 	/*
338 		 * Should use fuword() here .. but in the interests of
339 		 * squeezing every  bit of speed we will just use
340 		 * ReadWord(). We know the instruction can be read
341 		 * as was just executed so this will never fail unless
342 		 * the kernel is screwed up in which case it does
343 		 * not really matter does it ?
344 		 */
345 
346 		fault_instruction = *(const uint32_t *)fault_pc;
347 #if defined(__ARMEB__) && defined(_ARM_ARCH_7)
348 		fault_instruction = le32toh(fault_instruction);
349 #endif
350 	}
351 
352 	/* Update vmmeter statistics */
353 	curcpu()->ci_data.cpu_ntrap++;
354 
355 #ifdef THUMB_CODE
356 	if ((frame->tf_spsr & PSR_T_bit) && !CPU_IS_ARMV7_P()) {
357 		coprocessor = THUMB_UNKNOWN_HANDLER;
358 	}
359 	else
360 #endif
361 	{
362 		/* Check for coprocessor instruction */
363 
364 		/*
365 		 * According to the datasheets you only need to look at
366 		 * bit 27 of the instruction to tell the difference
367 		 * between and undefined instruction and a coprocessor
368 		 * instruction following an undefined instruction trap.
369 		 *
370 		 * ARMv5 adds undefined instructions in the NV space,
371 		 * even when bit 27 is set.
372 		 */
373 
374 		if ((fault_instruction & (1 << 27)) != 0
375 		    && (fault_instruction & 0xf0000000) != 0xf0000000) {
376 			coprocessor = (fault_instruction >> 8) & 0x0f;
377 #ifdef THUMB_CODE
378 		} else if ((frame->tf_spsr & PSR_T_bit) && !CPU_IS_ARMV7_P()) {
379 			coprocessor = THUMB_UNKNOWN_HANDLER;
380 #endif
381 		} else {
382 			coprocessor = CORE_UNKNOWN_HANDLER;
383 		}
384 	}
385 
386 	if (user) {
387 		/*
388 		 * Modify the fault_code to reflect the USR/SVC state at
389 		 * time of fault.
390 		 */
391 		fault_code = FAULT_USER;
392 		lwp_settrapframe(l, frame);
393 	} else
394 		fault_code = 0;
395 
396 	/* OK this is were we do something about the instruction. */
397 	LIST_FOREACH(uh, &undefined_handlers[coprocessor], uh_link)
398 	    if (uh->uh_handler(fault_pc, fault_instruction, frame,
399 			       fault_code) == 0)
400 		    break;
401 
402 	if (uh == NULL) {
403 		/* Fault has not been handled */
404 		ksiginfo_t ksi;
405 
406 #ifdef VERBOSE_ARM32
407 		s = spltty();
408 
409 		if ((fault_instruction & 0x0f000010) == 0x0e000000) {
410 			printf("CDP\n");
411 			disassemble(fault_pc);
412 		} else if ((fault_instruction & 0x0e000000) == 0x0c000000) {
413 			printf("LDC/STC\n");
414 			disassemble(fault_pc);
415 		} else if ((fault_instruction & 0x0f000010) == 0x0e000010) {
416 			printf("MRC/MCR\n");
417 			disassemble(fault_pc);
418 		} else if ((fault_instruction & ~INSN_COND_MASK)
419 			 != (KERNEL_BREAKPOINT & ~INSN_COND_MASK)) {
420 			printf("Undefined instruction\n");
421 			disassemble(fault_pc);
422 		}
423 
424 		splx(s);
425 #endif
426 
427 		if ((fault_code & FAULT_USER) == 0) {
428 #ifdef DDB
429 			db_printf("Undefined instruction in kernel\n");
430 			kdb_trap(T_FAULT, frame);
431 #else
432 			panic("undefined instruction in kernel");
433 #endif
434 		}
435 		KSI_INIT_TRAP(&ksi);
436 		ksi.ksi_signo = SIGILL;
437 		ksi.ksi_code = ILL_ILLOPC;
438 		ksi.ksi_addr = (uint32_t *)fault_pc;
439 		ksi.ksi_trap = fault_instruction;
440 		trapsignal(l, &ksi);
441 	}
442 
443 	if ((fault_code & FAULT_USER) == 0)
444 		return;
445 
446 #ifdef FAST_FPE
447 	/* Optimised exit code */
448 	{
449 		/*
450 		 * Check for reschedule request, at the moment there is only
451 		 * 1 ast so this code should always be run
452 		 */
453 		if (curcpu()->ci_want_resched) {
454 			/*
455 			 * We are being preempted.
456 			 */
457 			preempt();
458 		}
459 
460 		/* Invoke MI userret code */
461 		mi_userret(l);
462 	}
463 #else
464 	userret(l);
465 #endif
466 }
467