xref: /netbsd-src/sys/arch/arm/arm/undefined.c (revision 53b02e147d4ed531c0d2a5ca9b3e8026ba3e99b5) 
1 /*	$NetBSD: undefined.c,v 1.72 2021/10/31 16:23:47 skrll Exp $	*/
2 
3 /*
4  * Copyright (c) 2001 Ben Harris.
5  * Copyright (c) 1995 Mark Brinicombe.
6  * Copyright (c) 1995 Brini.
7  * All rights reserved.
8  *
9  * This code is derived from software written for Brini by Mark Brinicombe
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the distribution.
19  * 3. All advertising materials mentioning features or use of this software
20  *    must display the following acknowledgement:
21  *	This product includes software developed by Brini.
22  * 4. The name of the company nor the name of the author may be used to
23  *    endorse or promote products derived from this software without specific
24  *    prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
27  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
28  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
29  * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
30  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36  * SUCH DAMAGE.
37  *
38  * RiscBSD kernel project
39  *
40  * undefined.c
41  *
42  * Fault handler
43  *
44  * Created      : 06/01/95
45  */
46 
47 #include "opt_cputypes.h"
48 #include "opt_ddb.h"
49 #include "opt_dtrace.h"
50 #include "opt_kgdb.h"
51 
52 #include <sys/cdefs.h>
53 __KERNEL_RCSID(0, "$NetBSD: undefined.c,v 1.72 2021/10/31 16:23:47 skrll Exp $");
54 
55 #include <sys/param.h>
56 #include <sys/cpu.h>
57 #include <sys/kmem.h>
58 #ifdef KGDB
59 #include <sys/kgdb.h>
60 #endif
61 #include <sys/proc.h>
62 #include <sys/queue.h>
63 #include <sys/signal.h>
64 #include <sys/systm.h>
65 
66 #include <uvm/uvm_extern.h>
67 
68 #include <arm/locore.h>
69 #include <arm/undefined.h>
70 
71 #include <machine/pcb.h>
72 #include <machine/trap.h>
73 
74 #include <arch/arm/arm/disassem.h>
75 
76 #ifdef DDB
77 #include <ddb/db_output.h>
78 #include <machine/db_machdep.h>
79 #endif
80 
81 static int gdb_trapper(u_int, u_int, struct trapframe *, int);
82 
83 LIST_HEAD(, undefined_handler) undefined_handlers[NUM_UNKNOWN_HANDLERS];
84 
85 
86 void *
87 install_coproc_handler(int coproc, undef_handler_t handler)
88 {
89 	struct undefined_handler *uh;
90 
91 	KASSERT(coproc >= 0 && coproc < NUM_UNKNOWN_HANDLERS);
92 	KASSERT(handler != NULL); /* Used to be legal. */
93 
94 	uh = kmem_alloc(sizeof(*uh), KM_SLEEP);
95 	uh->uh_handler = handler;
96 	install_coproc_handler_static(coproc, uh);
97 	return uh;
98 }
99 
100 void
101 replace_coproc_handler(int coproc, undef_handler_t handler)
102 {
103 	LIST_INIT(&undefined_handlers[coproc]);
104 	install_coproc_handler(coproc, handler);
105 }
106 
107 void
108 install_coproc_handler_static(int coproc, struct undefined_handler *uh)
109 {
110 
111 	LIST_INSERT_HEAD(&undefined_handlers[coproc], uh, uh_link);
112 }
113 
114 void
115 remove_coproc_handler(void *cookie)
116 {
117 	struct undefined_handler *uh = cookie;
118 
119 	LIST_REMOVE(uh, uh_link);
120 	kmem_free(uh, sizeof(*uh));
121 }
122 
123 static int
124 cp15_trapper(u_int addr, u_int insn, struct trapframe *tf, int code)
125 {
126 	struct lwp * const l = curlwp;
127 
128 #if defined(THUMB_CODE) && !defined(CPU_ARMV7)
129 	if (tf->tf_spsr & PSR_T_bit)
130 		return 1;
131 #endif
132 	if (code != FAULT_USER)
133 		return 1;
134 
135 	/*
136 	 * Don't overwrite sp, pc, etc.
137 	 */
138 	const u_int regno = (insn >> 12) & 15;
139 	if (regno == 13 || regno == 15)
140 		return 1;
141 
142 	/*
143 	 * Get a pointer to the register used in the instruction to be emulated.
144 	 */
145 	register_t * const regp = &tf->tf_r0 + regno;
146 
147 	/*
148 	 * Handle MRC p15, 0, <Rd>, c13, c0, 3 (Read User read-only thread id)
149 	 */
150 	if ((insn & 0xffff0fff) == 0xee1d0f70) {
151 		*regp = (uintptr_t)l->l_private;
152 		tf->tf_pc += INSN_SIZE;
153 		curcpu()->ci_und_cp15_ev.ev_count++;
154 		return 0;
155 	}
156 
157 	/*
158 	 * Handle {MRC,MCR} p15, 0, <Rd>, c13, c0, 2 (User read/write thread id)
159 	 */
160 	if ((insn & 0xffef0fff) == 0xee0d0f50) {
161 		struct pcb * const pcb = lwp_getpcb(l);
162 		if (insn & 0x00100000)
163 			*regp = pcb->pcb_user_pid_rw;
164 		else
165 			pcb->pcb_user_pid_rw = *regp;
166 		tf->tf_pc += INSN_SIZE;
167 		curcpu()->ci_und_cp15_ev.ev_count++;
168 		return 0;
169 	}
170 
171 	return 1;
172 }
173 
174 static int
175 gdb_trapper(u_int addr, u_int insn, struct trapframe *tf, int code)
176 {
177 	struct lwp * const l = curlwp;
178 
179 #ifdef THUMB_CODE
180 	if (tf->tf_spsr & PSR_T_bit) {
181 		if (insn == GDB_THUMB_BREAKPOINT)
182 			goto bkpt;
183 	}
184 	else
185 #endif
186 	{
187 		if (insn == GDB_BREAKPOINT || insn == GDB5_BREAKPOINT) {
188 #ifdef THUMB_CODE
189 		bkpt:
190 #endif
191 			if (code == FAULT_USER) {
192 				ksiginfo_t ksi;
193 
194 				KSI_INIT_TRAP(&ksi);
195 				ksi.ksi_signo = SIGTRAP;
196 				ksi.ksi_code = TRAP_BRKPT;
197 				ksi.ksi_addr = (uint32_t *)addr;
198 				ksi.ksi_trap = 0;
199 				trapsignal(l, &ksi);
200 				return 0;
201 			}
202 #ifdef KGDB
203 			return !kgdb_trap(T_BREAKPOINT, tf);
204 #endif
205 		}
206 	}
207 	return 1;
208 }
209 
210 #ifdef FPU_VFP
211 /*
212  * Used to test for a VFP. The following function is installed as a coproc10
213  * handler on the undefined instruction vector and then we issue a VFP
214  * instruction. If ci_vfd_id is set to zero then the VFP did not handle
215  * the instruction so must be absent, or disabled.
216  */
217 
218 static int
219 vfp_test(u_int address, u_int insn, trapframe_t *frame, int fault_code)
220 {
221 	struct cpu_info * const ci = curcpu();
222 
223 	frame->tf_pc += INSN_SIZE;
224 	ci->ci_vfp_id = 0;
225 
226 	return 0;
227 }
228 #endif
229 
230 static struct undefined_handler cp15_uh = {
231 	.uh_handler = cp15_trapper,
232 };
233 static struct undefined_handler gdb_uh = {
234 	.uh_handler = gdb_trapper,
235 };
236 #ifdef THUMB_CODE
237 static struct undefined_handler gdb_uh_thumb = {
238 	.uh_handler = gdb_trapper,
239 };
240 #endif
241 #ifdef FPU_VFP
242 struct undefined_handler vfptest_uh = {
243 	.uh_handler = vfp_test,
244 };
245 #endif
246 
247 #ifdef KDTRACE_HOOKS
248 #include <sys/dtrace_bsd.h>
249 
250 /* Not used for now, but needed for dtrace/fbt modules */
251 dtrace_doubletrap_func_t	dtrace_doubletrap_func = NULL;
252 dtrace_trap_func_t		dtrace_trap_func = NULL;
253 
254 int (* dtrace_invop_jump_addr)(struct trapframe *);
255 
256 static int
257 dtrace_trapper(u_int addr, struct trapframe *frame)
258 {
259 	u_int insn = read_insn(addr, false);
260 
261 	if (dtrace_invop_jump_addr == NULL)
262 		return 1;
263 
264 	if (!DTRACE_IS_BREAKPOINT(insn))
265 		return 1;
266 
267 	/* cond value is encoded in the low nibble */
268 	if (!arm_cond_ok_p(__SHIFTIN(insn, INSN_COND_MASK), frame->tf_spsr)) {
269 		frame->tf_pc += INSN_SIZE;
270 		return 0;
271 	}
272 
273 	dtrace_invop_jump_addr(frame);
274 	return 0;
275 }
276 #endif
277 
278 void
279 undefined_init(void)
280 {
281 	int loop;
282 
283 	/* Not actually necessary -- the initialiser is just NULL */
284 	for (loop = 0; loop < NUM_UNKNOWN_HANDLERS; ++loop)
285 		LIST_INIT(&undefined_handlers[loop]);
286 
287 	/* Install handler for CP15 emulation */
288 	install_coproc_handler_static(SYSTEM_COPROC, &cp15_uh);
289 
290 	/* Install handler for GDB breakpoints */
291 	install_coproc_handler_static(CORE_UNKNOWN_HANDLER, &gdb_uh);
292 #ifdef THUMB_CODE
293 	install_coproc_handler_static(THUMB_UNKNOWN_HANDLER, &gdb_uh_thumb);
294 #endif
295 #ifdef FPU_VFP
296 	install_coproc_handler_static(VFP_COPROC, &vfptest_uh);
297 #endif
298 }
299 
300 void
301 undefinedinstruction(trapframe_t *tf)
302 {
303 	struct lwp *l;
304 	vaddr_t fault_pc;
305 	int fault_instruction;
306 	int fault_code;
307 	int coprocessor;
308 	int user;
309 	struct undefined_handler *uh;
310 #ifdef VERBOSE_ARM32
311 	int s;
312 #endif
313 
314 	curcpu()->ci_und_ev.ev_count++;
315 
316 #ifdef KDTRACE_HOOKS
317 	if ((tf->tf_spsr & PSR_MODE) != PSR_USR32_MODE) {
318 		tf->tf_pc -= INSN_SIZE;
319 		if (dtrace_trapper(tf->tf_pc, tf) == 0)
320 			return;
321 		tf->tf_pc += INSN_SIZE; /* Reset for the rest code */
322 	}
323 #endif
324 
325 	/* Enable interrupts if they were enabled before the exception. */
326 	restore_interrupts(tf->tf_spsr & IF32_bits);
327 
328 #ifdef THUMB_CODE
329 	if (tf->tf_spsr & PSR_T_bit)
330 		tf->tf_pc -= THUMB_INSN_SIZE;
331 	else
332 #endif
333 	{
334 		tf->tf_pc -= INSN_SIZE;
335 	}
336 
337 	fault_pc = tf->tf_pc;
338 
339 	/* Get the current lwp/proc structure or lwp0/proc0 if there is none. */
340 	l = curlwp;
341 
342 	if ((tf->tf_spsr & PSR_MODE) == PSR_USR32_MODE) {
343 		user = 1;
344 		LWP_CACHE_CREDS(l, l->l_proc);
345 	} else
346 		user = 0;
347 
348 
349 #ifdef THUMB_CODE
350 	if (tf->tf_spsr & PSR_T_bit) {
351 		fault_instruction = read_thumb_insn(fault_pc, user);
352 		if (fault_instruction >= 0xe000) {
353 			fault_instruction = (fault_instruction << 16)
354 			    | read_thumb_insn(fault_pc + 2, user);
355 		}
356 	}
357 	else
358 #endif
359 	{
360 		/*
361 		 * Make sure the program counter is correctly aligned so we
362 		 * don't take an alignment fault trying to read the opcode.
363 		 */
364 		if (__predict_false((fault_pc & 3) != 0)) {
365 			ksiginfo_t ksi;
366 			/* Give the user an illegal instruction signal. */
367 			KSI_INIT_TRAP(&ksi);
368 			ksi.ksi_signo = SIGILL;
369 			ksi.ksi_code = ILL_ILLOPC;
370 			ksi.ksi_addr = (uint32_t *)(intptr_t) fault_pc;
371 			trapsignal(l, &ksi);
372 			userret(l);
373 			return;
374 		}
375 	 	/*
376 		 * Should use ufetch_32() here .. but in the interests of
377 		 * squeezing every bit of speed we will just use
378 		 * read_insn(). We know the instruction can be read
379 		 * as was just executed so this will never fail unless
380 		 * the kernel is screwed up in which case it does
381 		 * not really matter does it?
382 		 */
383 		fault_instruction = read_insn(fault_pc, user);
384 	}
385 
386 	curcpu()->ci_data.cpu_ntrap++;
387 
388 #ifdef THUMB_CODE
389 	if ((tf->tf_spsr & PSR_T_bit) && !CPU_IS_ARMV7_P()) {
390 		coprocessor = THUMB_UNKNOWN_HANDLER;
391 	}
392 	else
393 #endif
394 	{
395 		/* Check for coprocessor instruction */
396 
397 		/*
398 		 * According to the datasheets you only need to look at
399 		 * bit 27 of the instruction to tell the difference
400 		 * between and undefined instruction and a coprocessor
401 		 * instruction following an undefined instruction trap.
402 		 *
403 		 * ARMv5 adds undefined instructions in the NV space,
404 		 * even when bit 27 is set.
405 		 */
406 
407 		if ((fault_instruction & (1 << 27)) != 0
408 		    && (fault_instruction & 0xf0000000) != 0xf0000000) {
409 			coprocessor = (fault_instruction >> 8) & 0x0f;
410 #ifdef THUMB_CODE
411 		} else if ((tf->tf_spsr & PSR_T_bit) && !CPU_IS_ARMV7_P()) {
412 			coprocessor = THUMB_UNKNOWN_HANDLER;
413 #endif
414 		} else {
415 			coprocessor = CORE_UNKNOWN_HANDLER;
416 		}
417 	}
418 
419 	if (user) {
420 		/*
421 		 * Modify the fault_code to reflect the USR/SVC state at
422 		 * time of fault.
423 		 */
424 		fault_code = FAULT_USER;
425 		KASSERTMSG(tf == lwp_trapframe(l), "tf %p vs %p", tf,
426 		    lwp_trapframe(l));
427 	} else
428 		fault_code = 0;
429 
430 	/* OK this is were we do something about the instruction. */
431 	LIST_FOREACH(uh, &undefined_handlers[coprocessor], uh_link) {
432 		int ret = uh->uh_handler(fault_pc, fault_instruction, tf,
433 		    fault_code);
434 
435 		if (ret == 0)
436 			break;
437 	}
438 
439 	if (uh == NULL) {
440 		/* Fault has not been handled */
441 		ksiginfo_t ksi;
442 
443 #ifdef VERBOSE_ARM32
444 		s = spltty();
445 
446 		if ((fault_instruction & 0x0f000010) == 0x0e000000) {
447 			printf("CDP\n");
448 			disassemble(fault_pc);
449 		} else if ((fault_instruction & 0x0e000000) == 0x0c000000) {
450 			printf("LDC/STC\n");
451 			disassemble(fault_pc);
452 		} else if ((fault_instruction & 0x0f000010) == 0x0e000010) {
453 			printf("MRC/MCR\n");
454 			disassemble(fault_pc);
455 		} else if ((fault_instruction & ~INSN_COND_MASK)
456 			 != (KERNEL_BREAKPOINT & ~INSN_COND_MASK)) {
457 			printf("Undefined instruction\n");
458 			disassemble(fault_pc);
459 		}
460 
461 		splx(s);
462 #endif
463 
464 		if ((fault_code & FAULT_USER) == 0) {
465 #ifdef DDB
466 			db_printf("Undefined instruction %#x in kernel at %#lx (LR %#x SP %#x)\n",
467 			    fault_instruction, fault_pc, tf->tf_svc_lr, tf->tf_svc_sp);
468 			kdb_trap(T_FAULT, tf);
469 #else
470 			panic("undefined instruction %#x in kernel at %#lx", fault_instruction, fault_pc);
471 #endif
472 		}
473 		KSI_INIT_TRAP(&ksi);
474 		ksi.ksi_signo = SIGILL;
475 		ksi.ksi_code = ILL_ILLOPC;
476 		ksi.ksi_addr = (uint32_t *)fault_pc;
477 		ksi.ksi_trap = fault_instruction;
478 		trapsignal(l, &ksi);
479 	}
480 
481 	if ((fault_code & FAULT_USER) == 0)
482 		return;
483 
484 	userret(l);
485 }
486