1/* $NetBSD: cpufunc_asm_arm10.S,v 1.5 2005/12/11 12:16:41 christos Exp $ */ 2 3/* 4 * Copyright (c) 2002 ARM Limited 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company may not be used to endorse or promote 16 * products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * ARM10 assembly functions for CPU / MMU / TLB specific operations 32 */ 33 34#include <machine/cpu.h> 35#include <machine/asm.h> 36 37/* 38 * Functions to set the MMU Translation Table Base register 39 * 40 * We need to clean and flush the cache as it uses virtual 41 * addresses that are about to change. 42 */ 43ENTRY(arm10_setttb) 44 stmfd sp!, {r0, lr} 45 bl _C_LABEL(armv5_idcache_wbinv_all) 46 ldmfd sp!, {r0, lr} 47 48 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ 49 50 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ 51 RET 52 53/* 54 * TLB functions 55 */ 56ENTRY(arm10_tlb_flushID_SE) 57 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ 58 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */ 59 RET 60 61ENTRY(arm10_tlb_flushI_SE) 62 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */ 63 RET 64 65 66/* 67 * Context switch. 68 * 69 * These is the CPU-specific parts of the context switcher cpu_switch() 70 * These functions actually perform the TTB reload. 71 * 72 * NOTE: Special calling convention 73 * r1, r4-r13 must be preserved 74 */ 75ENTRY(arm10_context_switch) 76 /* 77 * We can assume that the caches will only contain kernel addresses 78 * at this point. So no need to flush them again. 79 */ 80 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 81 mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */ 82 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */ 83 84 /* Paranoia -- make sure the pipeline is empty. */ 85 nop 86 nop 87 nop 88 RET 89