1/* $NetBSD: cpufunc_asm.S,v 1.14 2008/04/27 18:58:43 matt Exp $ */ 2 3/* 4 * Copyright (c) 1997,1998 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Causality Limited. 19 * 4. The name of Causality Limited may not be used to endorse or promote 20 * products derived from this software without specific prior written 21 * permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.S 38 * 39 * Assembly functions for CPU / MMU / TLB specific operations 40 * 41 * Created : 30/01/97 42 */ 43 44#include <machine/asm.h> 45#include <machine/cpu.h> 46 47 .text 48 .align 0 49 50ENTRY(cpufunc_nullop) 51 RET 52 53/* 54 * Generic functions to read the internal coprocessor registers 55 * 56 * Currently these registers are : 57 * c0 - CPU ID 58 * c5 - Fault status 59 * c6 - Fault address 60 * 61 */ 62 63ENTRY(cpufunc_id) 64 mrc p15, 0, r0, c0, c0, 0 65 RET 66 67ENTRY(cpu_get_control) 68 mrc p15, 0, r0, c1, c0, 0 69 RET 70 71ENTRY(cpu_read_cache_config) 72 mrc p15, 0, r0, c0, c0, 1 73 RET 74 75ENTRY(cpufunc_faultstatus) 76 mrc p15, 0, r0, c5, c0, 0 77 RET 78 79ENTRY(cpufunc_faultaddress) 80 mrc p15, 0, r0, c6, c0, 0 81 RET 82 83 84/* 85 * Generic functions to write the internal coprocessor registers 86 * 87 * 88 * Currently these registers are 89 * c1 - CPU Control 90 * c3 - Domain Access Control 91 * 92 * All other registers are CPU architecture specific 93 */ 94 95#if 0 /* See below. */ 96ENTRY(cpufunc_control) 97 mcr p15, 0, r0, c1, c0, 0 98 RET 99#endif 100 101ENTRY(cpufunc_domains) 102 mcr p15, 0, r0, c3, c0, 0 103 RET 104 105/* 106 * Generic functions to read/modify/write the internal coprocessor registers 107 * 108 * 109 * Currently these registers are 110 * c1 - CPU Control 111 * 112 * All other registers are CPU architecture specific 113 */ 114 115ENTRY(cpufunc_control) 116 mrc p15, 0, r3, c1, c0, 0 /* Read the control register */ 117 bic r2, r3, r0 /* Clear bits */ 118 eor r2, r2, r1 /* XOR bits */ 119 120 teq r2, r3 /* Only write if there is a change */ 121 mcrne p15, 0, r2, c1, c0, 0 /* Write new control register */ 122 mov r0, r3 /* Return old value */ 123 RET 124 125/* 126 * other potentially useful software functions are: 127 * clean D cache entry and flush I cache entry 128 * for the moment use cache_purgeID_E 129 */ 130 131/* Random odd functions */ 132 133/* 134 * Function to get the offset of a stored program counter from the 135 * instruction doing the store. This offset is defined to be the same 136 * for all STRs and STMs on a given implementation. Code based on 137 * section 2.4.3 of the ARM ARM (2nd Ed.), with modifications to work 138 * in 26-bit modes as well. 139 */ 140ENTRY(get_pc_str_offset) 141 mov ip, sp 142 stmfd sp!, {fp, ip, lr, pc} 143 sub fp, ip, #4 144 sub sp, sp, #4 145 mov r1, pc /* R1 = addr of following STR */ 146 mov r0, r0 147 str pc, [sp] /* [SP] = . + offset */ 148 ldr r0, [sp] 149 sub r0, r0, r1 150 ldmdb fp, {fp, sp, pc} 151