1 /* $NetBSD: mesongxl_usb3phy.c,v 1.2 2021/01/27 03:10:18 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(0, "$NetBSD: mesongxl_usb3phy.c,v 1.2 2021/01/27 03:10:18 thorpej Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 #include <sys/time.h> 39 40 #include <dev/fdt/fdtvar.h> 41 42 #define USB3PHY_REG0 0x00 43 #define REG0_U2D_ACT __BIT(31) 44 45 #define USB3PHY_REG1 0x04 46 #define REG1_U3H_FLADJ_30MHZ_REG __BITS(24,19) 47 48 #define USB3PHY_REG4 0x10 49 #define REG4_P21_SLEEP_M0 __BIT(1) 50 51 #define USB3PHY_REG5 0x14 52 #define REG5_ID_DIG_TH __BITS(15,8) 53 #define REG5_ID_DIG_EN_1 __BIT(5) 54 #define REG5_ID_DIG_EN_0 __BIT(4) 55 56 static int mesongxl_usb3phy_match(device_t, cfdata_t, void *); 57 static void mesongxl_usb3phy_attach(device_t, device_t, void *); 58 59 static const struct device_compatible_entry compat_data[] = { 60 { .compat = "amlogic,meson-gxl-usb3-phy" }, 61 DEVICE_COMPAT_EOL 62 }; 63 64 struct mesongxl_usb3phy_softc { 65 device_t sc_dev; 66 bus_space_tag_t sc_bst; 67 bus_space_handle_t sc_bsh; 68 int sc_phandle; 69 struct clk *sc_clk_phy; 70 struct clk *sc_clk_peripheral; 71 }; 72 73 #define PHY_READ(sc, reg) \ 74 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 75 #define PHY_WRITE(sc, reg, val) \ 76 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 77 78 CFATTACH_DECL_NEW(mesongxl_usb3phy, sizeof(struct mesongxl_usb3phy_softc), 79 mesongxl_usb3phy_match, mesongxl_usb3phy_attach, NULL, NULL); 80 81 static void * 82 mesongxl_usb3phy_acquire(device_t dev, const void *data, size_t len) 83 { 84 if (len != 0) 85 return NULL; 86 87 return (void *)(uintptr_t)1; 88 } 89 90 static void 91 mesongxl_usb3phy_release(device_t dev, void *priv) 92 { 93 } 94 95 static int 96 mesongxl_usb3phy_enable(device_t dev, void *priv, bool enable) 97 { 98 struct mesongxl_usb3phy_softc * const sc = device_private(dev); 99 uint32_t val; 100 101 if (enable) { 102 /* Power on PHY */ 103 val = PHY_READ(sc, USB3PHY_REG5); 104 val |= REG5_ID_DIG_EN_0; 105 val |= REG5_ID_DIG_EN_1; 106 val &= ~REG5_ID_DIG_TH; 107 val |= __SHIFTIN(0xff, REG5_ID_DIG_TH); 108 PHY_WRITE(sc, USB3PHY_REG5, val); 109 110 /* Set host mode */ 111 val = PHY_READ(sc, USB3PHY_REG0); 112 val &= ~REG0_U2D_ACT; 113 PHY_WRITE(sc, USB3PHY_REG0, val); 114 115 val = PHY_READ(sc, USB3PHY_REG4); 116 val &= ~REG4_P21_SLEEP_M0; 117 PHY_WRITE(sc, USB3PHY_REG4, val); 118 } else { 119 /* Power off PHY */ 120 val = PHY_READ(sc, USB3PHY_REG5); 121 val &= ~REG5_ID_DIG_EN_0; 122 val &= ~REG5_ID_DIG_EN_1; 123 PHY_WRITE(sc, USB3PHY_REG5, val); 124 } 125 126 return 0; 127 } 128 129 const struct fdtbus_phy_controller_func mesongxl_usb3phy_funcs = { 130 .acquire = mesongxl_usb3phy_acquire, 131 .release = mesongxl_usb3phy_release, 132 .enable = mesongxl_usb3phy_enable, 133 }; 134 135 static void 136 mesongxl_usb3phy_init(struct mesongxl_usb3phy_softc *sc) 137 { 138 uint32_t val; 139 140 val = PHY_READ(sc, USB3PHY_REG1); 141 val &= ~REG1_U3H_FLADJ_30MHZ_REG; 142 val |= __SHIFTIN(0x20, REG1_U3H_FLADJ_30MHZ_REG); 143 PHY_WRITE(sc, USB3PHY_REG1, val); 144 } 145 146 static int 147 mesongxl_usb3phy_match(device_t parent, cfdata_t cf, void *aux) 148 { 149 struct fdt_attach_args * const faa = aux; 150 151 return of_compatible_match(faa->faa_phandle, compat_data); 152 } 153 154 static void 155 mesongxl_usb3phy_attach(device_t parent, device_t self, void *aux) 156 { 157 struct mesongxl_usb3phy_softc * const sc = device_private(self); 158 struct fdt_attach_args * const faa = aux; 159 const int phandle = faa->faa_phandle; 160 struct fdtbus_regulator *supply; 161 struct fdtbus_reset *rst; 162 bus_addr_t addr; 163 bus_size_t size; 164 u_int n; 165 166 sc->sc_dev = self; 167 sc->sc_bst = faa->faa_bst; 168 sc->sc_phandle = phandle; 169 170 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 171 aprint_error(": couldn't get registers\n"); 172 return; 173 } 174 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 175 aprint_error(": couldn't map registers\n"); 176 return; 177 } 178 179 sc->sc_clk_phy = fdtbus_clock_get(phandle, "phy"); 180 if (sc->sc_clk_phy == NULL) { 181 aprint_error(": couldn't get phy clock\n"); 182 return; 183 } 184 #if notyet 185 sc->sc_clk_peripheral = fdtbus_clock_get(phandle, "peripheral"); 186 if (sc->sc_clk_peripheral == NULL) { 187 aprint_error(": couldn't get peripheral clock\n"); 188 return; 189 } 190 #endif 191 192 for (n = 0; (rst = fdtbus_reset_get_index(phandle, n)) != NULL; n++) { 193 if (fdtbus_reset_deassert(rst) != 0) { 194 aprint_error(": couldn't de-assert reset #%d\n", n); 195 return; 196 } 197 } 198 if (clk_enable(sc->sc_clk_phy) != 0) { 199 aprint_error(": couldn't enable phy clock\n"); 200 return; 201 } 202 #if notyet 203 if (clk_enable(sc->sc_clk_peripheral) != 0) { 204 aprint_error(": couldn't enable peripheral clock\n"); 205 return; 206 } 207 #endif 208 209 supply = fdtbus_regulator_acquire(phandle, "phy-supply"); 210 if (supply != NULL) { 211 if (fdtbus_regulator_enable(supply) != 0) { 212 aprint_error(": couldn't enable supply\n"); 213 return; 214 } 215 } 216 217 aprint_naive("\n"); 218 aprint_normal(": USB3 PHY\n"); 219 220 mesongxl_usb3phy_init(sc); 221 222 fdtbus_register_phy_controller(self, phandle, &mesongxl_usb3phy_funcs); 223 } 224