1 /* $NetBSD: meson_dwmac.c,v 1.8 2020/02/06 00:32:07 rjs Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(0, "$NetBSD: meson_dwmac.c,v 1.8 2020/02/06 00:32:07 rjs Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 #include <sys/gpio.h> 39 #include <sys/rndsource.h> 40 41 #include <net/if.h> 42 #include <net/if_ether.h> 43 #include <net/if_media.h> 44 45 #include <dev/mii/miivar.h> 46 47 #include <dev/ic/dwc_gmac_var.h> 48 #include <dev/ic/dwc_gmac_reg.h> 49 50 #include <dev/fdt/fdtvar.h> 51 52 #define PRG_ETHERNET_ADDR0 0x00 53 #define CLKGEN_ENABLE __BIT(12) 54 #define RMII_CLK_I_INVERTED __BIT(11) 55 #define PHY_CLK_ENABLE __BIT(10) 56 #define MP2_CLK_OUT_DIV __BITS(9,7) 57 #define TX_CLK_DELAY __BITS(6,5) 58 #define PHY_INTERFACE_SEL __BIT(0) 59 60 static const char * compatible[] = { 61 "amlogic,meson8b-dwmac", 62 "amlogic,meson-gx-dwmac", 63 "amlogic,meson-gxbb-dwmac", 64 NULL 65 }; 66 67 static int 68 meson_dwmac_reset(const int phandle) 69 { 70 struct fdtbus_gpio_pin *pin_reset; 71 const u_int *reset_delay_us; 72 bool reset_active_low; 73 int len, val; 74 75 pin_reset = fdtbus_gpio_acquire(phandle, "snps,reset-gpio", GPIO_PIN_OUTPUT); 76 if (pin_reset == NULL) 77 return 0; 78 79 reset_delay_us = fdtbus_get_prop(phandle, "snps,reset-delays-us", &len); 80 if (reset_delay_us == NULL || len != 12) 81 return ENXIO; 82 83 reset_active_low = of_hasprop(phandle, "snps,reset-active-low"); 84 85 val = reset_active_low ? 1 : 0; 86 87 fdtbus_gpio_write(pin_reset, val); 88 delay(be32toh(reset_delay_us[0])); 89 fdtbus_gpio_write(pin_reset, !val); 90 delay(be32toh(reset_delay_us[1])); 91 fdtbus_gpio_write(pin_reset, val); 92 delay(be32toh(reset_delay_us[2])); 93 94 return 0; 95 } 96 97 static void 98 meson_dwmac_set_mode_rgmii(int phandle, bus_space_tag_t bst, 99 bus_space_handle_t bsh, struct clk *clkin) 100 { 101 u_int tx_delay; 102 uint32_t val; 103 104 const u_int div = clk_get_rate(clkin) / 250000000; 105 106 if (of_getprop_uint32(phandle, "amlogic,tx-delay-ns", &tx_delay) != 0) 107 tx_delay = 2; 108 109 val = bus_space_read_4(bst, bsh, PRG_ETHERNET_ADDR0); 110 val |= PHY_INTERFACE_SEL; 111 val &= ~TX_CLK_DELAY; 112 val |= __SHIFTIN((tx_delay >> 1), TX_CLK_DELAY); 113 val &= ~MP2_CLK_OUT_DIV; 114 val |= __SHIFTIN(div, MP2_CLK_OUT_DIV); 115 val |= PHY_CLK_ENABLE; 116 val |= CLKGEN_ENABLE; 117 bus_space_write_4(bst, bsh, PRG_ETHERNET_ADDR0, val); 118 } 119 120 static void 121 meson_dwmac_set_mode_rmii(int phandle, bus_space_tag_t bst, 122 bus_space_handle_t bsh) 123 { 124 uint32_t val; 125 126 val = bus_space_read_4(bst, bsh, PRG_ETHERNET_ADDR0); 127 val &= ~PHY_INTERFACE_SEL; 128 val |= RMII_CLK_I_INVERTED; 129 val &= ~TX_CLK_DELAY; 130 val |= CLKGEN_ENABLE; 131 bus_space_write_4(bst, bsh, PRG_ETHERNET_ADDR0, val); 132 } 133 134 static int 135 meson_dwmac_intr(void *arg) 136 { 137 struct dwc_gmac_softc * const sc = arg; 138 139 return dwc_gmac_intr(sc); 140 } 141 142 static int 143 meson_dwmac_match(device_t parent, cfdata_t cf, void *aux) 144 { 145 struct fdt_attach_args * const faa = aux; 146 147 return of_match_compatible(faa->faa_phandle, compatible); 148 } 149 150 static void 151 meson_dwmac_attach(device_t parent, device_t self, void *aux) 152 { 153 struct dwc_gmac_softc * const sc = device_private(self); 154 struct fdt_attach_args * const faa = aux; 155 const int phandle = faa->faa_phandle; 156 bus_space_handle_t prgeth_bsh; 157 struct fdtbus_reset *rst_gmac; 158 struct clk *clk_gmac, *clk_in[2]; 159 const char *phy_mode; 160 char intrstr[128]; 161 bus_addr_t addr[2]; 162 bus_size_t size[2]; 163 164 if (fdtbus_get_reg(phandle, 0, &addr[0], &size[0]) != 0 || 165 fdtbus_get_reg(phandle, 1, &addr[1], &size[1]) != 0) { 166 aprint_error(": couldn't get registers\n"); 167 return; 168 } 169 170 sc->sc_dev = self; 171 sc->sc_bst = faa->faa_bst; 172 if (bus_space_map(sc->sc_bst, addr[0], size[0], 0, &sc->sc_bsh) != 0 || 173 bus_space_map(sc->sc_bst, addr[1], size[1], 0, &prgeth_bsh) != 0) { 174 aprint_error(": couldn't map registers\n"); 175 return; 176 } 177 sc->sc_dmat = faa->faa_dmat; 178 179 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 180 aprint_error(": failed to decode interrupt\n"); 181 return; 182 } 183 184 clk_gmac = fdtbus_clock_get(phandle, "stmmaceth"); 185 clk_in[0] = fdtbus_clock_get(phandle, "clkin0"); 186 clk_in[1] = fdtbus_clock_get(phandle, "clkin1"); 187 if (clk_gmac == NULL || clk_in[0] == NULL || clk_in[1] == NULL) { 188 aprint_error(": couldn't get clocks\n"); 189 return; 190 } 191 192 rst_gmac = fdtbus_reset_get(phandle, "stmmaceth"); 193 194 phy_mode = fdtbus_get_string(phandle, "phy-mode"); 195 if (phy_mode == NULL) { 196 aprint_error(": missing 'phy-mode' property\n"); 197 return; 198 } 199 200 if (strcmp(phy_mode, "rgmii") == 0) { 201 meson_dwmac_set_mode_rgmii(phandle, sc->sc_bst, prgeth_bsh, clk_in[0]); 202 } else if (strcmp(phy_mode, "rmii") == 0) { 203 meson_dwmac_set_mode_rmii(phandle, sc->sc_bst, prgeth_bsh); 204 } else { 205 aprint_error(": unsupported phy-mode '%s'\n", phy_mode); 206 return; 207 } 208 209 if (clk_enable(clk_gmac) != 0) { 210 aprint_error(": couldn't enable clock\n"); 211 return; 212 } 213 214 if (rst_gmac != NULL && fdtbus_reset_deassert(rst_gmac) != 0) { 215 aprint_error(": couldn't de-assert reset\n"); 216 return; 217 } 218 219 aprint_naive("\n"); 220 aprint_normal(": Gigabit Ethernet Controller\n"); 221 222 if (fdtbus_intr_establish(phandle, 0, IPL_NET, DWCGMAC_FDT_INTR_MPSAFE, 223 meson_dwmac_intr, sc) == NULL) { 224 aprint_error_dev(self, "failed to establish interrupt on %s\n", intrstr); 225 return; 226 } 227 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 228 229 if (meson_dwmac_reset(phandle) != 0) 230 aprint_error_dev(self, "PHY reset failed\n"); 231 232 dwc_gmac_attach(sc, MII_PHY_ANY, GMAC_MII_CLK_100_150M_DIV62); 233 } 234 235 CFATTACH_DECL_NEW(meson_dwmac, sizeof(struct dwc_gmac_softc), 236 meson_dwmac_match, meson_dwmac_attach, NULL, NULL); 237