1 /* $NetBSD: meson_dwmac.c,v 1.11 2021/01/27 03:10:18 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(0, "$NetBSD: meson_dwmac.c,v 1.11 2021/01/27 03:10:18 thorpej Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 #include <sys/gpio.h> 39 #include <sys/rndsource.h> 40 41 #include <net/if.h> 42 #include <net/if_ether.h> 43 #include <net/if_media.h> 44 45 #include <dev/mii/miivar.h> 46 47 #include <dev/ic/dwc_gmac_var.h> 48 #include <dev/ic/dwc_gmac_reg.h> 49 50 #include <dev/fdt/fdtvar.h> 51 52 #define PRG_ETHERNET_ADDR0 0x00 53 #define CLKGEN_ENABLE __BIT(12) 54 #define RMII_CLK_I_INVERTED __BIT(11) 55 #define PHY_CLK_ENABLE __BIT(10) 56 #define MP2_CLK_OUT_DIV __BITS(9,7) 57 #define TX_CLK_DELAY __BITS(6,5) 58 #define PHY_INTERFACE_SEL __BIT(0) 59 60 static const struct device_compatible_entry compat_data[] = { 61 { .compat = "amlogic,meson8b-dwmac" }, 62 { .compat = "amlogic,meson-gx-dwmac" }, 63 { .compat = "amlogic,meson-gxbb-dwmac" }, 64 { .compat = "amlogic,meson-axg-dwmac" }, 65 DEVICE_COMPAT_EOL 66 }; 67 68 static int 69 meson_dwmac_reset(const int phandle) 70 { 71 struct fdtbus_gpio_pin *pin_reset; 72 const u_int *reset_delay_us; 73 bool reset_active_low; 74 int len, val; 75 76 pin_reset = fdtbus_gpio_acquire(phandle, "snps,reset-gpio", GPIO_PIN_OUTPUT); 77 if (pin_reset == NULL) 78 return 0; 79 80 reset_delay_us = fdtbus_get_prop(phandle, "snps,reset-delays-us", &len); 81 if (reset_delay_us == NULL || len != 12) 82 return ENXIO; 83 84 reset_active_low = of_hasprop(phandle, "snps,reset-active-low"); 85 86 val = reset_active_low ? 1 : 0; 87 88 fdtbus_gpio_write(pin_reset, val); 89 delay(be32toh(reset_delay_us[0])); 90 fdtbus_gpio_write(pin_reset, !val); 91 delay(be32toh(reset_delay_us[1])); 92 fdtbus_gpio_write(pin_reset, val); 93 delay(be32toh(reset_delay_us[2])); 94 95 return 0; 96 } 97 98 static void 99 meson_dwmac_set_mode_rgmii(int phandle, bus_space_tag_t bst, 100 bus_space_handle_t bsh, struct clk *clkin) 101 { 102 u_int tx_delay; 103 uint32_t val; 104 105 #define DIV_ROUND_OFF(x, y) (((x) + (y) / 2) / (y)) 106 const u_int div = DIV_ROUND_OFF(clk_get_rate(clkin), 250000000); 107 108 if (of_getprop_uint32(phandle, "amlogic,tx-delay-ns", &tx_delay) != 0) 109 tx_delay = 2; 110 111 val = bus_space_read_4(bst, bsh, PRG_ETHERNET_ADDR0); 112 val |= PHY_INTERFACE_SEL; 113 val &= ~TX_CLK_DELAY; 114 val |= __SHIFTIN((tx_delay >> 1), TX_CLK_DELAY); 115 val &= ~MP2_CLK_OUT_DIV; 116 val |= __SHIFTIN(div, MP2_CLK_OUT_DIV); 117 val |= PHY_CLK_ENABLE; 118 val |= CLKGEN_ENABLE; 119 bus_space_write_4(bst, bsh, PRG_ETHERNET_ADDR0, val); 120 } 121 122 static void 123 meson_dwmac_set_mode_rmii(int phandle, bus_space_tag_t bst, 124 bus_space_handle_t bsh) 125 { 126 uint32_t val; 127 128 val = bus_space_read_4(bst, bsh, PRG_ETHERNET_ADDR0); 129 val &= ~PHY_INTERFACE_SEL; 130 val |= RMII_CLK_I_INVERTED; 131 val &= ~TX_CLK_DELAY; 132 val |= CLKGEN_ENABLE; 133 bus_space_write_4(bst, bsh, PRG_ETHERNET_ADDR0, val); 134 } 135 136 static int 137 meson_dwmac_intr(void *arg) 138 { 139 struct dwc_gmac_softc * const sc = arg; 140 141 return dwc_gmac_intr(sc); 142 } 143 144 static int 145 meson_dwmac_match(device_t parent, cfdata_t cf, void *aux) 146 { 147 struct fdt_attach_args * const faa = aux; 148 149 return of_compatible_match(faa->faa_phandle, compat_data); 150 } 151 152 static void 153 meson_dwmac_attach(device_t parent, device_t self, void *aux) 154 { 155 struct dwc_gmac_softc * const sc = device_private(self); 156 struct fdt_attach_args * const faa = aux; 157 const int phandle = faa->faa_phandle; 158 int miiclk, phandle_phy, phy = MII_PHY_ANY; 159 u_int miiclk_rate; 160 bus_space_handle_t prgeth_bsh; 161 struct fdtbus_reset *rst_gmac; 162 struct clk *clk_gmac, *clk_in[2]; 163 const char *phy_mode; 164 char intrstr[128]; 165 bus_addr_t addr[2]; 166 bus_size_t size[2]; 167 168 if (fdtbus_get_reg(phandle, 0, &addr[0], &size[0]) != 0 || 169 fdtbus_get_reg(phandle, 1, &addr[1], &size[1]) != 0) { 170 aprint_error(": couldn't get registers\n"); 171 return; 172 } 173 174 sc->sc_dev = self; 175 sc->sc_bst = faa->faa_bst; 176 if (bus_space_map(sc->sc_bst, addr[0], size[0], 0, &sc->sc_bsh) != 0 || 177 bus_space_map(sc->sc_bst, addr[1], size[1], 0, &prgeth_bsh) != 0) { 178 aprint_error(": couldn't map registers\n"); 179 return; 180 } 181 sc->sc_dmat = faa->faa_dmat; 182 183 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 184 aprint_error(": failed to decode interrupt\n"); 185 return; 186 } 187 188 clk_gmac = fdtbus_clock_get(phandle, "stmmaceth"); 189 clk_in[0] = fdtbus_clock_get(phandle, "clkin0"); 190 clk_in[1] = fdtbus_clock_get(phandle, "clkin1"); 191 if (clk_gmac == NULL || clk_in[0] == NULL || clk_in[1] == NULL) { 192 aprint_error(": couldn't get clocks\n"); 193 return; 194 } 195 196 rst_gmac = fdtbus_reset_get(phandle, "stmmaceth"); 197 198 phy_mode = fdtbus_get_string(phandle, "phy-mode"); 199 if (phy_mode == NULL) { 200 aprint_error(": missing 'phy-mode' property\n"); 201 return; 202 } 203 phandle_phy = fdtbus_get_phandle(phandle, "phy-handle"); 204 if (phandle_phy > 0) { 205 of_getprop_uint32(phandle_phy, "reg", &phy); 206 } else { 207 phandle_phy = phandle; 208 } 209 210 if (strcmp(phy_mode, "rgmii") == 0) { 211 meson_dwmac_set_mode_rgmii(phandle, sc->sc_bst, prgeth_bsh, clk_in[0]); 212 } else if (strcmp(phy_mode, "rmii") == 0) { 213 meson_dwmac_set_mode_rmii(phandle, sc->sc_bst, prgeth_bsh); 214 } else { 215 aprint_error(": unsupported phy-mode '%s'\n", phy_mode); 216 return; 217 } 218 219 if (clk_enable(clk_gmac) != 0) { 220 aprint_error(": couldn't enable clock\n"); 221 return; 222 } 223 224 if (rst_gmac != NULL && fdtbus_reset_deassert(rst_gmac) != 0) { 225 aprint_error(": couldn't de-assert reset\n"); 226 return; 227 } 228 229 aprint_naive("\n"); 230 aprint_normal(": Gigabit Ethernet Controller\n"); 231 232 if (fdtbus_intr_establish_xname(phandle, 0, IPL_NET, 233 DWCGMAC_FDT_INTR_MPSAFE, meson_dwmac_intr, sc, 234 device_xname(sc->sc_dev)) == NULL) { 235 aprint_error_dev(self, "failed to establish interrupt on %s\n", intrstr); 236 return; 237 } 238 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 239 240 if (meson_dwmac_reset(phandle_phy) != 0) 241 aprint_error_dev(self, "PHY reset failed\n"); 242 243 miiclk_rate = clk_get_rate(clk_gmac); 244 if (miiclk_rate > 250 * 1000 * 1000) 245 miiclk = GMAC_MII_CLK_250_300M_DIV124; 246 else if (miiclk_rate > 150 * 1000 * 1000) 247 miiclk = GMAC_MII_CLK_150_250M_DIV102; 248 else if (miiclk_rate > 100 * 1000 * 1000) 249 miiclk = GMAC_MII_CLK_100_150M_DIV62; 250 else if (miiclk_rate > 60 * 1000 * 1000) 251 miiclk = GMAC_MII_CLK_60_100M_DIV42; 252 else if (miiclk_rate > 35 * 1000 * 1000) 253 miiclk = GMAC_MII_CLK_35_60M_DIV26; 254 else 255 miiclk = GMAC_MII_CLK_25_35M_DIV16; 256 257 dwc_gmac_attach(sc, phy, miiclk); 258 } 259 260 CFATTACH_DECL_NEW(meson_dwmac, sizeof(struct dwc_gmac_softc), 261 meson_dwmac_match, meson_dwmac_attach, NULL, NULL); 262